aarch64: Add missing CC clobber to max/min-of-add/sub patterns [PR116815]

*aarch64_plus_within_<optab><mode>3_<ovf_commutate> and
*aarch64_minus_within_<optab><mode>3 split into a flag-setting ADDS or SUBS
followed by a CSEL, but their insn patterns do not say that they write the
condition codes.

For

  unsigned f (unsigned a, unsigned b, unsigned c, unsigned d)
  {
    unsigned s = a + b;
    unsigned m = s > a ? s : a;
    return (c < d && a < b) ? m : d;
  }

combine produces

  (parallel [(set (reg:SI 0 x0)
                  (umax:SI (plus:SI (reg:SI 107) (reg:SI 108))
                           (reg:SI 107)))
             (clobber (scratch:SI))])

which claims to leave the flags alone.  The compare feeding the enclosing
CCMP chain is therefore treated as still live and is removed, and split1
then emits an ADDS that overwrites the flags the outer CSEL reads:

  adds  w1, w0, w1
  csel  w1, w1, w0, cc
  csel  w0, w1, w3, cc

so f (5, 7, 9, 2) returns 12 rather than 2.

Add the (clobber (reg:CC CC_REGNUM)) that the neighbouring
*aarch64_minmax_plus pattern already carries.  The comparison is then kept:

  cmp   w2, w3
  ccmp  w0, w1, 2, cc
  bcs   .L2
  adds  w1, w0, w1
  csel  w3, w1, w0, cc

Bootstrapped and tested on aarch64-none-linux-gnu.

gcc/ChangeLog:

	PR middle-end/116815
	* config/aarch64/aarch64.md
	(*aarch64_plus_within_<optab><mode>3_<ovf_commutate>): Add a
	clobber of CC_REGNUM.
	(*aarch64_minus_within_<optab><mode>3): Likewise.

gcc/testsuite/ChangeLog:

	PR middle-end/116815
	* gcc.target/aarch64/pr116815-4.c: New test.

Signed-off-by: Kyrylo Tkachov <ktkachov@nvidia.com>