[PATCH] RISC-V: PR target/127374 - Zicond improvement for RISC-V

Fix a missed optimization where conditional zeroes based on less-than-or-equal
and greater-than comparisons against immediates generate redundant
Immediate loads.
Add define_split patterns to optimize these if_then_else operations.
Introduce the gt_to_le code attribute to map greater-than conditions to
Less-than-or-equal.
This enables the patterns to utilize the sle_operand predicate, safely splitting the
operations into slti or sltiu evaluations followed by czero.nez or czero.eqz
Instructions.

ASM Before:

    li a5,100
    sgt a0,a0,a5 //  sgtu a0,a0,a5
    czero.nez a0,a1,a0 // czero.eqz a0,a1,a0

ASM after:

    slti a0,a0,101 // sltiu a0,a0,101
    czero.eqz a0,a1,a0 // czero.nez a0,a1,a0

Also, add a new regression test to cover this optimization and
update an existing test to prevent false alarms due to the new
instruction sequence.

	PR target/127374
gcc/ChangeLog:

	* config/riscv/iterators.md (leu): Map gt to le
	* config/riscv/zicond.md: Add define_split patterns

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/czero-bext.c: Change scan assembler
	* gcc.target/riscv/pr127374.c: New test.