RISC-V: Use bext for masked bit-test branches

The branch-specific Zbs split only recognizes bit indices
zero-extended from QImode.  Bit tests with an XLEN-wide index instead
mask the index with XLEN - 1, so combine emits a bset/and pair before
the branch.

BEXT applies the same XLEN - 1 mask to its index.  Match the masked
form only when the mask is exactly XLEN - 1, then split it into bext
and the branch.  With register allocation normalized, the key sequence
changes from:

  bset  t0,zero,a1
  and   a4,t0,t1
  bne   a4,zero,.L

to:

  bext  a4,t1,a1
  bne   a4,zero,.L

This removes one instruction from each affected branch.  On SPEC CPU
2017 Integer 541.leela_r, the measured dynamic instruction count drops
by about 0.5%.

gcc/ChangeLog:

	* config/riscv/bitmanip.md: Split masked bit-test branches into
	BEXT.

gcc/testsuite/ChangeLog:

	* g++.target/riscv/zbs-branch-bext.C: New test.
	* gcc.target/riscv/zbs-branch-bext.c: New test.

Signed-off-by: Jin Ma <jinma@linux.alibaba.com>