aarch64: fix combinez patterns for FP16 types [PR126983]

The combinez patterns for scalar and partial vector operands added in
r17-898-g920eeb67a3537b use the FMOV instruction indiscriminately,
including for scalar FP16 modes in absence of the fp16 extension, causing
assembly failure reported in PR126983.  Fix this by specializing the
patterns for HF and BF modes and using the indexed INS instruction as
fallback.

This patch also adds the new vec-init-23-nofp16.c test, which simply tries
to assemble the testcases from vec-init-23.c without the fp16 extension
(including test_float16_6 that triggers the problem).

Bootstrapped and regtested on aarch64-linux-gnu.

	PR target/126983

gcc/ChangeLog:

	* config/aarch64/aarch64-simd.md (*aarch64_combinez<mode>):
	Split into VS32_I_SUB64_F_CONDFP16 and HFBF variants.  Change
	uxtw to uxt<extsize>.
	(*aarch64_combinez_be<mode>): Likewise.
	* config/aarch64/iterators.md (VSSUB64_F): Remove iterator.
	(VS32_I_SUB64_F): Amend by explicitly listing all modes.
	(VS32_I_SUB64_F_CONDFP16): New iterator.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/vec-init-23-nofp16.c: New test.