RISC-V: Allow RVV register overlap for vwmaccsu.vv

Like vwmacc[u].vv, allow the rvv register overlap for the dual
widen ternary vv insn vwmaccsu.vv, which has the mixed signed
and unsigned narrowed sources.

gcc/ChangeLog:

	* config/riscv/vector.md: Leverage Wvr constraint.

Signed-off-by: Pan Li <pan2.li@intel.com>