Add -ffuse-ops-with-volatile-access: Adjust 'gcc.target/nvptx/alloca-5.c' [PR122343]
With commit r16-5947-ga6c50ec2c6ebcbda2b032eee0552a6a486355e12
"Add -ffuse-ops-with-volatile-access", GCC/nvptx avoids use of intermediate
registers in applicable cases (nice!). This causes one test suite regression:
PASS: gcc.target/nvptx/alloca-5.c (test for excess errors)
XFAIL: gcc.target/nvptx/alloca-5.c execution test
[-PASS:-]{+FAIL:+} gcc.target/nvptx/alloca-5.c check-function-bodies f
PASS: gcc.target/nvptx/alloca-5.c check-function-bodies g
Adjust the FAILing 'check-function-bodies' as per the improved code generation.
PR target/122343
gcc/testsuite/
* gcc.target/nvptx/alloca-5.c: Adjust.
diff --git a/gcc/testsuite/gcc.target/nvptx/alloca-5.c b/gcc/testsuite/gcc.target/nvptx/alloca-5.c
index ada0df0..45aced5 100644
--- a/gcc/testsuite/gcc.target/nvptx/alloca-5.c
+++ b/gcc/testsuite/gcc.target/nvptx/alloca-5.c
@@ -18,12 +18,10 @@
** \.reg\.u32 %value;
** \.reg\.u64 %ar0;
** ld\.param\.u64 %ar0, \[%in_ar0\];
-** \.reg\.u32 (%r[0-9]+);
** \.reg\.u64 (%r[0-9]+);
-** mov\.u64 \2, %ar0;
-** atom\.exch\.b32 \1, \[\2\], 1;
+** mov\.u64 \1, %ar0;
+** atom\.exch\.b32 %value, \[\1\], 1;
** membar\.sys;
-** mov\.u32 %value, \1;
** st\.param\.u32 \[%value_out\], %value;
** ret;
*/
