| commit | 92f46037a0f672d1480f754f76a9bfa0334d099c | [log] [tgz] |
|---|---|---|
| author | Tsukasa OI <research_trasio@irq.a4lg.com> | Wed Aug 02 23:50:27 2023 +0000 |
| committer | Tsukasa OI <research_trasio@irq.a4lg.com> | Thu Aug 03 00:01:31 2023 +0000 |
| tree | 4adfd6c80389f5dc1b0ae0f7f3834bf7836c45aa | |
| parent | 4b177a76d5b759ba631568fb69e8750e99b43647 [diff] |
RISC-V: Imply 'Zicsr' from 'Zve32x' Further clarification is made so that 'Zve32x' implies 'Zicsr' (the same implication is already implemented in LLVM). See related issue (the author raised) on the vector specification: <https://github.com/riscv/riscv-v-spec/issues/908> and its resolution: <https://github.com/riscv/riscv-v-spec/issues/909> bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): Add 'Zve32x' -> 'Zicsr'.