[wip] always compile in cgen logic see if sizeof cgen structs differ in some way.
diff --git a/sim/common/cgen-cpu.h b/sim/common/cgen-cpu.h index d65e0db..6b0f85c 100644 --- a/sim/common/cgen-cpu.h +++ b/sim/common/cgen-cpu.h
@@ -105,6 +105,6 @@ /* Shorthand macro for fetching registers. CPU_CGEN_HW is defined in cpu.h. */ -#define CPU(x) (CPU_CGEN_HW (current_cpu)->x) +//#define CPU(x) (CPU_CGEN_HW (current_cpu)->x) #endif /* CGEN_CPU_H */
diff --git a/sim/common/cgen-defs.h b/sim/common/cgen-defs.h index b9e0c06..ff01705 100644 --- a/sim/common/cgen-defs.h +++ b/sim/common/cgen-defs.h
@@ -20,6 +20,9 @@ #ifndef CGEN_DEFS_H #define CGEN_DEFS_H +#include "opcode/cgen.h" +#include "cgen-types.h" + /* Compute number of longs required to hold N bits. */ #define HOST_LONGS_FOR_BITS(n) \ (((n) + sizeof (long) * 8 - 1) / sizeof (long) * 8)
diff --git a/sim/common/cgen-scache.h b/sim/common/cgen-scache.h index 1043920..29e80832 100644 --- a/sim/common/cgen-scache.h +++ b/sim/common/cgen-scache.h
@@ -20,6 +20,8 @@ #ifndef CGEN_SCACHE_H #define CGEN_SCACHE_H +#include "cgen-types.h" + /* When caching bb's, instructions are extracted into "chains". SCACHE_MAP is a hash table into these chains. */
diff --git a/sim/common/sim-cpu.h b/sim/common/sim-cpu.h index 90e294e..8994a19 100644 --- a/sim/common/sim-cpu.h +++ b/sim/common/sim-cpu.h
@@ -28,9 +28,7 @@ /* Type of function to return an insn name. */ typedef const char * (CPU_INSN_NAME_FN) (sim_cpu *, int); -#ifdef CGEN_ARCH -# include "cgen-cpu.h" -#endif +#include "cgen-cpu.h" /* Types for register access functions. These routines implement the sim_{fetch,store}_register interface. */ @@ -123,11 +121,9 @@ PC_STORE_FN *pc_store; #define CPU_PC_STORE(c) ((c)->pc_store) -#ifdef CGEN_ARCH /* Static parts of cgen. */ CGEN_CPU cgen_cpu; #define CPU_CGEN_CPU(cpu) ((cpu)->cgen_cpu) -#endif /* Pointer for sim target to store arbitrary cpu data. Normally the target should define a struct and use it here. */