aarch64: implement FMUL SME instruction

The SME2.2 extension introduces the following variants of a new
streaming-mode instruction:

- FMUL (Multi-vector floating-point multiply by vector)
- FMUL (Multi-vector floating-point multiply)

The first operand is a multi-vector consisting of two or four vectors, and
the second operand either has the same type, or is a single vector of the
underlying type.  New intrinsics are documented in the ACLE manual [0] and
are as follows:

svfloat{16,32,64}x{2,4}_t svmul[_single_f{16,32,64}_x{2,4}]
  (svfloat{16,32,64}x{2,4}_t zd, svfloat{16,32,64}_t zm) __arm_streaming;

svfloat{16,32,64}x{2,4}_t svmul[_f{16,32,64}_x{2,4}]
  (svfloat{16,32,64}x{2,4}_t zd, svfloat{16,32,64}x{2,4}_t zm) __arm_streaming;

This patch implements the above changes throughout the SVE builtin
description files and aarch64-sve2.md.

[0] https://github.com/ARM-software/acle

gcc/ChangeLog:

	* config/aarch64/aarch64-sve-builtins-sve2.def (svmul): Define new
	SVE function variant.
	* config/aarch64/aarch64-sve2.md (@aarch64_sve_<optab><mode>): New
	instruction pattern.
	(@aarch64_sve_<optab><mode>_single): Likewise.
	* config/aarch64/aarch64.h (TARGET_STREAMING_SME2p2): New macro.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/sme2/acle-asm/mul_f16_x2.c: New test.
	* gcc.target/aarch64/sme2/acle-asm/mul_f16_x4.c: Likewise.
	* gcc.target/aarch64/sme2/acle-asm/mul_f32_x2.c: Likewise.
	* gcc.target/aarch64/sme2/acle-asm/mul_f32_x4.c: Likewise.
	* gcc.target/aarch64/sme2/acle-asm/mul_f64_x2.c: Likewise.
	* gcc.target/aarch64/sme2/acle-asm/mul_f64_x4.c: Likewise.