RISC-V: Support Sscounterenw extension.

Support the Sscounterenw extension, which allows writeable enables for any
supported counter.

gcc/ChangeLog:

	* config/riscv/riscv-ext.def: New extension definition.
	* config/riscv/riscv-ext.opt: New extension mask.
	* doc/riscv-ext.texi: Document the new extension.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/arch-sscounterenw.c: New test.

Signed-off-by: Jiawei <jiawei@iscas.ac.cn>