RISC-V: Support Sscounterenw extension.

Support the Sscounterenw extension, which allows writeable enables for any
supported counter.

gcc/ChangeLog:

	* config/riscv/riscv-ext.def: New extension definition.
	* config/riscv/riscv-ext.opt: New extension mask.
	* doc/riscv-ext.texi: Document the new extension.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/arch-sscounterenw.c: New test.

Signed-off-by: Jiawei <jiawei@iscas.ac.cn>

gcc/config/riscv/riscv-ext.def

diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def
index ec0a08c..dab8cb8 100644
--- a/gcc/config/riscv/riscv-ext.def
+++ b/gcc/config/riscv/riscv-ext.def
@@ -1832,6 +1832,19 @@
   /* EXTRA_EXTENSION_FLAGS */ 0)
 
 DEFINE_RISCV_EXT(
+  /* NAME */ sscounterenw,
+  /* UPPERCASE_NAME */ SSCOUNTERENW,
+  /* FULL_NAME */ "Support writeable enables for any supported counter",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({"zicsr"}),
+  /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+  /* FLAG_GROUP */ ss,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
+DEFINE_RISCV_EXT(
   /* NAME */ sscsrind,
   /* UPPERCASE_NAME */ SSCSRIND,
   /* FULL_NAME */ "Supervisor-Level Indirect CSR Access",

gcc/config/riscv/riscv-ext.opt

diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt
index f851678..ad9e1d6 100644
--- a/gcc/config/riscv/riscv-ext.opt
+++ b/gcc/config/riscv/riscv-ext.opt
@@ -359,6 +359,8 @@
 
 Mask(SSCOFPMF) Var(riscv_ss_subext)
 
+Mask(SSCOUNTERENW) Var(riscv_ss_subext)
+
 Mask(SSCSRIND) Var(riscv_ss_subext)
 
 Mask(SSNPM) Var(riscv_ss_subext)

gcc/doc/riscv-ext.texi

diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi
index 83aa436..2b23366 100644
--- a/gcc/doc/riscv-ext.texi
+++ b/gcc/doc/riscv-ext.texi
@@ -542,6 +542,10 @@
 @tab 1.0
 @tab Count overflow & filtering extension
 
+@item sscounterenw
+@tab 1.0
+@tab Support writeable enables for any supported counter
+
 @item sscsrind
 @tab 1.0
 @tab Supervisor-Level Indirect CSR Access

gcc/testsuite/gcc.target/riscv/arch-sscounterenw.c

diff --git a/gcc/testsuite/gcc.target/riscv/arch-sscounterenw.c b/gcc/testsuite/gcc.target/riscv/arch-sscounterenw.c
new file mode 100644
index 0000000..901b6bc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-sscounterenw.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_sscounterenw -mabi=lp64" } */
+int foo()
+{
+}