RISC-V: Allow RVV register overlap for vwmaccu.vx undef

Like vwmacc[u].vx, allow the rvv register overlap for the undef
form of the dual widen ternary vx insn vwmaccu.vx.  The undef form
comes from the combine of the vec_duplicate and the vwmaccu.vv
instead of the intrinsic.  After that, all the dual widen ternary
vx insns are able to overlap.

gcc/ChangeLog:

	* config/riscv/vector.md: Leverage Wvr constraint.

Signed-off-by: Pan Li <pan2.li@intel.com>