RISC-V: Fix reg overlap for vs1 of the widening integer reduction

The vs1 of the widening reduction (aka vwredsum[u].vs) is read with
EEW = 2 * SEW while the vs2 is read with EEW = SEW.  The section 5.2
of the vector spec reserves any encoding in which one vector register
supplies source operands with two or more different EEWs.  Thus, the
vs1 must not fall inside the vs2 register group, but we may have below
asm dump when the vs1 comes from the vs2 register group.

  vwredsum.vs v2,v2,v3

Add one new constraint Wn3 which indicates the register of the operand
doesn't overlap the register group of the operand 3 (aka vs2), and then
take it for the operand 4 (aka vs1) of the widening integer reduction.
See below issue of the riscv-isa-manual for more details.

  https://github.com/riscv/riscv-isa-manual/issues/2350

gcc/ChangeLog:

	* config/riscv/constraints.md (Wn3): New constraint for the
	vector register which doesn't overlap the register group of
	the operand 3.
	* config/riscv/riscv-protos.h (riscv_v_widen_non_overlap_constraint_ok):
	New function declaration.
	* config/riscv/riscv-v.cc (riscv_v_reg_group_overlap_p): New
	function to tell if two vector register groups overlap.
	(riscv_v_widen_constraint_ok): Leverage the above function for
	the register group overlap check.
	(riscv_v_widen_non_overlap_constraint_ok): New function to tell
	if the register doesn't overlap the reference register group.
	* config/riscv/vector.md: Take the Wn3 constraint for the
	operand 4 of the widening integer reduction.

Signed-off-by: Pan Li <pan2.li@intel.com>