RISC-V: Add intrinsic support for Zvabd

This commit adds intrinsic support for Zvabd.  The original vwabad
machine description pattern would cause an ICE when emitting the
intrinsic because operand 0 and operand 2 are different pseudos,
and operand 2 has a constraint of "0", while operand 0 is marked as
read-write "+".  The vwmacc-like pattern is now used to support correct
intrinsic generation and to better reflect the semantics.  Pan Li's new
overlap constraint is used according to Robin's review comments of v2.

gcc/ChangeLog:

	* config/riscv/autovec-opt.md: Match the new vwmacc-like pattern.
	* config/riscv/genrvv-type-indexer.cc: Support
	DOUBLE_TRUNC_SIGNED type for v[u]int types.
	* config/riscv/riscv-vector-builtins-bases.cc (class vabd): New
	class.
	(class vabs): Ditto.
	(class vabda): Ditto.
	(BASE): Define.
	* config/riscv/riscv-vector-builtins-bases.h: Ditto.
	* config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
	Ditto.
	(vabs): Ditto.
	(vabd): Ditto.
	(vabdu): Ditto.
	(vwabda): Ditto.
	(vwabdau): Ditto.
	* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_QU_HU_OPS):
	Define.
	(DEF_RVV_HU_SU_OPS): Ditto.
	* config/riscv/riscv-vector-builtins.cc (qu_hu_ops): Ditto.
	(hu_su_ops): Ditto.
	(ss_args): Ditto.
	(wwss_args): Ditto.
	(qu_hu_vss_ops): Ditto
	(qu_hu_vvv_ops): Ditto
	(hu_su_wwss_ops): Ditto
	(hu_su_wwvv_ops): Ditto
	(u_s_ops): Ditto
	(get_builtin_partition): Add Zvabd case.
	* config/riscv/riscv-vector-builtins.h (enum required_ext):
	Ditto.
	(enum rvv_builtin_partition): Ditto.
	(required_ext_to_isa_name): Ditto.
	(required_extensions_specified): Ditto.
	* config/riscv/riscv_vector.h (__riscv_intrinsic_zvabd): Define.
	* config/riscv/vector.md: Rewrite pred_widen_abd_plus as
	vwmacc-like form.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/intrinsic-detection.c: Add Zvabd.
	* gcc.target/riscv/rvv/base/zvabd-intrinsic.c: New test.