| /* Definition of RISC-V target for GNU compiler. |
| Copyright (C) 2016-2021 Free Software Foundation, Inc. |
| Contributed by Andrew Waterman (andrew@sifive.com). |
| |
| This file is part of GCC. |
| |
| GCC is free software; you can redistribute it and/or modify |
| it under the terms of the GNU General Public License as published by |
| the Free Software Foundation; either version 3, or (at your option) |
| any later version. |
| |
| GCC is distributed in the hope that it will be useful, |
| but WITHOUT ANY WARRANTY; without even the implied warranty of |
| MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| GNU General Public License for more details. |
| |
| You should have received a copy of the GNU General Public License |
| along with GCC; see the file COPYING3. If not see |
| <http://www.gnu.org/licenses/>. */ |
| |
| #ifndef GCC_RISCV_OPTS_H |
| #define GCC_RISCV_OPTS_H |
| |
| enum riscv_abi_type { |
| ABI_ILP32, |
| ABI_ILP32E, |
| ABI_ILP32F, |
| ABI_ILP32D, |
| ABI_LP64, |
| ABI_LP64F, |
| ABI_LP64D |
| }; |
| extern enum riscv_abi_type riscv_abi; |
| |
| enum riscv_code_model { |
| CM_MEDLOW, |
| CM_MEDANY, |
| CM_PIC |
| }; |
| extern enum riscv_code_model riscv_cmodel; |
| |
| enum riscv_isa_spec_class { |
| ISA_SPEC_CLASS_NONE, |
| |
| ISA_SPEC_CLASS_2P2, |
| ISA_SPEC_CLASS_20190608, |
| ISA_SPEC_CLASS_20191213 |
| }; |
| |
| extern enum riscv_isa_spec_class riscv_isa_spec; |
| |
| /* Keep this list in sync with define_attr "tune" in riscv.md. */ |
| enum riscv_microarchitecture_type { |
| generic, |
| sifive_7 |
| }; |
| extern enum riscv_microarchitecture_type riscv_microarchitecture; |
| |
| enum riscv_align_data { |
| riscv_align_data_type_xlen, |
| riscv_align_data_type_natural |
| }; |
| |
| /* Where to get the canary for the stack protector. */ |
| enum stack_protector_guard { |
| SSP_TLS, /* per-thread canary in TLS block */ |
| SSP_GLOBAL /* global canary */ |
| }; |
| |
| #define MASK_ZICSR (1 << 0) |
| #define MASK_ZIFENCEI (1 << 1) |
| |
| #define TARGET_ZICSR ((riscv_zi_subext & MASK_ZICSR) != 0) |
| #define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0) |
| |
| #define MASK_ZBA (1 << 0) |
| #define MASK_ZBB (1 << 1) |
| #define MASK_ZBC (1 << 2) |
| #define MASK_ZBS (1 << 3) |
| |
| #define TARGET_ZBA ((riscv_zb_subext & MASK_ZBA) != 0) |
| #define TARGET_ZBB ((riscv_zb_subext & MASK_ZBB) != 0) |
| #define TARGET_ZBC ((riscv_zb_subext & MASK_ZBC) != 0) |
| #define TARGET_ZBS ((riscv_zb_subext & MASK_ZBS) != 0) |
| |
| #endif /* ! GCC_RISCV_OPTS_H */ |