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gnu/gcc/be2f50cff66daf13e5109c9d8369e9aee255a136/./gcc/ChangeLog
blob: 78cf5e3b681abd7bdbf622860683cbac3fa94302 [file]
2025-10-17 Hu, Lin1 <lin1.hu@intel.com>
PR target/122119
* config/i386/amxmovrsintrin.h
(_tile_loaddrs_internal): Use __PTRDIFF_TYPE__ instead of long.
(_tile_loaddrst1_internal): Ditto.
(_tile_2rpntlvwz0rs_internal): Ditto.
(_tile_2rpntlvwz0rst1_internal): Ditto.
(_tile_2rpntlvwz1rs_internal): Ditto.
(_tile_2rpntlvwz1rst1_internal): Ditto.
2025-10-16 Ayappan Perumal <ayappap2@in.ibm.com>
Backported from master:
2025-10-16 Ayappan Perumal <ayappap2@in.ibm.com>
* config/rs6000/aix.h (SUBTARGET_DRIVER_SELF_SPECS):
Error out when stack-protector option is used in AIX
as it is not supported on AIX
Approved By: Segher Boessenkool <segher@kernel.crashing.org>
2025-10-15 Alice Carlotti <alice.carlotti@arm.com>
* config/aarch64/aarch64-sys-regs.def: Fix pmsdsfr_el1 encoding.
2025-10-15 Haochen Jiang <haochen.jiang@intel.com>
* config/i386/i386.h
(PTA_PANTHERLAKE): Remove PREFETCHI.
(PTA_DIAMONDRAPIDS): Remove USER_MSR.
* doc/invoke.texi: Correct documentation.
2025-10-14 Jakub Jelinek <jakub@redhat.com>
Backported from master:
2025-10-06 Jakub Jelinek <jakub@redhat.com>
PR middle-end/122133
* stmt.cc (resolve_asm_operand_names): Handle % and 2 letters followed
by open square.
2025-10-14 Jakub Jelinek <jakub@redhat.com>
Backported from master:
2025-10-04 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/122104
* tree-ssa-math-opts.cc (maybe_optimize_guarding_check): Call
reset_flow_sensitive_info_in_bb on bb when optimizing out the
guarding condition.
2025-10-14 Haochen Jiang <haochen.jiang@intel.com>
* config/i386/i386.h (PTA_DIAMONDRAPIDS): Remove AMX-TRANSPOSE.
* doc/invoke.texi: Correct documentation.
2025-10-13 Avinash Jayakar <avinashd@linux.ibm.com>
PR tree-optimization/122213
* match.pd: Canonicalize unsigned pow2 div only for trunk, floor and
exact div.
2025-10-11 Robin Dapp <rdapp.gcc@gmail.com>
Backported from master:
2025-10-07 Robin Dapp <rdapp.gcc@gmail.com>
PR target/121845
* config/riscv/riscv-v.cc (shuffle_series_patterns):
Modulo indices for VLA and punt when wrapping for VLS.
2025-10-08 Aurelien Jarno <aurelien@aurel32.net>
Backported from master:
2025-10-02 Aurelien Jarno <aurelien@aurel32.net>
PR target/121652
* config/riscv/riscv.md (round_pattern): special case NaN input
instead of saving/restoring fflags.
2025-10-07 Georg-Johann Lay <avr@gjlay.de>
Backported from master:
2025-10-07 Georg-Johann Lay <avr@gjlay.de>
PR target/122187
* config/avr/avr.cc (avr_out_extr, avr_out_extr_not):
Make a local copy of the passed rtx[] operands.
2025-10-03 Robin Dapp <rdapp@ventanamicro.com>
Backported from master:
2025-09-04 Robin Dapp <rdapp@ventanamicro.com>
PR target/121742
PR target/121780
PR target/121781
* config/riscv/riscv-v.cc (expand_vec_perm): Swap target and
tmp_target.
2025-10-03 Robin Dapp <rdapp@ventanamicro.com>
Backported from master:
2025-09-02 Robin Dapp <rdapp@ventanamicro.com>
PR target/121742
* config/riscv/riscv-v.cc (expand_vec_perm): Use temporary if
op1 and target overlap.
2025-10-02 Kito Cheng <kito.cheng@sifive.com>
PR target/110812
* config/riscv/riscv-c.cc (pragma_intrinsic_flags): Remove struct.
(riscv_pragma_intrinsic_flags_pollute): Remove function.
(riscv_pragma_intrinsic_flags_restore): Remove function.
(riscv_pragma_intrinsic): Simplify to only call handle_pragma_vector.
* config/riscv/riscv-vector-builtins.cc (pragma_intrinsic_flags):
Move struct definition here from riscv-c.cc.
(riscv_pragma_intrinsic_flags_pollute): Move and adapt from
riscv-c.cc, add zvfbfmin, zvfhmin and vector_elen_bf_16 support.
(riscv_pragma_intrinsic_flags_restore): Move from riscv-c.cc.
(rvv_switcher::rvv_switcher): Add pollute_flags parameter to
control flag manipulation.
(rvv_switcher::~rvv_switcher): Restore flags conditionally.
(register_builtin_types): Use rvv_switcher without polluting flags.
(get_required_extensions): Remove function.
(check_required_extensions): Simplify to only check type validity.
(function_instance::function_returns_void_p): Move implementation
from header.
(function_builder::add_function): Register placeholder for LTO.
(init_builtins): Simplify and handle LTO case.
(reinit_builtins): Remove function.
(handle_pragma_vector): Remove extension checking.
* config/riscv/riscv-vector-builtins.h
(function_instance::function_returns_void_p): Add declaration.
(function_call_info::function_returns_void_p): Remove inline
implementation.
2025-09-26 Lulu Cheng <chenglulu@loongson.cn>
Backported from master:
2025-09-26 Lulu Cheng <chenglulu@loongson.cn>
PR target/121875
* config/loongarch/loongarch.cc
(loongarch_can_inline_p): New function.
(TARGET_CAN_INLINE_P): Define.
2025-09-25 Alex Coplan <alex.coplan@arm.com>
Backported from master:
2025-09-15 Alex Coplan <alex.coplan@arm.com>
PR tree-optimization/121772
* match.pd: Add type check to reduc(ctor) pattern.
2025-09-25 Tobias Burnus <tburnus@baylibre.com>
Backported from master:
2025-09-18 Tobias Burnus <tburnus@baylibre.com>
Sandra Loosemore <sloosemore@baylibre.com>
PR middle-end/121922
* omp-general.cc (omp_dynamic_cond): Use 'unshare_expr' for
the user condition.
2025-09-24 Jakub Jelinek <jakub@redhat.com>
Backported from master:
2025-09-18 Jakub Jelinek <jakub@redhat.com>
PR c++/121977
* omp-low.cc (lower_omp_regimplify_operands_p): If maybe_lookup_decl
returns NULL, use maybe_lookup_decl_in_outer_ctx as fallback.
2025-09-24 Jakub Jelinek <jakub@redhat.com>
Backported from master:
2025-09-16 Jakub Jelinek <jakub@redhat.com>
* doc/invoke.texi (Wimplicit-fallthrough=): Document that also C23
provides a standard way to suppress the warning with [[fallthrough]];.
2025-09-24 Jakub Jelinek <jakub@redhat.com>
Backported from master:
2025-09-10 Jakub Jelinek <jakub@redhat.com>
PR middle-end/121828
* gimple-lower-bitint.cc (gimple_lower_bitint): For REALPART_EXPR
consumed by store in the same bb and with REALPART_EXPR from
optimizable_arith_overflow, don't add REALPART_EXPR lhs to
the m_names bitmap only if the cast from IMAGPART_EXPR doesn't
appear in between the REALPART_EXPR and the store.
2025-09-24 Jakub Jelinek <jakub@redhat.com>
Backported from master:
2025-09-10 Jakub Jelinek <jakub@redhat.com>
PR middle-end/121831
* expr.cc (raw_data_cst_read_str): New function.
(store_constructor) <case ARRAY_TYPE>: Handle RAW_DATA_CST.
2025-09-24 Jakub Jelinek <jakub@redhat.com>
Backported from master:
2025-08-25 Jakub Jelinek <jakub@redhat.com>
PR middle-end/121453
* omp-expand.cc (expand_omp_for_init_counts): Clear fd->loop.n2
before first zero count check if zero_iter1_bb is non-NULL upon
entry and fd->loop.n2 has not been written yet.
2025-09-24 Richard Biener <rguenther@suse.de>
Backported from master:
2025-09-22 Richard Biener <rguenther@suse.de>
PR tree-optimization/122016
* tree-ssa-sccvn.cc (vn_nary_simplify): Do not use the
simplified expression when it references abnormals.
2025-09-24 Richard Biener <rguenther@suse.de>
Backported from master:
2025-09-11 Richard Biener <rguenther@suse.de>
PR tree-optimization/121870
* tree-ssa-propagate.cc
(substitute_and_fold_engine::substitute_and_fold): Skip
removed stmts from noreturn fixup.
2025-09-24 Richard Biener <rguenther@suse.de>
Backported from master:
2025-09-08 Richard Biener <rguenther@suse.de>
PR tree-optimization/107997
PR tree-optimization/121844
* tree-ssa-loop-ivopts.cc (allow_ip_end_pos_p): Do not allow
IP_END for latches ending with a control stmt.
(create_new_iv): Do not split the latch edge, instead assert
that's not necessary.
2025-09-24 Richard Biener <rguenther@suse.de>
Backported from master:
2025-08-26 Richard Biener <rguenther@suse.de>
PR tree-optimization/121659
* tree-vect-slp.cc (vect_build_slp_tree_1): Do not allow
matching up comparison operators by swapping if that would
disturb STMT_VINFO_REDUC_IDX. Make sure to only
actually mark operands for swapping when there was a
mismatch and we're not processing the first stmt.
2025-09-24 Richard Biener <rguenther@suse.de>
Backported from master:
2025-08-19 Richard Biener <rguenther@suse.de>
PR tree-optimization/121527
* tree-sra.cc (build_access_from_expr_1): Do not strip an
outer VIEW_CONVERT_EXPR as it's relevant for the size of
the access.
(get_access_for_expr): Likewise.
2025-09-24 Richard Biener <rguenther@suse.de>
Backported from master:
2025-08-05 Richard Biener <rguenther@suse.de>
PR tree-optimization/121370
* tree-scalar-evolution.cc (scev_dfs::add_to_evolution_1):
Avoid UB integer overflow in accumulating CHREC_RIGHT.
2025-09-20 Michael Eager <eager@eagercon.com>
PR target/118280
* config/microblaze/iterators.md: New.
* config/microblaze/microblaze-protos.h: Add
microblaze_subword_address.
* config/microblaze/microblaze.cc: Ditto.
* config/microblaze/microblaze.md: constants: Add UNSPECV_CAS_BOOL,
UNSPECV_CAS_MEM, UNSPECV_CAS_VAL, UNSPECV_ATOMIC_FETCH_OP
type: add atomic
* config/microblaze/sync.md: Add atomic_fetch_<atomic_optab>si
atomic_test_and_set
2025-09-18 hongtao.liu <hongtao.liu@intel.com>
Backported from master:
2025-09-18 hongtao.liu <hongtao.liu@intel.com>
* config/i386/x86-tune.def (X86_TUNE_AVX512_MOVE_BY_PIECES):
Remove SPR/GNR/DMR.
(X86_TUNE_AVX512_STORE_BY_PIECES): Ditto.
2025-09-16 Jeff Law <jlaw@ventanamicro.com>
Backported from master:
2025-09-12 Jeff Law <jlaw@ventanamicro.com>
* lra-constraints.cc (get_equiv): Bounds check before accessing
data in ira_reg_equiv.
2025-09-16 Jennifer Schmitz <jschmitz@nvidia.com>
PR target/121602
* config/aarch64/aarch64-sve-builtins.cc
(gimple_folder::fold_active_lanes_to): Add force_vector
statement.
2025-09-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
Backported from master:
2025-08-11 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR target/121464
* config/arm/arm.md (arm_<mrrc>, arm_<mcrr>): Fix operand check.
2025-09-15 Kyrylo Tkachov <ktkachov@nvidia.com>
Backported from master:
2025-09-03 Kyrylo Tkachov <ktkachov@nvidia.com>
PR target/121749
* config/aarch64/aarch64-simd.md (aarch64_<shrn_op>shrn_n<mode>):
Use aarch64_simd_shift_imm_offset_<vn_mode> instead of
aarch64_simd_shift_imm_offset_<ve_mode> predicate.
(aarch64_<shrn_op>shrn_n<mode> VQN define_expand): Likewise.
(*aarch64_<shrn_op>rshrn_n<mode>_insn): Likewise.
(aarch64_<shrn_op>rshrn_n<mode>): Likewise.
(aarch64_<shrn_op>rshrn_n<mode> VQN define_expand): Likewise.
(aarch64_sqshrun_n<mode>_insn): Likewise.
(aarch64_sqshrun_n<mode>): Likewise.
(aarch64_sqshrun_n<mode> VQN define_expand): Likewise.
(aarch64_sqrshrun_n<mode>_insn): Likewise.
(aarch64_sqrshrun_n<mode>): Likewise.
(aarch64_sqrshrun_n<mode>): Likewise.
* config/aarch64/iterators.md (vn_mode): Handle DI, SI, HI modes.
2025-09-15 Georg-Johann Lay <avr@gjlay.de>
Backported from master:
2025-09-15 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr-mcus.def: Add avr32eb14, avr32eb20,
avr32eb28, avr32eb32.
* doc/avr-mmcu.texi: Rebuild.
2025-09-15 Xi Ruoyao <xry111@xry111.site>
Backported from master:
2025-09-15 Xi Ruoyao <xry111@xry111.site>
PR target/121906
* config/loongarch/loongarch.md (*bstrins_<mode>_for_ior_mask):
Always create a new pseudo for the input register of the bstrins
instruction.
2025-09-11 Richard Sandiford <rdsandiford@googlemail.com>
PR rtl-optimization/121757
* rtl-ssa/accesses.h (clobber_group::lookup_clobber): New member
function.
* rtl-ssa/accesses.cc (clobber_group::lookup_clobber): Likewise.
(clobber_group::prev_clobber, clobber_group::next_clobber)
(function_info::add_clobber): Use it.
2025-09-10 Georg-Johann Lay <avr@gjlay.de>
Backported from master:
2025-09-10 Georg-Johann Lay <avr@gjlay.de>
PR target/81540
PR target/49857
* common/config/avr/avr-common.cc: Disable -ftree-switch-conversion.
2025-09-08 Robin Dapp <rdapp@ventanamicro.com>
Backported from master:
2025-09-05 Robin Dapp <rdapp@ventanamicro.com>
PR target/121510
* config/riscv/riscv.cc (riscv_legitimize_move): Check if we can
vec_extract.
2025-09-07 Georg-Johann Lay <avr@gjlay.de>
Backported from master:
2025-09-07 Georg-Johann Lay <avr@gjlay.de>
PR target/121794
* config/avr/avr.md (cmpqi3): Use cpi R,0 if possible.
2025-09-05 Georg-Johann Lay <avr@gjlay.de>
Backported from master:
2025-09-05 Georg-Johann Lay <avr@gjlay.de>
PR target/121794
* config/avr/avr.cc (avr_out_compare): Only use zero_reg
when there is no other sequence of the same length.
(avr_out_plus_ext): Same.
(avr_out_plus_1): Same.
2025-09-02 Jeff Law <jlaw@ventanamicro.com>
Backported from master:
2025-08-29 Jeff Law <jlaw@ventanamicro.com>
PR target/121548
* config/riscv/riscv-avlprop.cc (get_insn_vtype_mode): Assert
MODE_IDX is smaller than the number of operands.
(simplify_replace_vlmax_avl): Similarly.
(pass_avlprop::get_vlmax_ta_preferred_avl): Similarly.
* config/riscv/vector.md: Override merge_op_idx computation
for simple moves, just like is done for avl_type_idx and mode_idx.
2025-09-01 Mark Harmstone <mark@harmstone.com>
* dwarf2codeview.cc (get_type_num_array_type): Don't try to
encode non-C-style arrays.
2025-08-31 Benjamin Wu <bwu25@cs.washington.edu>
Backported from master:
2025-07-13 Benjamin Wu <bwu25@cs.washington.edu>
* gimple.h (GTMA_DOES_GO_IRREVOCABLE): Fix typo.
2025-08-25 Xi Ruoyao <xry111@xry111.site>
Backported from master:
2025-08-25 Xi Ruoyao <xry111@xry111.site>
PR target/121634
* config/loongarch/simd.md (simd_maddw_evod_<mode>_<su>): Use
WVEC_HALF instead of WVEC for the mode of the sign_extend for
the rhs of multiplication.
2025-08-22 Sebastian Huber <sebastian.huber@embedded-brains.de>
Backported from master:
2025-08-22 Sebastian Huber <sebastian.huber@embedded-brains.de>
* config/riscv/t-rtems: Add -mstrict-align multilibs for
targets without support for misaligned access in hardware.
2025-08-20 Georg-Johann Lay <avr@gjlay.de>
Backported from master:
2025-08-20 Georg-Johann Lay <avr@gjlay.de>
PR target/121608
* config/avr/specs.h (LINK_RELAX_SPEC): Wrap in %{!r...}.
2025-08-20 Vineet Gupta <vineetg@rivosinc.com>
PR target/121534
* config/riscv/riscv.md (round_pattern): save/restore fflags.
2025-08-18 Richard Sandiford <richard.sandiford@arm.com>
PR target/121118
* config/aarch64/aarch64.cc (aarch64_sve_move_pred_via_while):
Return a VNx16BI predicate.
2025-08-18 Richard Sandiford <richard.sandiford@arm.com>
Backported from master:
2025-08-12 Richard Sandiford <richard.sandiford@arm.com>
PR rtl-optimization/121253
* fwprop.cc (forward_propagate_into): Don't propagate asm defs.
2025-08-15 Alex Coplan <alex.coplan@arm.com>
Backported from master:
2025-08-08 Alex Coplan <alex.coplan@arm.com>
PR target/120986
* config/aarch64/aarch64-sve-builtins.cc
(function_expander::expand): Relax fpm_t assert to allow
modeless const_ints.
2025-08-15 Alex Coplan <alex.coplan@arm.com>
Backported from master:
2025-08-08 Alex Coplan <alex.coplan@arm.com>
PR target/120986
* config/aarch64/aarch64-sve2.md (@aarch64_sve_dot<mode>):
Switch mode iterator from SVE_FULL_HSF to new iterator;
remove insn predicate as this is now taken care of by conditions
in the mode iterator.
(@aarch64_sve_dot_lane<mode>): Likewise.
* config/aarch64/iterators.md (SVE_FULL_HSF_FP8_FDOT): New.
2025-08-15 Pengfei Li <Pengfei.Li2@arm.com>
PR target/121449
* config/aarch64/aarch64-sve.md
(mask_gather_load<mode><v_int_container>): Use vg<Vesize>
constraints for alternatives with immediate offset.
(mask_scatter_store<mode><v_int_container>): Likewise.
2025-08-15 Lulu Cheng <chenglulu@loongson.cn>
Backported from master:
2025-08-15 Lulu Cheng <chenglulu@loongson.cn>
PR target/121542
* config/loongarch/loongarch.cc
(loongarch_vector_costs::add_stmt_cost): When using vectype,
first determine whether it is NULL.
2025-08-14 Richard Sandiford <richard.sandiford@arm.com>
PR target/121414
* config/aarch64/aarch64.cc (aarch64_is_variant_pcs): New function,
split out from...
(aarch64_asm_output_variant_pcs): ...here. Handle various types
of SME function type.
2025-08-14 Richard Sandiford <richard.sandiford@arm.com>
PR target/121294
* config/aarch64/aarch64.md (UNSPEC_REV_PRED): New unspec.
* config/aarch64/aarch64-sve.md (@aarch64_sve_rev<mode>_acle)
(*aarch64_sve_rev<mode>_acle): New patterns.
* config/aarch64/aarch64-sve-builtins-base.cc
(svrev_impl::expand): Use the new patterns for boolean svrev.
2025-08-14 Richard Sandiford <richard.sandiford@arm.com>
PR target/121294
* config/aarch64/iterators.md (UNSPEC_TRN1_CONV): Delete.
(UNSPEC_PERMUTE_PRED): New unspec.
* config/aarch64/aarch64-sve.md (@aarch64_sve_trn1_conv<mode>):
Replace with...
(@aarch64_sve_<perm_insn><mode>_acle)
(*aarch64_sve_<perm_insn><mode>_acle): ...these new patterns.
* config/aarch64/aarch64.cc (aarch64_expand_sve_const_pred_trn):
Update accordingly.
* config/aarch64/aarch64-sve-builtins-functions.h
(binary_permute::expand): Use the new _acle patterns for
predicate operations.
2025-08-14 Richard Sandiford <richard.sandiford@arm.com>
PR rtl-optimization/120718
* simplify-rtx.cc (simplify_context::simplify_gen_subreg):
Remove MODE_COMPOSITE_P condition.
2025-08-14 Vladimir N. Makarov <vmakarov@redhat.com>
PR target/121007
* lra-constraints.cc (process_address_1): When changing base reg
on a reg of the base class, fall back to reload of whole inner address.
(process_address): Constrain the iteration number.
2025-08-14 Andrew Pinski <quic_apinski@quicinc.com>
Backported from master:
2025-06-22 Andrew Pinski <quic_apinski@quicinc.com>
PR target/119830
* config/riscv/riscv.cc (riscv_build_integer_1): Make arithmetic in bclr case
clean for 32 bit hosts.
2025-08-14 H.J. Lu <hjl.tools@gmail.com>
Backported from master:
2025-07-28 H.J. Lu <hjl.tools@gmail.com>
PR target/121208
* config/i386/i386.cc (ix86_tls_get_addr): Issue an error for
-mtls-dialect=gnu with no_caller_saved_registers attribute and
suggest -mtls-dialect=gnu2.
2025-08-13 Richard Sandiford <richard.sandiford@arm.com>
Backported from master:
2025-07-17 Richard Sandiford <richard.sandiford@arm.com>
Yury Khrustalev <yury.khrustalev@arm.com>
* doc/sourcebuild.texi (aarch64_sme_hw): Document.
2025-08-13 Lulu Cheng <chenglulu@loongson.cn>
Backported from master:
2025-08-13 Lulu Cheng <chenglulu@loongson.cn>
PR target/120476
* config/loongarch/loongarch.cc
(loongarch_compute_pressure_classes): New function.
(TARGET_COMPUTE_PRESSURE_CLASSES): Define.
2025-08-12 mengqinggang <mengqinggang@loongson.cn>
Backported from master:
2025-08-12 mengqinggang <mengqinggang@loongson.cn>
* config/loongarch/loongarch-def.h (ABI_BASE_LP64D): New macro.
(ABI_BASE_LP64F): New macro.
(ABI_BASE_LP64S): New macro.
(N_ABI_BASE_TYPES): New macro.
2025-08-10 Xi Ruoyao <xry111@xry111.site>
Backported from master:
2025-07-12 Xi Ruoyao <xry111@xry111.site>
PR rtl-optimization/120983
* lra-constraints.cc (process_alt_operands): Allow reloading
user hard registers unless the insn is an asm.
2025-08-08 Jakub Jelinek <jakub@redhat.com>
Backported from master:
2025-08-08 Jakub Jelinek <jakub@redhat.com>
PR middle-end/121389
* tree-tailcall.cc (find_tail_calls): For finally_tmp.N
handle not just GIMPLE_CONDs with EQ_EXPR/NE_EXPR and only
values 0 and 1, but arbitrary non-negative values, arbitrary
comparisons in conditions and also GIMPLE_SWITCH next to
GIMPLE_CONDs.
2025-08-08 Jakub Jelinek <jakub@redhat.com>
Backported from master:
2025-08-06 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/121413
* gimple-lower-bitint.cc (abi_limb_prec): New variable
(bitint_precision_kind): Initialize it.
(gimple_lower_bitint): Clear it at the start. For
min_prec > limb_prec descreased precision vars for
INTEGER_CST PHI arguments ensure min_prec is either
prec or multiple of abi_limb_prec.
2025-08-08 Jakub Jelinek <jakub@redhat.com>
Backported from master:
2025-08-06 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/121127
* gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr): For
uninitialized SSA_NAME, set *prec_stored to 0 rather than *prec.
Handle that case in narrowing casts. If prec_stored is non-NULL,
set *prec_stored to prec_stored_val.
2025-08-08 Release Manager
* GCC 15.2.0 released.
2025-08-07 Uros Bizjak <ubizjak@gmail.com>
Backported from master:
2025-08-06 Uros Bizjak <ubizjak@gmail.com>
PR target/96226
* config/i386/predicates.md (and_operator): New operator.
* config/i386/i386.md (splitter after *<rotate_insn><mode>3_mask):
Use and_operator to match AND RTX and use its mode
in the split pattern.
2025-08-01 Richard Earnshaw <rearnsha@arm.com>
Backported from master:
2025-05-19 Richard Earnshaw <rearnsha@arm.com>
PR target/120351
* config/arm/predicates.md (mem_noofs_operand): Also check the op
is a valid memory_operand.
2025-08-01 Richard Biener <rguenther@suse.de>
Backported from master:
2025-07-31 Richard Biener <rguenther@suse.de>
PR tree-optimization/121323
* tree-ssa-alias.cc (ao_ref_init_from_ptr_and_range): Check
the pointer offset fits in a HWI when represented in bits.
2025-08-01 Richard Biener <rguenther@suse.de>
Backported from master:
2025-07-31 Richard Biener <rguenther@suse.de>
PR tree-optimization/121320
* tree-ssa-sccvn.cc (ao_ref_init_from_vn_reference): Convert
op->off to poly_offset_int before multiplying by
BITS_PER_UNIT.
2025-08-01 Jakub Jelinek <jakub@redhat.com>
Backported from master:
2025-08-01 Jakub Jelinek <jakub@redhat.com>
PR middle-end/121322
* gimple-ssa-store-merging.cc (find_bswap_or_nop): Return NULL if
count is 0.
2025-07-31 Georg-Johann Lay <avr@gjlay.de>
Backported from master:
2025-07-31 Georg-Johann Lay <avr@gjlay.de>
PR rtl-optimization/121340
* config/avr/avr.opt (-mfuse-move2): New option.
* config/avr/avr-passes.def (avr_pass_2moves): Insert after combine.
* config/avr/avr-passes.cc (make_avr_pass_2moves): New function.
(pass_data avr_pass_data_2moves): New static variable.
(avr_pass_2moves): New rtl_opt_pass.
* config/avr/avr-protos.h (make_avr_pass_2moves): New proto.
* common/config/avr/avr-common.cc
(default_options avr_option_optimization_table) <-mfuse-move2>:
Set for -O1 and higher.
* doc/invoke.texi (AVR Options) <-mfuse-move2>: Document.
* config/avr/avr.opt.urls (-mfuse-move2): Add url.
2025-07-31 Georg-Johann Lay <avr@gjlay.de>
Backported from master:
2025-07-31 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr.cc (avr_output_addr_vec) <labl>: Asm out its .type.
2025-07-31 Spencer Abson <spencer.abson@arm.com>
Backported from master:
2025-07-31 Spencer Abson <spencer.abson@arm.com>
PR target/121028
* config/aarch64/aarch64-sme.md (aarch64_smstart_sm): Use the .inst
directive if !TARGET_SME.
(aarch64_smstop_sm): Likewise.
2025-07-31 Richard Biener <rguenther@suse.de>
PR tree-optimization/121256
* tree-vect-loop.cc (vectorizable_recurr): Handle the case
of a NULL SLP node.
2025-07-31 Andreas Schwab <schwab@suse.de>
Backported from master:
2025-07-21 Andreas Schwab <schwab@suse.de>
PR target/121121
* config/riscv/riscv.cc (riscv_allocate_and_probe_stack_space):
Use temp2 instead of temp1 for the CFA note.
2025-07-31 Jakub Jelinek <jakub@redhat.com>
Backported from master:
2025-07-31 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/121264
* machmode.h (get_best_mode): Change type of first 2 arguments
from int to HOST_WIDE_INT.
* stor-layout.cc (get_best_mode): Likewise.
2025-07-31 Jan Hubicka <hubicka@ucw.cz>
Backported from master:
2025-07-11 Jan Hubicka <hubicka@ucw.cz>
PR ipa/114790
* cgraph.cc (cgraph_update_edges_for_call_stmt_node): Resolve devirtualization
if call statement was optimized out or turned to direct call.
2025-07-31 Richard Biener <rguenther@suse.de>
Backported from master:
2025-07-28 Richard Biener <rguenther@suse.de>
PR tree-optimization/121256
* tree-vect-loop.cc (vectorizable_recurr): Build a correct
initialization vector for SLP_TREE_LANES > 1.
2025-07-31 Richard Biener <rguenther@suse.de>
Backported from master:
2025-07-30 Richard Biener <rguenther@suse.de>
PR tree-optimization/121130
* tree-vect-stmts.cc (vectorizable_call): Bail out for
.MASK_CALL.
2025-07-31 Pengfei Li <Pengfei.Li2@arm.com>
Backported from master:
2025-07-30 Pengfei Li <Pengfei.Li2@arm.com>
PR tree-optimization/121190
* tree-vect-data-refs.cc (vect_enhance_data_refs_alignment):
Increase alignment requirement for speculative loads.
2025-07-31 H.J. Lu <hjl.tools@gmail.com>
Backported from master:
2025-07-30 H.J. Lu <hjl.tools@gmail.com>
PR target/120427
* config/i386/i386.md (peephole2): Transform "movq $-1,reg" to
"pushq $-1; popq reg" for -Oz if reg is a legacy integer register.
2025-07-31 liuhongt <hongtao.liu@intel.com>
Backported from master:
2025-07-30 liuhongt <hongtao.liu@intel.com>
PR target/121274
* config/i386/sse.md (*vec_concatv2di_0): Add a splitter
before it.
2025-07-30 Jennifer Schmitz <jschmitz@nvidia.com>
Dhruv Chawla <dhruvc@nvidia.com>
* config/aarch64/aarch64-cores.def (olympus): Use olympus tuning
model.
* config/aarch64/aarch64.cc: Include olympus.h.
* config/aarch64/tuning_models/olympus.h: New file.
2025-07-29 Francois-Xavier Coudert <fxcoudert@gcc.gnu.org>
Backported from master:
2025-07-14 François-Xavier Coudert <fxcoudert@gcc.gnu.org>
PR target/120645
* config/darwin-driver.cc: Account for latest macOS numbering
scheme.
2025-07-29 Martin Jambor <mjambor@suse.cz>
Backported from master:
2025-07-23 Martin Jambor <mjambor@suse.cz>
PR tree-optimization/119085
* tree-sra.cc (sort_and_splice_var_accesses): Prevent total
scalarization if two incompatible aggregates access the same place.
2025-07-29 Jakub Jelinek <jakub@redhat.com>
Backported from master:
2025-07-29 Jakub Jelinek <jakub@redhat.com>
PR middle-end/121159
* calls.cc (can_implement_as_sibling_call_p): Don't reject declared
noreturn functions in musttail calls.
2025-07-29 H.J. Lu <hjl.tools@gmail.com>
Backported from master:
2025-06-19 H.J. Lu <hjl.tools@gmail.com>
PR target/120427
* config/i386/i386.md (*mov<mode>_and): Changed to
define_insn_and_split. Split it to "mov $0,mem" if not -Oz.
(*mov<mode>_or): Changed to define_insn_and_split. Split it
to "mov $-1,mem" if not -Oz.
(peephole2): Don't transform "mov $-1,reg" to "push $-1; pop reg"
for -Oz since it will be transformed to "or $-1,reg".
2025-07-28 Georg-Johann Lay <avr@gjlay.de>
Backported from master:
2025-07-28 Georg-Johann Lay <avr@gjlay.de>
PR target/121277
* config/avr/avr.cc (avr_addr_space_convert): When converting
from generic AS to __flashx, don't set bit 23.
(avr_convert_to_type): Don't -Waddr-space-convert when NULL
is converted to __flashx or to __flash.
2025-07-28 Xi Ruoyao <xry111@xry111.site>
Backported from master:
2025-07-17 Xi Ruoyao <xry111@xry111.site>
PR target/121064
* config/loongarch/lsx.md (lsx_vshuf_<lsxfmt_f>): Add '@' to
generate a mode-aware helper. Use <VIMODE> as the mode of the
operand 1 (selector).
* config/loongarch/lasx.md (lasx_xvshuf_<lasxfmt_f>): Likewise.
* config/loongarch/loongarch.cc
(loongarch_try_expand_lsx_vshuf_const): Create a new pseudo for
the selector. Use the mode-aware helper to simplify the code.
(loongarch_expand_vec_perm_const): Likewise.
2025-07-27 Alexey Merzlyakov <alexey.merzlyakov@samsung.com>
Backported from master:
2025-06-30 Alexey Merzlyakov <alexey.merzlyakov@samsung.com>
PR target/120714
* config/riscv/riscv.cc (riscv_allocate_and_probe_stack_space):
Fix SP-addresses in REG_CFA_DEF_CFA notes for stack-clash case.
2025-07-26 Andrew Pinski <quic_apinski@quicinc.com>
Backported from master:
2025-07-17 Andrew Pinski <quic_apinski@quicinc.com>
PR middle-end/121095
* gcse.cc (execute_hardreg_pre): Skip if the hardreg which is never live.
2025-07-26 Andrew Pinski <quic_apinski@quicinc.com>
Backported from master:
2025-07-23 Andrew Pinski <quic_apinski@quicinc.com>
PR target/120119
* config/aarch64/cortex-a57-fma-steering.cc (func_fma_steering::analyze):
Skip if renaming fails.
2025-07-24 Richard Biener <rguenther@suse.de>
Backported from master:
2025-07-22 Richard Biener <rguenther@suse.de>
PR tree-optimization/121202
* tree-vect-slp.cc (vect_schedule_slp_node): Do not take
an out-of-region stmt as "last".
2025-07-23 Martin Jambor <mjambor@suse.cz>
Backported from master:
2025-07-18 Martin Jambor <mjambor@suse.cz>
PR tree-optimization/117423
* tree-sra.cc (analyze_access_subtree): Fix computation of grp_covered
flag.
2025-07-22 Tobias Burnus <tburnus@baylibre.com>
Backported from master:
2025-06-17 Tobias Burnus <tburnus@baylibre.com>
* omp-offload.cc (omp_discover_declare_target_tgt_fn_r): Also
walk external functions that are declare inline (and have a
DECL_SAVED_TREE).
2025-07-22 Thomas Schwinge <tschwinge@baylibre.com>
Backported from master:
2025-06-04 Thomas Schwinge <tschwinge@baylibre.com>
* config/nvptx/mkoffload.cc (process): Use an 'auto_vec' for
'file_idx'.
2025-07-22 Thomas Schwinge <tschwinge@baylibre.com>
Backported from master:
2025-05-30 Thomas Schwinge <tschwinge@baylibre.com>
Richard Biener <rguenther@suse.de>
PR middle-end/119835
* tree-nrv.cc (pass_nrv::execute): Defuse 'RESULT_DECL' check.
2025-07-22 Thomas Schwinge <tschwinge@baylibre.com>
Backported from master:
2025-05-19 Thomas Schwinge <tschwinge@baylibre.com>
PR lto/120308
* lto-streamer-out.cc (hash_tree): Don't handle 'TYPE_EMPTY_P' for
'lto_stream_offload_p'.
* tree-streamer-in.cc (unpack_ts_type_common_value_fields):
Likewise.
* tree-streamer-out.cc (pack_ts_type_common_value_fields):
Likewise.
2025-07-22 Thomas Schwinge <tschwinge@baylibre.com>
Backported from master:
2025-05-12 Thomas Schwinge <tschwinge@baylibre.com>
* config/nvptx/nvptx-sm.def: Add '61'.
* config/nvptx/nvptx-gen.h: Regenerate.
* config/nvptx/nvptx-gen.opt: Likewise.
* config/nvptx/nvptx.cc (first_ptx_version_supporting_sm): Adjust.
* config/nvptx/nvptx.opt (-march-map=sm_61, -march-map=sm_62):
Likewise.
* config.gcc: Likewise.
* doc/invoke.texi (Nvidia PTX Options): Document '-march=sm_61'.
* config/nvptx/gen-multilib-matches-tests: Extend.
2025-07-22 Thomas Schwinge <tschwinge@baylibre.com>
Backported from master:
2025-05-12 Thomas Schwinge <tschwinge@baylibre.com>
* config/nvptx/nvptx-opts.h (enum ptx_version): Add
'PTX_VERSION_5_0'.
* config/nvptx/nvptx.cc (ptx_version_to_string)
(ptx_version_to_number): Adjust.
* config/nvptx/nvptx.h (TARGET_PTX_5_0): New.
* config/nvptx/nvptx.opt (Enum(ptx_version)): Add 'EnumValue'
'5.0' for 'PTX_VERSION_5_0'.
* doc/invoke.texi (Nvidia PTX Options): Document '-mptx=5.0'.
2025-07-22 Andrew Pinski <quic_apinski@quicinc.com>
Backported from master:
2025-04-25 Andrew Pinski <quic_apinski@quicinc.com>
Thomas Schwinge <tschwinge@baylibre.com>
PR target/119737
* config/gcn/gcn.cc (gcn_hsa_declare_function_name): Properly
switch sections.
2025-07-21 Richard Sandiford <richard.sandiford@arm.com>
Backported from master:
2025-07-11 Richard Sandiford <richard.sandiford@arm.com>
PR target/121027
* config/aarch64/aarch64.cc (aarch64_evpc_sve_tbl): Punt on 2-input
operations that can be handled by vec_perm.
2025-07-21 Richard Sandiford <richard.sandiford@arm.com>
Backported from master:
2025-07-10 Richard Sandiford <richard.sandiford@arm.com>
* config/aarch64/aarch64-sve2.md (aarch64_gather_ld1q): Replace with...
(@aarch64_gather_ld1q<mode>): ...this, parameterizing based on mode.
* config/aarch64/aarch64-sve-builtins-sve2.cc
(svld1q_gather_impl::expand): Update accordingly.
(svst1q_scatter_impl::expand): Use aarch64_sve_reinterpret
instead of force_lowpart_subreg.
2025-07-21 Richard Sandiford <richard.sandiford@arm.com>
Backported from master:
2025-07-10 Richard Sandiford <richard.sandiford@arm.com>
* doc/sourcebuild.texi (aarch64_sve2_hw, aarch64_sve2p1_hw): Document.
* config/aarch64/aarch64.cc (aarch64_evpc_hvla): Extend to
BYTES_BIG_ENDIAN.
2025-07-21 Richard Sandiford <richard.sandiford@arm.com>
Backported from master:
2025-07-09 Richard Sandiford <richard.sandiford@arm.com>
* config/aarch64/aarch64.cc (aarch64_simd_valid_imm): Account
for FLOAT_WORDS_BIG_ENDIAN when building a floating-point value.
2025-07-21 Richard Sandiford <richard.sandiford@arm.com>
Backported from master:
2025-07-09 Richard Sandiford <richard.sandiford@arm.com>
* config/aarch64/aarch64.cc (aarch64_sve_index_series_p): New
function, split out from...
(aarch64_simd_valid_imm): ...here. Account for the different
SVE and Advanced SIMD element orders on big-endian targets.
Check each vector in a structure mode.
2025-07-21 Richard Sandiford <richard.sandiford@arm.com>
Backported from master:
2025-07-09 Richard Sandiford <richard.sandiford@arm.com>
* read-rtl-function.cc (function_reader::read_rtx_operand_r): Use
hard_regno_nregs to work out REG_NREGS for hard registers.
2025-07-21 Richard Sandiford <richard.sandiford@arm.com>
Backported from master:
2025-07-09 Richard Sandiford <richard.sandiford@arm.com>
* ext-dce.cc (ext_dce_process_uses): Apply is_constant directly
to the subreg_lsb.
2025-07-21 Richard Sandiford <richard.sandiford@arm.com>
Backported from master:
2025-07-07 Richard Sandiford <richard.sandiford@arm.com>
PR target/118891
* config/aarch64/aarch64.cc (aarch64_expand_vector_init): Fix the
ZIP1 operand order for big-endian targets.
2025-07-21 Richard Sandiford <richard.sandiford@arm.com>
Backported from master:
2025-07-07 Richard Sandiford <richard.sandiford@arm.com>
* config/aarch64/aarch64-sve.md (@aarch64_sve_set_neonq_<mode>):
Use %Z instead of lowpart_subreg. Tweak formatting.
2025-07-21 Richard Sandiford <richard.sandiford@arm.com>
Backported from master:
2025-07-07 Richard Sandiford <richard.sandiford@arm.com>
* ext-dce.cc (ext_dce_process_uses): Apply is_constant directly
to the subreg_lsb.
2025-07-21 Richard Sandiford <richard.sandiford@arm.com>
Backported from master:
2025-07-07 Richard Sandiford <richard.sandiford@arm.com>
PR tree-optimization/118891
* tree-vect-stmts.cc (supportable_widening_operation): Swap the
hi and lo internal functions on big-endian targets.
2025-07-18 Hans-Peter Nilsson <hp@bitrange.com>
Pietro Monteiro <pietro@sociotechnical.xyz>
PR middle-end/120935
* config/mmix/mmix.h (MAX_FIXED_MODE_SIZE): Define.
2025-07-18 Richard Biener <rguenther@suse.de>
Backported from master:
2025-07-18 Richard Biener <rguenther@suse.de>
PR tree-optimization/120924
* params.opt (uninit-max-chain-len): Up from 8 to 12.
2025-07-18 Richard Biener <rguenther@suse.de>
Backported from master:
2025-07-15 Richard Biener <rguenther@suse.de>
Richard Sandiford <richard.sandiford@arm.com>
PR tree-optimization/121059
* tree-vect-stmts.cc (vectorizable_operation): Query
scalar_cond_masked_set with the correct number of masks.
2025-07-18 Richard Biener <rguenther@suse.de>
Backported from master:
2025-07-16 Richard Biener <rguenther@suse.de>
PR tree-optimization/121049
* internal-fn.h (widening_evenodd_fn_p): Declare.
* internal-fn.cc (widening_evenodd_fn_p): New function.
* tree-vect-stmts.cc (vectorizable_conversion): When using
an even/odd widening function disable loop masking.
2025-07-18 Richard Biener <rguenther@suse.de>
Backported from master:
2025-07-17 Richard Biener <rguenther@suse.de>
PR tree-optimization/121035
* tree-ssa-pre.cc (find_or_generate_expression): Handle
values without expression.
2025-07-18 Jakub Jelinek <jakub@redhat.com>
Backported from master:
2025-07-18 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/121131
* gimple-fold.cc (fold_nonarray_ctor_reference): Use
TREE_INT_CST_LOW (TYPE_SIZE ()) instead of
GET_MODE_BITSIZE (SCALAR_INT_TYPE_MODE ()) for BLKmode BITINT_TYPEs.
Don't compute encoding_size at all for little endian targets.
2025-07-17 Xi Ruoyao <xry111@xry111.site>
Backported from master:
2025-07-04 Xi Ruoyao <xry111@xry111.site>
PR target/120807
* config/loongarch/loongarch.md (crc_combine): Avoid nested
subreg.
2025-07-16 Haochen Jiang <haochen.jiang@intel.com>
* common/config/i386/i386-common.cc
(OPTION_MASK_ISA2_AMX_AVX512_SET): Do not set AVX10.2.
(OPTION_MASK_ISA2_AVX10_2_UNSET): Remove AMX-AVX512 unset.
(OPTION_MASK_ISA2_AVX512F_UNSET): Unset AMX-AVX512.
(ix86_handle_option): Imply AVX512F for AMX-AVX512.
2025-07-15 Andrew Pinski <quic_apinski@quicinc.com>
Backported from master:
2025-07-07 Andrew Pinski <quic_apinski@quicinc.com>
PR middle-end/120709
* builtins.cc (expand_builtin_crc_table_based): Error out
instead of asserting the 3rd argument is an integer constant.
* internal-fn.cc (expand_crc_optab_fn): Likewise.
* doc/extend.texi (crc): Document requirement of the poly argument
being a constant.
2025-07-14 Kyrylo Tkachov <ktkachov@nvidia.com>
Backported from master:
2025-07-10 Kyrylo Tkachov <ktkachov@nvidia.com>
PR target/120999
* config/aarch64/aarch64-sve2.md (*aarch64_sve2_nor<mode>):
Adjust movprfx alternative.
2025-07-14 Richard Earnshaw <rearnsha@arm.com>
Backported from master:
2025-05-08 Richard Earnshaw <rearnsha@arm.com>
* config/aarch64/aarch64-sve.md (@aarch64_pred_<optab><mode>): Move
commutative marker to the cons specification.
(add<mode>3): Likewise.
(@aarch64_pred_<su>abd<mode>): Likewise.
(@aarch64_pred_<optab><mode>): Likewise.
(*cond_<optab><mode>_z): Likewise.
(<optab><mode>3): Likewise.
(@aarch64_pred_<optab><mode>): Likewise.
(*aarch64_pred_abd<mode>_relaxed): Likewise.
(*aarch64_pred_abd<mode>_strict): Likewise.
(@aarch64_pred_<optab><mode>): Likewise.
(@aarch64_pred_<optab><mode>): Likewise.
(@aarch64_pred_fma<mode>): Likewise.
(@aarch64_pred_fnma<mode>): Likewise.
(@aarch64_pred_<optab><mode>): Likewise.
* config/aarch64/aarch64-sve2.md (@aarch64_sve_<su>clamp<mode>): Move
commutative marker to the cons specification.
(*aarch64_sve_<su>clamp<mode>_x): Likewise.
(@aarch64_sve_fclamp<mode>): Likewise.
(*aarch64_sve_fclamp<mode>_x): Likewise.
(*aarch64_sve2_nor<mode>): Likewise.
(*aarch64_sve2_nand<mode>): Likewise.
(*aarch64_pred_faminmax_fused): Likewise.
* config/aarch64/aarch64.md (*loadwb_pre_pair_<ldst_sz>): Move the
early-clobber marker to the relevant alternative.
(*storewb_pre_pair_<ldst_sz>): Likewise.
(*add<mode>3_aarch64): Move commutative marker to the cons
specification.
(*addsi3_aarch64_uxtw): Likewise.
(*add<mode>3_poly_1): Likewise.
(add<mode>3_compare0): Likewise.
(*addsi3_compare0_uxtw): Likewise.
(*add<mode>3nr_compare0): Likewise.
(<optab><mode>3): Likewise.
(*<optab>si3_uxtw): Likewise.
(*and<mode>3_compare0): Likewise.
(*andsi3_compare0_uxtw): Likewise.
(@aarch64_and<mode>3nr_compare0): Likewise.
2025-07-14 Jeff Law <jlaw@ventanamicro.com>
Backported from master:
2025-06-30 Jeff Law <jlaw@ventanamicro.com>
PR rtl-optimization/120242
PR rtl-optimization/120627
PR rtl-optimization/120736
PR rtl-optimization/120813
* ext-dce.cc (ext_dce_process_uses): Remove some cases where we
unnecessarily expanded live sets for promoted subregs.
(expand_changed_pseudos): New function.
(reset_subreg_promoted_p): Use it.
2025-07-14 Vineet Gupta <vineetg@rivosinc.com>
Backported from master:
2025-07-04 Vineet Gupta <vineetg@rivosinc.com>
PR target/118241
* config/riscv/riscv.md (prefetch): Add alternative "r".
2025-07-14 Vineet Gupta <vineetg@rivosinc.com>
Backported from master:
2025-07-04 Vineet Gupta <vineetg@rivosinc.com>
* config/riscv/predicates.md (prefetch_operand): mack 5 bits.
2025-07-14 Jeff Law <jlaw@ventanamicro.com>
Backported from master:
2025-06-24 Jeff Law <jlaw@ventanamicro.com>
PR target/118241
* config/riscv/predicates.md: Fix comment typo in recent change.
2025-07-14 Jeff Law <jlaw@ventanamicro.com>
Backported from master:
2025-06-21 Jeff Law <jlaw@ventanamicro.com>
PR target/118241
* config/riscv/predicates.md (prefetch_operand): New predicate.
* config/riscv/constraints.md (Q): New constraint.
* config/riscv/riscv.md (prefetch): Use new predicate and constraint.
(riscv_prefetchi_<mode>): Similarly.
2025-07-14 H.J. Lu <hjl.tools@gmail.com>
Backported from master:
2025-07-03 H.J. Lu <hjl.tools@gmail.com>
PR target/120908
* config/i386/i386.cc (legitimize_tls_address): Pass RDI to
gen_tls_local_dynamic_64.
* config/i386/i386.md (*tls_global_dynamic_64_largepic): Add
RDI clobber and use it to generate LEA.
(*tls_local_dynamic_64_<mode>): Likewise.
(*tls_local_dynamic_base_64_largepic): Likewise.
(@tls_local_dynamic_64_<mode>): Add a clobber.
2025-07-14 H.J. Lu <hjl.tools@gmail.com>
Backported from master:
2025-07-02 H.J. Lu <hjl.tools@gmail.com>
PR target/120908
* config/i386/i386.cc (legitimize_tls_address): Pass RDI to
gen_tls_global_dynamic_64.
* config/i386/i386.md (*tls_global_dynamic_64_<mode>): Add RDI
clobber and use it to generate LEA.
(@tls_global_dynamic_64_<mode>): Add a clobber.
2025-07-14 Haochen Jiang <haochen.jiang@intel.com>
* config/i386/i386.h (PTA_PANTHERLAKE): Revmoe KL and WIDEKL.
(PTA_CLEARWATERFOREST): Ditto.
* doc/invoke.texi: Revise documentation.
2025-07-13 Alexey Merzlyakov <alexey.merzlyakov@samsung.com>
Backported from master:
2025-07-02 Alexey Merzlyakov <alexey.merzlyakov@samsung.com>
PR target/120356
* config/riscv/riscv-v.cc
(expand_const_vector_interleaved_stepped_npatterns):
Fix ASHIFT to LSHIFTRT insn.
2025-07-13 Andreas Schwab <schwab@suse.de>
Backported from master:
2025-07-08 Andreas Schwab <schwab@suse.de>
PR target/120995
* config/riscv/sync.md (zacas_atomic_cas_value_strong<mode>):
Allow op3 to be zero.
2025-07-11 Jakub Jelinek <jakub@redhat.com>
Backported from master:
2025-07-11 Jakub Jelinek <jakub@redhat.com>
Martin Jambor <mjambor@suse.cz>
PR ipa/121023
* ipa-fnsummary.cc (compute_fn_summary): Disallow signature changes
on cfun->has_musttail functions.
2025-07-10 Siddhesh Poyarekar <siddhesh@gotplt.org>
Backported from master:
2025-07-03 Siddhesh Poyarekar <siddhesh@gotplt.org>
PR tree-optimization/120780
* tree-object-size.cc (inner_at_offset,
get_wholesize_for_memref): New functions.
(addr_object_size): Call get_wholesize_for_memref.
2025-07-10 Kyrylo Tkachov <ktkachov@nvidia.com>
Backported from master:
2025-06-30 Kyrylo Tkachov <ktkachov@nvidia.com>
* config/aarch64/aarch64-cores.def (gb10): New entry.
* config/aarch64/aarch64-tune.md: Regenerate.
* doc/invoke.texi (AArch64 Options): Document the above.
2025-07-09 Richard Biener <rguenther@suse.de>
Backported from master:
2025-07-08 Richard Biener <rguenther@suse.de>
PR tree-optimization/120358
* tree-ssa-structalias.cc (get_constraint_for_1): Adjust
pruning of sub-variables according to the imprecise
known start offset.
2025-07-09 Richard Biener <rguenther@suse.de>
Backported from master:
2025-07-03 Richard Biener <rguenther@suse.de>
PR tree-optimization/118669
* tree-vect-stmts.cc (vectorizable_load): Emit loads
with proper (element) alignment.
(vectorizable_store): Likewise.
2025-07-09 Richard Biener <rguenther@suse.de>
Backported from master:
2025-07-07 Richard Biener <rguenther@suse.de>
PR tree-optimization/120817
* tree-ssa-dse.cc (initialize_ao_ref_for_dse): Use
ao_ref_init_from_ptr_and_range with unknown size for
.MASK_STORE and .MASK_LEN_STORE.
2025-07-09 Richard Biener <rguenther@suse.de>
Backported from master:
2025-07-04 Richard Biener <rguenther@suse.de>
PR tree-optimization/120927
* tree-vect-data-refs.cc (vect_compute_data_ref_alignment):
Do not force a DRs base alignment when analyzing an
epilog loop. Check whether the step preserves alignment
for all VFs possibly involved sofar.
2025-07-09 Richard Biener <rguenther@suse.de>
Backported from master:
2025-07-04 Richard Biener <rguenther@suse.de>
PR tree-optimization/120944
* tree-ssa-sccvn.cc (vn_reference_lookup_3): Gate optimizations
invalid when volatile is involved.
2025-07-06 Georg-Johann Lay <avr@gjlay.de>
Backported from master:
2025-07-06 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr-mcus.def: -mmcu= takes lower case MCU names.
* doc/avr-mmcu.texi: Rebuild.
2025-07-06 Georg-Johann Lay <avr@gjlay.de>
Backported from master:
2025-07-06 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr-mcus.def (avr32da28S, avr32da32S, avr32da48S)
(avr64da28S, avr64da32S, avr64da48S avr64da64S)
(avr128da28S, avr128da32S, avr128da48S, avr128da64S): Add devices.
* doc/avr-mmcu.texi: Rebuild.
2025-07-03 Andrew Pinski <quic_apinski@quicinc.com>
Backported from master:
2025-05-21 Andrew Pinski <quic_apinski@quicinc.com>
PR middle-end/120369
* tree-complex.cc (gimple_expand_builtin_cabs): Return early
if the LHS of cabs is null.
2025-07-03 Sam James <sam@gentoo.org>
Backported from master:
2025-06-23 Sam James <sam@gentoo.org>
Jeff Law <jlaw@ventanamicro.com>
PR rtl-optimization/120795
* ext-dce.cc (ext_dce_try_optimize_insn): Enable rescan in
remove_reg_equal_equiv_notes call.
2025-07-03 Jeff Law <jlaw@ventanamicro.com>
Backported from master:
2025-06-22 Jeff Law <jlaw@ventanamicro.com>
PR rtl-optimization/120550
* ext-dce.cc (ext_dce_try_optimize_insn): Drop REG_EQUAL/REG_EQUIV
notes on modified insns.
2025-07-02 Richard Biener <rguenther@suse.de>
Backported from master:
2025-07-02 Richard Biener <rguenther@suse.de>
PR tree-optimization/120927
* tree-vect-loop.cc (vect_analyze_loop): Stop querying
further epilogues after one with partial vectors.
2025-07-02 Haochen Jiang <haochen.jiang@intel.com>
* config/i386/driver-i386.cc (host_detect_local_cpu): Change
to AMX-FP8 for Diamond Rapids.
2025-07-01 Jakub Jelinek <jakub@redhat.com>
Backported from master:
2025-07-01 Jakub Jelinek <jakub@redhat.com>
PR middle-end/120608
* passes.def (pass_musttail): Move before pass_sanopt.
* tree-tailcall.cc (empty_eh_cleanup): Handle GIMPLE_RESX
which doesn't throw externally through recursion on single
eh edge (if any and cnt still allows that).
(find_tail_calls): Add ESUCC, IGNORED_EDGES and MUST_SEE_BBS
arguments. Handle GIMPLE_CONDs for non-simplified cleanups with
finally_tmp temporaries both on backward and forward walks, adjust
recursive call.
(tree_optimize_tail_calls_1): Adjust find_tail_calls callers.
2025-06-27 Eric Botcazou <ebotcazou@adacore.com>
* gimple-fold.cc (fold_const_aggregate_ref_1) <COMPONENT_REF>:
Bail out immediately if the reference has reverse storage order.
* tree-ssa-sccvn.cc (fully_constant_vn_reference_p): Likewise.
2025-06-26 Richard Biener <rguenther@suse.de>
* lto-streamer.h (LTO_minor_version): Bump to 1.
2025-06-26 Richard Biener <rguenther@suse.de>
Backported from master:
2025-06-23 Richard Biener <rguenther@suse.de>
PR tree-optimization/120729
* gimple-predicate-analysis.h (uninit_analysis::prune_phi_opnds):
Add argument of work budget remaining.
* gimple-predicate-analysis.cc (uninit_analysis::prune_phi_opnds):
Likewise. Maintain and honor it throughout the recursion.
* params.opt (uninit-max-prune-work): New.
* doc/invoke.texi (uninit-max-prune-work): Document.
2025-06-26 Richard Biener <rguenther@suse.de>
Backported from master:
2025-06-20 Richard Biener <rguenther@suse.de>
PR tree-optimization/120654
* vr-values.cc (range_fits_type_p): Check for undefined_p ()
before accessing type ().
2025-06-25 Jeff Law <jlaw@ventanamicro.com>
Backported from master:
2025-06-10 Jeff Law <jlaw@ventanamicro.com>
* config/riscv/riscv.md (lui-constraint<X:mode>and_to_or): Do not use
the RTL template for split code. Emit it directly taking care to avoid
emitting a constant load that needed synthesis. Fix formatting.
2025-06-25 Richard Sandiford <richard.sandiford@arm.com>
Backported from master:
2025-06-12 Richard Sandiford <richard.sandiford@arm.com>
PR target/120624
* config/aarch64/aarch64.md (SME_STATE_REGNUM): Expand on comments.
* config/aarch64/aarch64-sme.md (aarch64_restore_za): Also set
SME_STATE_REGNUM
2025-06-25 Richard Sandiford <richard.sandiford@arm.com>
Backported from master:
2025-05-30 Richard Sandiford <richard.sandiford@arm.com>
PR rtl-optimization/120347
* rtlanal.cc (rtx_properties::try_to_add_src): Don't drop the
IN_MEM_LOAD and IN_MEM_STORE flags for autoinc registers.
* rtl-ssa/changes.cc (recog_level2): Check whether an
RTX_AUTOINCed register also appears outside of an address.
2025-06-25 Haochen Jiang <haochen.jiang@intel.com>
* config/i386/i386.h (PTA_ALDERLAKE): Use PTA_GOLDMONT_PLUS
as base to remove PTA_CLDEMOTE.
(PTA_SIERRAFOREST): Add PTA_CLDEMOTE since PTA_ALDERLAKE
does not include that anymore.
* doc/invoke.texi: Update texi file.
2025-06-23 Jakub Jelinek <jakub@redhat.com>
Backported from master:
2025-06-23 Jakub Jelinek <jakub@redhat.com>
PR middle-end/120608
* tree-tailcall.cc (empty_eh_cleanup): Ignore .ASAN_MARK (POISON)
internal calls for the cfun->has_musttail case and diag_musttail.
(find_tail_calls): Likewise.
2025-06-23 Jakub Jelinek <jakub@redhat.com>
Backported from master:
2025-06-23 Jakub Jelinek <jakub@redhat.com>
PR middle-end/120608
* cfgexpand.cc: Include rtl-iter.h.
(expand_gimple_tailcall): Add ASAN_EPILOG_SEQ argument, if non-NULL
and expand_gimple_stmt emitted a tail call, emit a copy of that
insn sequence before the call sequence.
(expand_gimple_basic_block): Remove DISABLE_TAIL_CALLS argument, add
ASAN_EPILOG_SEQ argument. Disable tail call flag only on non-musttail
calls if that flag is set, pass it to expand_gimple_tailcall.
(pass_expand::execute): Pass VAR_RET_SEQ directly as last
expand_gimple_basic_block argument rather than its comparison with
NULL.
2025-06-20 Jeff Law <jlaw@ventanamicro.com>
Backported from master:
2025-05-05 Jeff Law <jlaw@ventanamicro.com>
PR target/119971
* config/riscv/bitmanip.md (rotation with masked count): Rewrite
as define_insn patterns. Fix formatting.
* config/riscv/riscv.md (shift with masked count): Similarly.
2025-06-19 Jakub Jelinek <jakub@redhat.com>
Backported from master:
2025-06-19 Jakub Jelinek <jakub@redhat.com>
PR middle-end/120631
* dfp.cc (decimal_real_to_integer): Use result multiplication not just
when precision > 128 and dn.exponent > 19, but when precision > 64
and dn.exponent > 0.
2025-06-19 Jakub Jelinek <jakub@redhat.com>
Backported from master:
2025-06-18 Jakub Jelinek <jakub@redhat.com>
PR middle-end/120631
* real.cc (decimal_from_integer): Add digits argument, if larger than
256, use XALLOCAVEC allocated buffer.
(real_from_integer): Pass val_in's precision divided by 3 to
decimal_from_integer.
* dfp.cc (decimal_real_to_integer): For precision > 128 if finite
and exponent is large, decrease exponent and multiply resulting
wide_int by powers of 10^19.
2025-06-18 Jan Beulich <jbeulich@suse.com>
* doc/gcov.texi: Drop blank after @anchor.
2025-06-18 Jan Beulich <jbeulich@suse.com>
* doc/extend.texi: Fill first argument of @xref{}.
2025-06-17 Jakub Jelinek <jakub@redhat.com>
Backported from master:
2025-06-17 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/120677
* gimple-crc-optimization.cc (crc_optimization::optimize_crc_loop):
Insert before gsi_after_labels instead of gsi_start_bb. Use
gimple_bb (output_crc) instead of output_crc->bb. Formatting fix.
2025-06-14 Georg-Johann Lay <avr@gjlay.de>
PR rtl-optimization/120423
PR rtl-optimization/116389
* config/avr/avr.md [-mno-lra]: Add pre-reload split to transform
(left shift of) a paradoxical subreg to a (left shift of) zero-extend.
2025-06-13 Jakub Jelinek <jakub@redhat.com>
Backported from master:
2025-06-12 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/120638
* tree-ssa-math-opts.cc (pass_cse_reciprocals::execute): Call
reset_flow_sensitive_info on arg1.
2025-06-13 Jakub Jelinek <jakub@redhat.com>
Backported from master:
2025-06-05 Jakub Jelinek <jakub@redhat.com>
PR middle-end/120547
* real.cc (real_from_integer): Remove maxbitlen variable, use
len instead of that. When shifting right, or in 1 if any of the
shifted away bits are non-zero. Formatting fix.
2025-06-13 Jakub Jelinek <jakub@redhat.com>
Backported from master:
2025-05-20 Jakub Jelinek <jakub@redhat.com>
* tree-chrec.cc (convert_affine_scev): Use signed_type_for instead of
build_nonstandard_integer_type.
2025-06-12 Martin Jambor <mjambor@suse.cz>
Backported from master:
2025-05-29 Martin Jambor <mjambor@suse.cz>
PR ipa/120295
* ipa-prop.cc (update_jump_functions_after_inlining): Do not
combine pass-through jump functions with type-casts changing
signedness.
2025-06-10 Andrew Pinski <quic_apinski@quicinc.com>
Backported from master:
2025-04-30 Andrew Pinski <quic_apinski@quicinc.com>
PR target/120042
* tree-vectorizer.h: Include dominance.h.
2025-06-10 Xi Ruoyao <xry111@xry111.site>
Backported from master:
2025-06-04 Xi Ruoyao <xry111@xry111.site>
PR rtl-optimization/120050
* ext-dce.cc (ext_dce_process_uses): Break early if a SUBREG in
rhs is promoted and the truncation from the inner mode to the
outer mode is not a noop when handling SETs.
2025-06-06 Tobias Burnus <tburnus@baylibre.com>
Backported from master:
2025-06-05 Tobias Burnus <tburnus@baylibre.com>
* config.gcc (--with-{arch,tune}): Use .def file to validate gcn
processor names.
* doc/install.texi (amdgcn*-*-*): Update list of devices supported
by --with-arch/--with-tune.
2025-06-06 Richard Biener <rguenther@suse.de>
Backported from master:
2025-05-31 Richard Biener <rguenther@suse.de>
PR tree-optimization/120357
* tree-vect-loop.cc (vect_create_epilog_for_reduction): Create
the conditional reduction induction IV increment before the
main IV exit.
2025-06-06 Richard Biener <rguenther@suse.de>
Backported from master:
2025-05-30 Richard Biener <rguenther@suse.de>
PR tree-optimization/120341
* tree-ssa-loop-im.cc (can_sm_ref_p): STRING_CSTs are readonly.
* tree-ssa-phiopt.cc (cond_store_replacement): Likewise.
2025-06-06 Richard Biener <rguenther@suse.de>
Backported from master:
2025-05-09 Richard Biener <rguenther@suse.de>
PR rtl-optimization/120182
* dse.cc (canon_address): Constant addresses have no
separate store group.
2025-06-06 Richard Biener <rguenther@suse.de>
Backported from master:
2025-04-30 Richard Biener <rguenther@suse.de>
PR tree-optimization/120003
* tree-ssa-threadbackward.cc (back_threader::find_paths_to_names):
Allow block re-use but do not enlarge the path beyond such a
re-use.
2025-06-06 Richard Biener <rguenther@suse.de>
Backported from master:
2025-05-09 Richard Biener <rguenther@suse.de>
PR tree-optimization/119960
* tree-vect-slp.cc (vect_slp_can_convert_to_external):
Handle cases where defs from multiple BBs are ordered
by their dominance relation.
2025-06-06 Richard Biener <rguenther@suse.de>
Backported from master:
2025-05-08 Richard Biener <rguenther@suse.de>
PR tree-optimization/116352
* tree-vect-slp.cc (vect_build_slp_tree_2): When compressing
operands from a two-operator node make sure the resulting
operation does not mix defs from different basic-blocks.
2025-06-06 Richard Biener <rguenther@suse.de>
Backported from master:
2025-04-30 Richard Biener <rguenther@suse.de>
PR tree-optimization/119960
* tree-vect-slp.cc (vect_schedule_slp_node): Sanity
check dominance check on operand defs.
2025-06-06 Richard Biener <rguenther@suse.de>
Backported from master:
2025-04-30 Richard Biener <rguenther@suse.de>
* tree-vectorizer.h (get_later_stmt): Robustify against
stmts in different BBs, assert when they are unordered.
2025-06-06 Richard Biener <rguenther@suse.de>
Backported from master:
2025-05-15 Richard Biener <rguenther@suse.de>
* config/i386/i386.cc (ix86_vector_costs::finish_cost):
Do not suggest a first epilogue mode for AVX512 sized
main loops with X86_TUNE_AVX512_TWO_EPILOGUES as that
interferes with using a masked epilogue.
2025-06-05 Eric Botcazou <ebotcazou@adacore.com>
* tree-vect-data-refs.cc (vect_can_force_dr_alignment_p): Return
false if the variable has no symtab node.
2025-05-29 Yuta Mukai <mukai.yuta@fujitsu.com>
Backported from master:
2025-05-28 Yuta Mukai <mukai.yuta@fujitsu.com>
* config/aarch64/aarch64-cores.def (fujitsu-monaka): Update ISA
features.
2025-05-27 Eric Botcazou <ebotcazou@adacore.com>
* ipa-sra.cc (scan_expr_access): Also disqualify storage order
barriers from splitting.
* tree.h (storage_order_barrier_p): Also return false if the
operand of the VIEW_CONVERT_EXPR has reverse storage order.
2025-05-27 Jonathan Wakely <jwakely@redhat.com>
Backported from master:
2025-05-27 Jonathan Wakely <jwakely@redhat.com>
* doc/extend.texi (Common Variable Attributes): Fix typo in
description of nonstring.
2025-05-25 Michael J. Eager <eager@eagercon.com>
PR target/86772
Tracking CVE-2017-5753
* config/microblaze/microblaze.cc (TARGET_HAVE_SPECULATION_SAFE_VALUE):
Define to speculation_save_value_not_needed
2025-05-20 Martin Jambor <mjambor@suse.cz>
Backported from master:
2025-05-14 Martin Jambor <mjambor@suse.cz>
PR tree-optimization/111873
* tree-sra.cc (sra_modify_expr): When processing a load which has
a type-incompatible replacement, do not store the contents of the
replacement into the original aggregate when that aggregate is
const.
2025-05-20 Martin Jambor <mjambor@suse.cz>
Backported from master:
2025-05-16 Martin Jambor <mjambor@suse.cz>
Michal Jires <mjires@suse.cz>
* cgraph.h (symtab_node): Make member function get_uid const.
* cgraphclones.cc (dump_callgraph_transformation): Dump m_uid of the
call graph nodes instead of order.
* cgraph.cc (cgraph_node::remove): Likewise.
* ipa-cp.cc (ipcp_lattice<valtype>::print): Likewise.
* ipa-sra.cc (ipa_sra_summarize_function): Likewise.
* symtab.cc (symtab_node::dump_base): Likewise.
2025-05-16 Maciej W. Rozycki <macro@orcam.me.uk>
Backported from master:
2025-04-19 Maciej W. Rozycki <macro@orcam.me.uk>
* config/alpha/alpha.cc
(alpha_get_mem_rtx_alignment_and_offset): Recurse into
COMPONENT_REF nodes.
2025-05-14 Kyle Huey <me@kylehuey.com>
* dwarf2out.cc (resolve_addr_in_expr): Propagate dtprel into the address
table when appropriate.
2025-05-13 Gaius Mulley <gaiusmod2@gmail.com>
Backported from master:
2025-05-12 Gaius Mulley <gaiusmod2@gmail.com>
PR modula2/120188
* doc/gm2.texi (Semantic checking): Add -fm2-plugin command line option.
2025-05-11 Richard Biener <rguenther@suse.de>
PR tree-optimization/120211
* tree-vect-stmts.cc (vect_stmt_relevant_p): Only add PHIs
from the loop header to LOOP_VINFO_EARLY_BREAKS_LIVE_IVS.
2025-05-11 Richard Biener <rguenther@suse.de>
Backported from master:
2025-05-08 Richard Biener <rguenther@suse.de>
PR ipa/120146
* tree-ssa-structalias.cc (create_variable_info_for): If
the symtab cannot tell us whether all refs to a variable
are explicit assume they are not.
2025-05-11 Richard Biener <rguenther@suse.de>
Backported from master:
2025-05-08 Richard Biener <rguenther@suse.de>
PR tree-optimization/120143
* tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
Move/update the original stmts, not the pattern stmts which
lack virtual operands and are not in the IL.
2025-05-11 Richard Biener <rguenther@suse.de>
Backported from master:
2025-05-08 Richard Biener <rguenther@suse.de>
PR tree-optimization/120089
* tree-vect-stmts.cc (vect_stmt_relevant_p): Mark all
PHIs live when not already so and doing early-break
vectorization.
(vect_mark_stmts_to_be_vectorized): Skip virtual PHIs.
* tree-vect-slp.cc (vect_analyze_slp): Robustify handling
of early-break forced IVs.
2025-05-11 Richard Biener <rguenther@suse.de>
Backported from master:
2025-05-08 Richard Biener <rguenther@suse.de>
PR tree-optimization/120043
* tree-ssa-phiopt.cc (cond_store_replacement): Check
whether the store is to readonly memory.
2025-05-09 Eric Botcazou <ebotcazou@adacore.com>
* vr-values.cc (simplify_using_ranges::simplify) <BIT_AND_EXPR>:
Do not call simplify_bit_ops_using_ranges for boolean types whose
precision is not 1.
2025-05-07 Martin Jambor <mjambor@suse.cz>
Backported from master:
2025-05-06 Martin Jambor <mjambor@suse.cz>
PR ipa/119852
* cgraphclones.cc (dump_callgraph_transformation): Document the
function. Do not dump if suffix is NULL.
2025-05-07 Martin Jambor <mjambor@suse.cz>
Backported from master:
2025-05-06 Martin Jambor <mjambor@suse.cz>
* doc/invoke.texi (Developer Options): Document -fdump-ipa-clones.
2025-05-06 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/120048
* ipa-cp.cc (ipcp_store_vr_results): Check for UNDEFINED.
2025-05-06 Jakub Jelinek <jakub@redhat.com>
Backported from master:
2025-05-06 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/120074
* gimple-fold.cc (fold_truth_andor_for_ifcombine): For
lsignbit && l_xor case, punt if ll_bitsize != lr_bitsize. Similarly
for rsignbit && r_xor case, punt if rl_bitsize != rr_bitsize.
Formatting fix.
2025-05-05 Richard Biener <rguenther@suse.de>
Backported from master:
2025-04-30 Richard Biener <rguenther@suse.de>
PR ipa/120006
* tree-ssa-structalias.cc (find_func_clobbers): Handle
strdup, strndup, realloc, index, strchr, strrchr, memchr,
strstr, strpbrk builtins like find_func_aliases does.
2025-05-05 Richard Biener <rguenther@suse.de>
Backported from master:
2025-04-28 Richard Biener <rguenther@suse.de>
PR ipa/119973
* tree-ssa-structalias.cc (create_variable_info_for):
Build constraints from DECL_INITIAL directly rather than
the IPA reference list which is incomplete.
2025-04-30 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/119712
* value-range.cc (range_bitmask::adjust_range): Delete.
(irange::set_range_from_bitmask): Integrate adjust_range.
(irange::update_bitmask): Do nothing if bitmask doesnt change.
(irange:intersect_bitmask): Do not call adjust_range. Exit if there
is no second bitmask.
* value-range.h (adjust_range): Remove prototype.
2025-04-30 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr.md (fxload_<mode>_libgcc): Use REG_ prefix for
magix register numbers (aligns with trunk).
2025-04-30 Georg-Johann Lay <avr@gjlay.de>
Backported from master:
2025-04-30 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr.md (xload_<mode>_libgcc): Clobber R21, Z.
2025-04-29 Richard Sandiford <richard.sandiford@arm.com>
Backported from master:
2025-04-24 Richard Sandiford <richard.sandiford@arm.com>
PR target/119610
* config/aarch64/aarch64.cc (aarch64_allocate_and_probe_stack_space):
Add a bytes_below_sp parameter and use it to calculate the CFA
offsets. Attach the first SVE CFA note to the move into the
associated temporary register.
(aarch64_allocate_and_probe_stack_space): Update calls accordingly.
Start out with bytes_per_sp set to the frame size and decrement
it after each allocation.
2025-04-29 liuhongt <hongtao.liu@intel.com>
Backported from master:
2025-04-29 liuhongt <hongtao.liu@intel.com>
* config/i386/x86-tune.def (X86_TUNE_DEST_FALSE_DEP_FOR_GLC):
Remove other processor except for GLC since this one is only
for GLC.
2025-04-25 Jakub Jelinek <jakub@redhat.com>
Backported from master:
2025-04-25 Jakub Jelinek <jakub@redhat.com>
PR target/119873
* config/s390/s390.cc (s390_call_saved_register_used): Don't return
true if default definition of PARM_DECL SSA_NAME of the same register
is passed in call saved register in the PARALLEL case either.
2025-04-25 Jakub Jelinek <jakub@redhat.com>
Backported from master:
2025-04-24 Jakub Jelinek <jakub@redhat.com>
Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
PR target/119873
* config/s390/s390.cc (s390_call_saved_register_used): Don't return
true if default definition of PARM_DECL SSA_NAME of the same register
is passed in call saved register.
(s390_function_ok_for_sibcall): Adjust comment.
2025-04-25 Jakub Jelinek <jakub@redhat.com>
Backported from master:
2025-04-22 Jakub Jelinek <jakub@redhat.com>
PR target/119327
* config/rs6000/rs6000.cc (rs6000_can_inline_p): Ignore also
OPTION_MASK_SAVE_TOC_INDIRECT differences.
2025-04-25 Release Manager
* GCC 15.1.0 released.
2025-04-24 Kyrylo Tkachov <ktkachov@nvidia.com>
Backported from master:
2025-04-24 Kyrylo Tkachov <ktkachov@nvidia.com>
* opts.cc (validate_ipa_reorder_locality_lto_partition): Check opts
instead of opts_set for x_flag_ipa_reorder_for_locality.
(finish_options): Update call site.
2025-04-24 Kyrylo Tkachov <ktkachov@nvidia.com>
Backported from master:
2025-04-24 Kyrylo Tkachov <ktkachov@nvidia.com>
* common.opt (LTO_PARTITION_DEFAULT): Delete.
(flto-partition=): Change default back to balanced.
* flag-types.h (lto_partition_model): Remove LTO_PARTITION_DEFAULT.
* opts.cc (validate_ipa_reorder_locality_lto_partition):
Check opts_set->x_flag_lto_partition instead of LTO_PARTITION_DEFAULT.
(finish_options): Remove handling of LTO_PARTITION_DEFAULT.
2025-04-22 Richard Sandiford <richard.sandiford@arm.com>
Backported from master:
2025-04-22 Richard Sandiford <richard.sandiford@arm.com>
* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Define
__ARM_FEATURE_FAMINMAX.
2025-04-22 Kyrylo Tkachov <ktkachov@nvidia.com>
Backported from master:
2025-04-22 Kyrylo Tkachov <ktkachov@nvidia.com>
* config/aarch64/aarch64-cores.def (olympus): Add fp8fma, fp8dot4
explicitly.
2025-04-22 Kyrylo Tkachov <ktkachov@nvidia.com>
Backported from master:
2025-04-22 Kyrylo Tkachov <ktkachov@nvidia.com>
* doc/invoke.texi (lto-partition-locality-frequency-cutoff,
lto-partition-locality-size-cutoff, lto-max-locality-partition):
Document.
2025-04-18 Richard Biener <rguenther@suse.de>
PR tree-optimization/119858
* tree-vect-loop.cc (vectorizable_live_operation): Convert
pointer offset to sizetype.
2025-04-17 Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/119351
* tree-vect-stmts.cc (vectorizable_early_exit): Mask both operands of
the gcond for partial masking support.
2025-04-17 Jakub Jelinek <jakub@redhat.com>
PR target/119834
* config/s390/s390.md (define_split after *cpymem_short): Use
(clobber (match_scratch N)) instead of (clobber (scratch)). Use
(match_dup 4) and operands[4] instead of (match_dup 3) and operands[3]
in the last of those.
(define_split after *clrmem_short): Use (clobber (match_scratch N))
instead of (clobber (scratch)).
(define_split after *cmpmem_short): Likewise.
2025-04-17 Thomas Schwinge <tschwinge@baylibre.com>
* config/nvptx/nvptx.cc (TARGET_ASM_NEED_VAR_DECL_BEFORE_USE):
Don't '#define'.
2025-04-17 Hans-Peter Nilsson <hp@axis.com>
* combine.cc: Correct comments about combine_validate_cost.
2025-04-16 Sandra Loosemore <sloosemore@baylibre.com>
PR c/88382
* doc/extend.texi (Syntax Extensions): Adjust menu.
(Raw String Literals): New section.
2025-04-16 Keith Packard <keithp@keithp.com>
* config/rx/rx.md (cmpstrnsi): Allow constant length. For
static length 0, just store 0 into the output register.
For dynamic zero, set C/Z appropriately.
(rxcmpstrn): No longer set C/Z.
2025-04-16 Eric Botcazou <ebotcazou@gcc.gnu.org>
* tree-ssa-phiopt.cc (factor_out_conditional_operation): Do not
bypass the int_fits_type_p test for boolean types whose precision
is not 1.
2025-04-16 Sandra Loosemore <sloosemore@baylibre.com>
* common.opt.urls: Regenerated.
2025-04-16 Ard Biesheuvel <ardb@kernel.org>
PR target/119386
* config/i386/i386-options.cc: Permit -mnop-mcount when
using -fpic with PLTs.
2025-04-16 Ard Biesheuvel <ardb@kernel.org>
PR target/119386
* config/i386/i386.cc (x86_print_call_or_nop): Add @PLT suffix
where appropriate.
(x86_function_profiler): Fall through to x86_print_call_or_nop()
for PIC codegen when flag_plt is set.
2025-04-16 Sandra Loosemore <sloosemore@baylibre.com>
PR driver/90465
* doc/invoke.texi (Overall Options): Add a @cindex for -Q in
connection with --help=.
(Developer Options): Point at --help= documentation for the
other use of -Q.
2025-04-16 Thomas Schwinge <tschwinge@baylibre.com>
PR target/97106
* config/nvptx/nvptx.cc (nvptx_asm_output_def_from_decls)
[ACCEL_COMPILER]: Make sure to emit C++ constructor, destructor
aliases.
2025-04-16 Jan Hubicka <hubicka@ucw.cz>
PR tree-optimization/119614
* ipa-prop.cc (ipa_write_return_summaries): New function.
(ipa_record_return_value_range_1): Break out from ....
(ipa_record_return_value_range): ... here.
(ipa_read_return_summaries): New function.
(ipa_prop_read_section): Read return summaries.
(read_ipcp_transformation_info): Read return summaries.
(ipcp_write_transformation_summaries): Write return summaries;
do not stream stray 0.
2025-04-16 Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/119351
* tree-vectorizer.h (LOOP_VINFO_MASK_NITERS_PFA_OFFSET,
LOOP_VINFO_NON_LINEAR_IV): New.
(class _loop_vec_info): Add mask_skip_niters_pfa_offset and
nonlinear_iv.
* tree-vect-loop.cc (_loop_vec_info::_loop_vec_info): Initialize them.
(vect_analyze_scalar_cycles_1): Record non-linear inductions.
(vectorizable_induction): If early break and PFA using masking create a
new phi which tracks where the scalar code needs to start...
(vectorizable_live_operation): ...and generate the adjustments here.
(vect_use_loop_mask_for_alignment_p): Reject non-linear inductions and
early break needing peeling.
2025-04-16 Jakub Jelinek <jakub@redhat.com>
PR middle-end/119808
* gimple-lower-bitint.cc (gimple_lower_bitint): Don't set
m_single_use_names bits for SSA_NAMEs which have single use but
their SSA_NAME_DEF_STMT is a copy from another SSA_NAME which doesn't
have a single use, or single use which is such a copy etc.
2025-04-16 Jesse Huang <jesse.huang@sifive.com>
* config/riscv/riscv.cc (riscv_file_end): Fix .p2align value.
2025-04-16 Kito Cheng <kito.cheng@sifive.com>
* config/riscv/riscv.h (JUMP_TABLES_IN_TEXT_SECTION): Check if
large code model.
2025-04-16 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-sve.md (vec_extract<vpred><Vel>): Fix operand
order to gen_vcond_mask_*.
2025-04-16 Alice Carlotti <alice.carlotti@arm.com>
* config/aarch64/aarch64.cc
(aarch64_valid_sysreg_name_p): Remove feature check.
(aarch64_retrieve_sysreg): Ditto.
2025-04-15 Sandra Loosemore <sloosemore@baylibre.com>
PR tree-optimization/71094
* doc/invoke.texi (Optimize Options): Document that -fivopts is
enabled at -O1 and higher. Add blurb about -O0 causing GCC to
completely ignore most optimization options.
2025-04-15 Iain Sandoe <iain@sandoe.co.uk>
* configure: Regenerate.
* configure.ac: Recognise PROJECT:ld-mmmm.nn.aa as an identifier
for Darwin's static linker.
2025-04-15 Iain Sandoe <iainsandoe@mini-05-seq.local>
PR target/116827
* ginclude/stddef.h: Undefine __PTRDIFF_T and __SIZE_T for module-
enabled c++ on Darwin/macOS platforms.
2025-04-15 Kyrylo Tkachov <ktkachov@nvidia.com>
* common.opt.urls: Regenerate.
2025-04-15 Jan Hubicka <hubicka@ucw.cz>
* config/i386/x86-tune-sched.cc (ix86_issue_rate): Set
to 4 for znver5.
2025-04-15 Jan Hubicka <hubicka@ucw.cz>
PR target/119298
* config/i386/x86-tune-costs.h (znver5_cost): Set ADDSS cost to 3.
2025-04-15 Vineet Gupta <vineetg@rivosinc.com>
PR target/119533
* config/riscv/riscv-vsetvl.cc (invalid_opt_bb_p): Check for
EDGE_ABNOMAL.
(pre_vsetvl::compute_lcm_local_properties): Initialize kill
bitmap.
Debug dump skipped edge.
2025-04-15 Robin Dapp <rdapp@ventanamicro.com>
PR target/119547
* config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info):
Do not perform lift if block is not transparent.
2025-04-15 Kyrylo Tkachov <ktkachov@nvidia.com>
* Makefile.in (OBJS): Add ipa-locality-cloning.o.
* cgraph.h (set_new_clone_decl_and_node_flags): Declare prototype.
* cgraphclones.cc (set_new_clone_decl_and_node_flags): Remove static
qualifier.
* common.opt (fipa-reorder-for-locality): New flag.
(LTO_PARTITION_DEFAULT): Declare.
(flto-partition): Change default to LTO_PARTITION_DFEAULT.
* doc/invoke.texi: Document -fipa-reorder-for-locality.
* flag-types.h (enum lto_locality_cloning_model): Declare.
(lto_partitioning_model): Add LTO_PARTITION_DEFAULT.
* lto-cgraph.cc (lto_set_symtab_encoder_in_partition): Add dumping of
node and index.
* opts.cc (validate_ipa_reorder_locality_lto_partition): Define.
(finish_options): Handle LTO_PARTITION_DEFAULT.
* params.opt (lto_locality_cloning_model): New enum.
(lto-partition-locality-cloning): New param.
(lto-partition-locality-frequency-cutoff): Likewise.
(lto-partition-locality-size-cutoff): Likewise.
(lto-max-locality-partition): Likewise.
* passes.def: Register pass_ipa_locality_cloning.
* timevar.def (TV_IPA_LC): New timevar.
* tree-pass.h (make_pass_ipa_locality_cloning): Declare.
* ipa-locality-cloning.cc: New file.
* ipa-locality-cloning.h: New file.
2025-04-15 Martin Jambor <mjambor@suse.cz>
Jakub Jelinek <jakub@redhat.com>
PR ipa/119803
* ipa-cp.cc (ipcp_bits_lattice::meet_with_1): Move m_value adjustmed
according to m_mask below the adjustment of the latter according to
cap_mask. Optimize the calculation of cap_mask a bit.
(ipcp_bits_lattice::meet_with): Optimize the calculation of cap_mask a
bit.
2025-04-15 Jakub Jelinek <jakub@redhat.com>
* ipa-cp.cc (ipcp_print_widest_int): Print values with all ones in
bits 128+ with "0xf..f" prefix instead of "all ones folled by ".
Simplify wide_int check for -1 or all ones above least significant
128 bits.
2025-04-15 Jakub Jelinek <jakub@redhat.com>
PR sanitizer/119801
* sanitizer.def (BUILT_IN_TSAN_FUNC_EXIT): Use BT_FN_VOID rather
than BT_FN_VOID_PTR.
* tree-tailcall.cc: Include attribs.h and asan.h.
(struct tailcall): Add has_tsan_func_exit member.
(empty_eh_cleanup): Add eh_has_tsan_func_exit argument, set what
it points to to 1 if there is exactly one __tsan_func_exit call
and ignore that call otherwise. Adjust recursive call.
(find_tail_calls): Add RETRY_TSAN_FUNC_EXIT argument, pass it
to recursive calls. When seeing __tsan_func_exit call with
RETRY_TSAN_FUNC_EXIT 0, set it to -1. If RETRY_TSAN_FUNC_EXIT
is 1, initially ignore __tsan_func_exit calls. Adjust
empty_eh_cleanup caller. When looking through stmts after the call,
ignore exactly one __tsan_func_exit call but remember it in
t->has_tsan_func_exit. Diagnose if EH cleanups didn't have
__tsan_func_exit and normal path did or vice versa.
(optimize_tail_call): Emit __tsan_func_exit before the tail call
or tail recursion.
(tree_optimize_tail_calls_1): Adjust find_tail_calls callers. If
find_tail_calls changes retry_tsan_func_exit to -1, set it to 1
and call it again with otherwise the same arguments.
2025-04-15 Sandra Loosemore <sloosemore@baylibre.com>
PR ipa/113203
* doc/extend.texi (Common Function Attributes): Explain how to
use always_inline in programs that have multiple translation
units, and that LTO inlining additionally needs optimization
enabled.
2025-04-15 liuhongt <hongtao.liu@intel.com>
PR target/108134
* doc/extend.texi: Remove documents from r11-344-g0fec3f62b9bfc0.
2025-04-15 Sandra Loosemore <sloosemore@baylibre.com>
PR target/42683
* doc/invoke.texi (x86 Options): Clarify that -march=pentiumpro
doesn't include MMX.
2025-04-14 Thomas Schwinge <tschwinge@baylibre.com>
PR target/118794
* config/gcn/gcn.opt (-mfake-exceptions): Support.
* config/nvptx/nvptx.opt (-mfake-exceptions): Likewise.
* config/gcn/gcn.md (define_expand "exception_receiver"): Use it.
* config/nvptx/nvptx.md (define_expand "exception_receiver"):
Likewise.
* config/gcn/mkoffload.cc (main): Set it.
* config/nvptx/mkoffload.cc (main): Likewise.
* config/nvptx/nvptx.cc (nvptx_assemble_integer)
<in_section == exception_section>: Special handling for
'SYMBOL_REF's.
* except.cc (expand_dw2_landing_pad_for_region): Don't generate
bogus code for (default)
'#define EH_RETURN_DATA_REGNO(N) INVALID_REGNUM'.
2025-04-14 Jakub Jelinek <jakub@redhat.com>
PR rtl-optimization/119785
* expmed.cc (init_expmed): Always pass QImode rather than mode to
set_src_cost passed to set_zero_cost.
2025-04-14 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/119718
* tree-pretty-print.cc (dump_generic_node) <case CALL_EXPR>: Dump
also CALL_EXPR_MUST_TAIL_CALL flag.
* calls.cc (maybe_complain_about_tail_call): Emit error about
CALL_EXPR_MUST_TAIL_CALL only after emitting dump message, not before
it.
2025-04-14 Arthur Cohen <arthur.cohen@embecosm.com>
* doc/install.texi: Add requirements for building gccrs.
2025-04-14 H.J. Lu <hjl.tools@gmail.com>
PR target/119784
* config/i386/i386.cc (ix86_using_red_zone): Don't use red-zone
with 32 GPRs and no caller-saved registers.
2025-04-14 Martin Jambor <mjambor@suse.cz>
PR ipa/118097
* ipa-cp.cc (ipa_get_jf_arith_result): Require res_operand for
anything except NOP_EXPR or ADDR_EXPR, document it and remove the code
trying to deduce it.
(ipa_value_from_jfunc): Use the stored and streamed type of arithmetic
pass-through functions.
(ipa_agg_value_from_jfunc): Use the stored and streamed type of
arithmetic pass-through functions, convert to the type used to store
the value if necessary.
(get_val_across_arith_op): New parameter op_type, pass it to
ipa_get_jf_arith_result.
(propagate_vals_across_arith_jfunc): New parameter op_type, pass it to
get_val_across_arith_op.
(propagate_vals_across_pass_through): Use the stored and streamed type
of arithmetic pass-through functions.
(propagate_aggregate_lattice): Likewise.
(push_agg_values_for_index_from_edge): Use the stored and streamed
type of arithmetic pass-through functions, convert to the type used to
store the value if necessary.
2025-04-14 Martin Jambor <mjambor@suse.cz>
PR ipa/118785
* ipa-cp.cc (ipa_vr_intersect_with_arith_jfunc): Use the stored
and streamed type of arithmetic pass-through functions.
2025-04-14 Martin Jambor <mjambor@suse.cz>
* ipa-cp.cc (ipcp_print_widest_int): Also add a truncated form of
dumping of widest ints which only have zeros in the lowest 128 bits.
Update the comment.
(ipcp_bits_lattice::print): Also dump the mask using
ipcp_print_widest_int.
(ipcp_store_vr_results): Likewise.
2025-04-14 Martin Jambor <mjambor@suse.cz>
PR ipa/119318
* ipa-cp.cc (ipcp_bits_lattice::meet_with_1): Set all mask bits
not covered by precision to one.
(ipcp_bits_lattice::meet_with): Likewise.
(propagate_bits_across_jump_function): Use the stored operation
type to perform meet with other lattices.
2025-04-14 Martin Jambor <mjambor@suse.cz>
PR ipa/118097
PR ipa/118785
PR ipa/119318
* lto-streamer.h (lto_variably_modified_type_p): Declare.
* ipa-prop.h (ipa_pass_through_data): New field op_type.
(ipa_get_jf_pass_through_op_type): New function.
* ipa-prop.cc: Include lto-streamer.h.
(ipa_dump_jump_function): Dump also pass-through
operation types, if any. Dump pass-through operands only if not NULL.
(ipa_set_jf_simple_pass_through): Set op_type accordingly.
(compute_complex_assign_jump_func): Set op_type of arithmetic
pass-through jump_functions.
(analyze_agg_content_value): Update lhs when walking assighment
copies. Set op_type of aggregate arithmetic pass-through
jump_functions.
(update_jump_functions_after_inlining): Also transfer the operation
type from the source arithmentic pass-through jump function to the
destination jump function.
(ipa_write_jump_function): Stream also the op_type when necessary.
(ipa_read_jump_function): Likewise.
(ipa_agg_pass_through_jf_equivalent_p): Also compare operation types.
* lto-streamer-out.cc (lto_variably_modified_type_p): Make public.
2025-04-14 Richard Biener <rguenther@suse.de>
PR tree-optimization/119757
* tree-vect-slp.cc (vect_build_slp_tree_1): Record and compare
whether a stmt uses a maks.
2025-04-14 Richard Biener <rguenther@suse.de>
PR tree-optimization/119778
* tree-inline.cc (copy_edges_for_bb): Mark calls that are
source of abnormal edges as altering control-flow.
2025-04-14 Gaius Mulley <gaiusmod2@gmail.com>
PR modula2/119779
* doc/gm2.texi (Interface to assembly language): Use eax
rather than rax in both examples.
2025-04-14 Jakub Jelinek <jakub@redhat.com>
PR driver/119727
* configure.ac (HOST_HAS_PERSONALITY_ADDR_NO_RANDOMIZE): New check.
* gcc.cc: Include sys/personality.h if
HOST_HAS_PERSONALITY_ADDR_NO_RANDOMIZE is defined.
(try_generate_repro): Call
personality (personality (0xffffffffU) | ADDR_NO_RANDOMIZE)
if HOST_HAS_PERSONALITY_ADDR_NO_RANDOMIZE is defined.
* config.in: Regenerate.
* configure: Regenerate.
2025-04-13 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* config/s390/s390.cc: Add z17 scheduler description.
* config/s390/s390.h: Ditto.
* config/s390/s390.md: Ditto.
* config/s390/9175.md: New file.
2025-04-13 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* common/config/s390/s390-common.cc: Rename arch15 to z17.
* config.gcc: Add z17.
* config/s390/driver-native.cc: Detect z17 machine.
* config/s390/s390-builtins.def (B_VXE3): Rename arch15 to z17.
* config/s390/s390-c.cc (s390_resolve_overloaded_builtin): Ditto.
* config/s390/s390-opts.h (enum processor_type): Ditto.
* config/s390/s390.cc: Ditto.
* config/s390/s390.h: Ditto.
* config/s390/s390.md: Ditto.
* config/s390/s390.opt: Add z17.
* doc/invoke.texi: Ditto.
2025-04-12 Sandra Loosemore <sloosemore@baylibre.com>
PR target/97585
* doc/invoke.texi (x86 Options): Document list of extensions
supported by -march=x86_64, according to the declaration of
PTA_X86_64_BASELINE in config/i386/i386.h.
2025-04-12 Jakub Jelinek <jakub@redhat.com>
PR driver/119727
* gcc.cc (files_equal_p): Rewritten using fopen/fgets/fclose instead
of open/fstat/read/close. At the start of lines, ignore lowercase
hexadecimal addresses followed by space.
2025-04-12 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/119722
* gimple-lower-bitint.h (build_bitint_stmt_ssa_conflicts): Add
CLEAR argument.
* gimple-lower-bitint.cc (build_bitint_stmt_ssa_conflicts): Add
CLEAR argument. Call clear on gimple_assign_copy_p rhs1 if lhs
is large/huge bitint unless lhs is not in names.
* tree-ssa-coalesce.cc (build_ssa_conflict_graph): Adjust
build_bitint_stmt_ssa_conflicts caller. Move gimple_assign_copy_p
handling to after the build_bitint_stmt_ssa_conflicts call.
2025-04-12 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/119718
* tree-tailcall.cc (maybe_error_musttail): Dump the GIMPLE at the
end of the Cannot tail-call line rather than on the line before it.
* calls.cc (maybe_complain_about_tail_call): Dump the GENERIC
at the end of the ;; Cannot tail-call line rather than on the
line before it.
2025-04-12 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/119718
* tree-tailcall.cc (maybe_error_musttail): Only dump into dump_file
if dump_flags & TDF_DETAILS. Use "Cannot tail-call: " prefix instead
of "Cannot convert: ".
(find_tail_calls, tree_optimize_tail_calls_1): Formatting fixes
for maybe_error_musttail calls.
* calls.cc (maybe_complain_about_tail_call): Emit also a message
into dump_file when dump_flags & TDF_DETAILS for CALL_EXPR_TAILCALL
calls.
(initialize_argument_information): Formatting fix for
maybe_complain_about_tail_call calls.
(can_implement_as_sibling_call_p, expand_call): Likewise.
2025-04-11 Sandra Loosemore <sloosemore@baylibre.com>
PR c++/106618
* doc/invoke.texi (Option Summary): Remove -fargs-in-order, add
-fstrong-eval-order.
(C++ Dialect Options): Explicitly document that -fstrong-eval-order
takes an optional argument and what the choices are. Generalize
references to C++17.
2025-04-11 Sandra Loosemore <sloosemore@baylibre.com>
PR middle-end/105548
* doc/invoke.texi (Optimize Options): Delete misleading sentence
about conversions.
2025-04-11 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/119707
* gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Only use
m_data[save_data_cnt] instead of m_data[save_data_cnt + 1] if
idx is odd and equal to low + 1. Remember tree_to_uhwi (idx) in
a temporary instead of calling the function multiple times.
2025-04-11 Sandra Loosemore <sloosemore@baylibre.com>
PR tree-optimization/87909
* common.opt.urls: Regenerate.
* doc/invoke.texi (Option Summary): Add -ftree-cselim.
(Optimize Options): Likewise.
2025-04-11 Sandra Loosemore <sloosemore@baylibre.com>
PR middle-end/14708
* doc/invoke.texi (Optimize Options): List -fexcess-precision
before -ffloat-store, moving some background discussion to the
former from the latter. Recommend using -fexcess-precision=standard
instead of -ffloat-store.
2025-04-10 Iain Sandoe <iain@sandoe.co.uk>
* config/darwin.h (LINK_SPEC): Add support for
-static-libgcobol.
2025-04-10 Richard Biener <rguenther@suse.de>
PR middle-end/119706
* gimple-expr.cc (is_gimple_mem_ref_addr): Also allow
POLY_INT_CST.
2025-04-10 Richard Sandiford <richard.sandiford@arm.com>
PR tree-optimization/119399
* tree-data-ref.cc (create_waw_or_war_checks): Use a MINUS_EXPR
on two converted pointers, rather than converting a POINTER_DIFF_EXPR
on the pointers.
2025-04-10 Kito Cheng <kito.cheng@sifive.com>
* config/riscv/multilib-generator: Remove the compact code model
and check large code model for RV32.
2025-04-09 Jakub Jelinek <jakub@redhat.com>
* pretty-print.cc (pretty_printer::format): Use %.Ns instead of
%Ns in function comment.
2025-04-09 Jakub Jelinek <jakub@redhat.com>
PR target/119664
* config/h8300/jumpcall.md (bit test and jump define_insn_and_split):
Use HSI iterator rather than QHSI.
2025-04-09 Jakub Jelinek <jakub@redhat.com>
* config/riscv/riscv-vector-builtins.cc (verify_type_context):
Diagnose RVV types for a given OpenMP context.
2025-04-09 Richard Biener <rguenther@suse.de>
PR rtl-optimization/119689
PR rtl-optimization/115568
* lra-remat.cc (create_cands): Use prev_nonnote_nondebug_insn
to check whether insn2 is directly before insn.
2025-04-09 Robin Dapp <rdapp@ventanamicro.com>
PR middle-end/116595
* expr.cc (categorize_ctor_elements_1): Use
constant_lower_bound.
2025-04-09 Yang Yujie <yangyujie@loongson.cn>
* config/loongarch/genopts/gen-evolution.awk: remove
usage of "asort".
* config/loongarch/genopts/genstr.sh: replace sed with awk.
2025-04-08 Sandra Loosemore <sloosemore@baylibre.com>
PR c++/90468
* doc/invoke.texi (Warning Options): Clean up text describing
-Wno-xxx.
2025-04-08 Jakub Jelinek <jakub@redhat.com>
PR rtl-optimization/119672
* simplify-rtx.cc (simplify_context::simplify_relational_operation_1):
For POPCOUNT == 0 or != 0 optimizations use
CONST0_RTX (GET_MODE (XEXP (op0, 0))) rather than const0_rtx.
2025-04-08 Tobias Burnus <tburnus@baylibre.com>
PR middle-end/119662
* gimplify.cc (modify_call_for_omp_dispatch): Fix GOMP_interop
arg passing; add location info to function calls.
2025-04-08 Jakub Jelinek <jakub@redhat.com>
PR target/119678
* config/riscv/freebsd.h (LINK_SPEC): Use FBSD_LINK_PG_NOTE rather
than non-existing FBSD_LINK_PG_NOTES.
2025-04-08 Thomas Schwinge <tschwinge@baylibre.com>
* config/nvptx/nvptx.cc (nvptx_asm_output_def_from_decls)
[!ACCEL_COMPILER]: Don't define label 'emit_ptx_alias'.
2025-04-08 Jakub Jelinek <jakub@redhat.com>
PR rtl-optimization/119594
* cse.cc (count_reg_usage): Count even x == dest regs if they have
non-zero counts already and incr is positive.
2025-04-08 Jakub Jelinek <jakub@redhat.com>
PR lto/119625
* lto-opts.cc (lto_write_options): Mask of CF_SET from
global_options.x_flag_cf_protection.
2025-04-08 Tejas Belagod <tejas.belagod@arm.com>
Andrea Corallo <andrea.corallo@arm.com>
* target.h (type_context_kind): Add new context kinds for target clauses.
(omp_type_context): Query if the context is of OMP kind.
* config/aarch64/aarch64-sve-builtins.cc (verify_type_context): Diagnose
SVE types for a given OpenMP context.
(omp_type_context): New.
* gimplify.cc (omp_notice_variable): Diagnose implicitly-mapped SVE
objects in OpenMP regions.
(gimplify_scan_omp_clauses): Diagnose SVE types for various target
clauses.
2025-04-08 Tejas Belagod <tejas.belagod@arm.com>
* tree.h (strip_pointer_types): New.
2025-04-08 Richard Sandiford <richard.sandiford@arm.com>
Tejas Belagod <tejas.belagod@arm.com>
PR middle-end/101018
* poly-int.h (can_and_p): New function.
* fold-const.cc (poly_int_binop): Use it to optimize BIT_AND_EXPRs
involving POLY_INT_CSTs.
* gimplify.cc (omp_notice_variable): Use poly_int_tree_p instead
of INTEGER_CST when checking for constant-sized omp data.
(gimplify_adjust_omp_clauses_1): Likewise.
(gimplify_adjust_omp_clauses): Likewise.
* omp-low.cc (scan_sharing_clauses): Likewise.
2025-04-08 Haochen Jiang <haochen.jiang@intel.com>
* config/i386/i386.h (PTA_DIAMONDRAPIDS): Add PTA_AVX10_1_256.
2025-04-08 Jin Ma <jinma@linux.alibaba.com>
* config/riscv/vector.md: Disable vsext/vzext for XTheadVector.
2025-04-07 Iain Sandoe <iain@sandoe.co.uk>
PR target/113257
* config/aarch64/aarch64-cores.def (AARCH64_CORE): Add Apple-a12,
Apple-M1, Apple-M2, Apple-M3 with expanded names to allow for the
LITTLE.big versions.
* config/aarch64/aarch64-tune.md: Regenerate.
* doc/invoke.texi: Add apple-m1,2 and 3 cores to the ones listed
for arch and tune selections.
2025-04-07 Thomas Schwinge <tschwinge@baylibre.com>
* config/nvptx/nvptx.opt (-mfake-ptx-alloca): Update.
2025-04-07 Martin Jambor <mjambor@suse.cz>
PR tree-optimization/118924
* tree-sra.cc (create_total_scalarization_access): Set
grp_same_access_path flag to zero.
2025-04-07 Martin Jambor <mjambor@suse.cz>
PR tree-optimization/118924
* tree-ssa-alias-compare.h (types_equal_for_same_type_for_tbaa_p):
Declare.
* tree-ssa-alias.cc: Include ipa-utils.h.
(types_equal_for_same_type_for_tbaa_p): New public overloaded variant.
* tree-sra.cc: Include tree-ssa-alias-compare.h.
(create_access): Initialzie grp_same_access_path to true.
(build_accesses_from_assign): Detect tbaa hazards and clear
grp_same_access_path fields of involved accesses when they occur.
(sort_and_splice_var_accesses): Take previous values of
grp_same_access_path into account.
2025-04-07 Richard Biener <rguenther@suse.de>
PR tree-optimization/119640
* tree-vect-stmts.cc (vectorizable_shift): Always insert code
for one of our SLP operands before the code for the vector
shift itself.
2025-04-07 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/119614
* tree-tailcall.cc (find_tail_calls): Remember edges which have been
walked through if !ass_var. Perform IPA-VRP workaround even when
ret_var is not TREE_CONSTANT, in that case check in a loop if it is
a PHI result and in that case look at the PHI argument from
corresponding edge in the edge vector.
2025-04-07 Richard Sandiford <richard.sandiford@arm.com>
PR testsuite/116398
* params.opt (-param=max-combine-search-insns=): New param.
* doc/invoke.texi: Document it.
* combine.cc (insn_link::insn_count): New field.
(alloc_insn_link): Initialize it.
(distribute_links): Add a limit parameter.
(try_combine): Use the new param to limit distribute_links
when only i3 has changed.
2025-04-07 Richard Sandiford <richard.sandiford@arm.com>
PR testsuite/116398
* combine.cc (distribute_links): Take an optional start point.
(try_combine): If only i3 has changed, only distribute i3's links,
not i2's. Start the search for the new use from i3 rather than
from the definition instruction. Likewise start the search for
the new use from i2 when distributing i2's links.
2025-04-07 Richard Sandiford <richard.sandiford@arm.com>
PR testsuite/116398
* combine.cc (try_combine): Shortcut the split_i2i3 handling if
i2 is unchanged.
2025-04-07 Richard Sandiford <richard.sandiford@arm.com>
Richard Biener <rguenther@suse.de>
PR testsuite/116398
* combine.cc (try_combine): Reallow 2->2 combinations. Detect when
only i3 has changed and restart from i3 in that case.
2025-04-07 Richard Sandiford <richard.sandiford@arm.com>
* simplify-rtx.cc (simplify_const_relational_operation): Generalize
the constant checks in the fold-via-minus path to match the
INTEGRAL_MODE_P condition.
2025-04-06 Sandra Loosemore <sloosemore@baylibre.com>
* doc/extend.texi (Boolean Type): Further clarify support for
_Bool in C23 and C++.
2025-04-06 Sandra Loosemore <sloosemore@baylibre.com>
PR middle-end/78874
* doc/invoke.texi (Warning Options): Fix description of
-Wno-aggressive-loop-optimizations to reflect that this turns
off the warning, and the default is for it to be enabled.
2025-04-06 Sandra Loosemore <sloosemore@baylibre.com>
PR c/81831
* doc/invoke.texi (Option Summary): Add -Wno-psabi.
(Warning Options): Document -Wpsabi separately from -Wabi.
Note it's enabled by default, not just implied by -Wabi.
Replace the detailed example for a GCC 4.4 change for x86
(which is unlikely to be very interesting nowadays) with
just a list of all targets that presently diagnose these
warnings.
(RS/6000 and PowerPC Options): Add cross-references for
-Wno-psabi.
2025-04-05 Sandra Loosemore <sloosemore@baylibre.com>
PR middle-end/112589
* common.opt (-fcf-protection): Add documentation string.
* doc/invoke.texi (Option Summary): Add entry for -fcf-protection
without argument.
(Instrumentation Options): Tidy the -fcf-protection entry and
and add documention for the form without an argument.
2025-04-04 Jakub Jelinek <jakub@redhat.com>
PR lto/119625
* lto-opts.cc (lto_write_options): If neither flag_pic nor
flag_pie are set, check first for flag_pie and only later
for flag_pic rather than the other way around, use a temporary
variable. If flag_cf_protection is not set, don't append anything
if flag_cf_protection is none of CF_{NONE,FULL,BRANCH,RETURN} and
use a temporary variable.
2025-04-04 Jakub Jelinek <jakub@redhat.com>
PR gcov-profile/119618
* profile.cc (branch_prob): Only check for musttail calls if
cfun->has_musttail. Use gsi_last_nondebug_bb instead of gsi_last_bb.
2025-04-04 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/119616
* tree-tailcall.cc (suitable_for_tail_call_opt_p): Move checking
for addressable parameters from here ...
(find_tail_calls): ... here. If cfun->has_musttail, don't clear
opt_tailcalls for it, instead set a local flag and punt if we can't
tail recurse optimize it.
2025-04-04 Jakub Jelinek <jakub@redhat.com>
PR middle-end/119613
* cfgrtl.cc (purge_dead_edges): Remove REG_EH_REGION notes from
tail calls.
2025-04-04 Jakub Jelinek <jakub@redhat.com>
PR target/115910
* rtlanal.cc (pattern_cost): Return at least COSTS_N_INSNS (1)
rather than just COSTS_N_INTNS (1) for cost <= 0.
* config/i386/i386.cc (ix86_rtx_costs): Set *total to 1 for
TARGET_64BIT x86_64_zext_immediate_operand constants.
2025-04-04 Andrew Pinski <quic_apinski@quicinc.com>
PR ipa/119599
* tree-cfg.cc (pass_warn_function_return::execute): Turn return statements always
into __builtin_unreachable calls.
2025-04-04 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/119614
* tree-tailcall.cc (find_tail_calls): Handle also pointer types in the
IPA-VRP workaround.
2025-04-03 Thomas Schwinge <tschwinge@baylibre.com>
PR target/119573
* config/nvptx/nvptx.cc (nvptx_encode_section_info): Don't set
'DATA_AREA_CONST' for 'TREE_CONSTANT', or 'TREE_READONLY'.
(nvptx_asm_declare_constant_name): Use '.global' instead of
'.const'.
2025-04-03 Peter Bergner <bergner@linux.ibm.com>
PR target/119308
* config/rs6000/rs6000-logue.cc (rs6000_output_function_epilogue):
Handle GCC COBOL for the tbtab lang field.
2025-04-03 Sandra Loosemore <sloosemore@baylibre.com>
* doc/extend.texi (Statement Attributes): Copy-edit the musttail
attribute documentation and correct the comment in the last
example.
2025-04-03 Jan Hubicka <hubicka@ucw.cz>
* config/i386/x86-tune-costs.h (ix86_size_cost): Fix sizes of move
instructions
2025-04-03 Jakub Jelinek <jakub@redhat.com>
PR cobol/119242
* fold-const.h (native_encode_wide_int): Declare.
* fold-const.cc (native_encode_wide_int): New function.
(native_encode_int): Use it.
2025-04-03 Xi Ruoyao <xry111@xry111.site>
* config/loongarch/genopts/gen-evolution.awk: Avoid using gensub
that FreeBSD awk lacks.
2025-04-03 Hongyu Wang <hongyu.wang@intel.com>
PR target/119539
* config/i386/i386.md (*<insn><mode>3_mask): Emit NF variant of
rotate when APX_NF enabled, and use force_lowpart_subreg.
(*<insn><mode>3_mask_1): Likewise.
2025-04-03 Sandra Loosemore <sloosemore@baylibre.com>
PR c/101440
* doc/extend.texi (Common Function Attributes): Clean up some
confusing language in the description of the "access" attribute.
2025-04-02 Sandra Loosemore <sloosemore@baylibre.com>
GUO Yixuan <culu.gyx@gmail.com>
PR driver/58973
* common.opt (Werror, Werror=): Use less awkward wording in
description.
(pedantic-errors): Likewise.
* doc/invoke.texi (Warning Options): Likewise for -Werror and
-Werror= here.
2025-04-02 Robin Dapp <rdapp@ventanamicro.com>
PR target/119572
* config/riscv/autovec.md: Mask broadcast value.
2025-04-02 Jin Ma <jinma@linux.alibaba.com>
* config/riscv/bitmanip.md: The optimization can only be applied if
the high bit of operands[3] is set to 1.
2025-04-02 Sandra Loosemore <sloosemore@baylibre.com>
PR c/114957
PR c/78008
PR c++/60972
* doc/extend.texi (Structure-Layout Pragmas): Add @cindex
entries and reformat the pragma descriptions to match the markup
used for other pragmas. Document what #pragma pack(0) does.
Add cross-references to similar attributes.
2025-04-02 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/119491
* tree-tailcall.cc (single_non_eh_succ_edge): New function.
(independent_of_stmt_p): Use single_non_eh_succ_edge (bb)->dest
instead of single_succ (bb).
(empty_eh_cleanup): New function.
(find_tail_calls): Diagnose throwing of exceptions which do not
propagate only if there are no EDGE_EH successor edges. If there are
and the call is musttail, use empty_eh_cleanup to find if the cleanup
is not empty. If not or the call is not musttail, use different
diagnostics. Set is_noreturn even if there are successor edges. Use
single_non_eh_succ_edge (abb) instead of single_succ_edge (abb). Punt
on internal noreturn calls.
(decrease_profile): Don't assert 0 or 1 successor edges.
(eliminate_tail_call): Use
single_non_eh_succ_edge (gsi_bb (t->call_gsi)) instead of
single_succ_edge (gsi_bb (t->call_gsi)).
(tree_optimize_tail_calls_1): Also look into basic blocks with
single succ edge which is EDGE_EH for noreturn musttail calls.
2025-04-02 Richard Biener <rguenther@suse.de>
PR tree-optimization/119586
* tree-vect-stmts.cc (vectorizable_load): Assume we got
alignment analysis for VMAT_STRIDED_SLP wrong.
(vectorizable_store): Likewise.
2025-04-02 Jakub Jelinek <jakub@redhat.com>
* doc/extend.texi (musttail statement attribute): Hint how
to avoid -Wmaybe-musttail-local-addr warnings.
2025-04-02 Jakub Jelinek <jakub@redhat.com>
PR ipa/119376
* common.opt (Wmusttail-local-addr, Wmaybe-musttail-local-addr): New.
* tree-tailcall.cc (suitable_for_tail_call_opt_p): Don't fail for
TREE_ADDRESSABLE PARM_DECLs for musttail calls if diag_musttail.
Emit -Wmusttail-local-addr warnings.
(maybe_error_musttail): Use gimple_location instead of directly
accessing location member.
(find_tail_calls): For musttail calls if diag_musttail, don't fail
if address of local could escape to the call, instead emit
-Wmaybe-musttail-local-addr warnings. Emit
-Wmaybe-musttail-local-addr warnings also for address taken
parameters.
* common.opt.urls: Regenerate.
* doc/extend.texi (musttail statement attribute): Clarify local
variables without non-trivial destruction are considered out of scope
before the tail call instruction.
* doc/invoke.texi (-Wno-musttail-local-addr,
-Wmaybe-musttail-local-addr): Document.
2025-04-02 Andi Kleen <ak@gcc.gnu.org>
PR middle-end/119482
* bitmap.cc (bitmap_set_bit): Write back value unconditionally
2025-04-02 Sandra Loosemore <sloosemore@baylibre.com>
PR c++/118982
* doc/extend.texi (Common Function Attributes): For the
constructor/destructory attribute, be more explicit about the
relationship between the constructor attribute and
the C++ init_priority attribute, and add a cross-reference.
Also document that most targets support this.
(C++ Attributes): Similarly for the init_priority attribute.
2025-04-01 Sandra Loosemore <sloosemore@baylibre.com>
PR c/118118
* doc/extend.texi (Boolean Type): New section.
2025-04-01 Sandra Loosemore <sloosemore@baylibre.com>
PR c/117689
* doc/extend.texi (Incomplete Enums): Rename to....
(Enum Extensions): This. Document support for specifying the
underlying type of an enum as an extension in all earlier C
and C++ standards. Document that a forward declaration with
underlying type is not an incomplete type, and which dialects
GCC supports that in.
2025-04-01 Tom Tromey <tromey@adacore.com>
* dwarf2out.cc (modified_type_die): Use mod_scope for
ranged types, base types, and array types.
2025-04-01 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/119493
* tree-tailcall.cc (find_tail_calls): Don't punt on tail recusion
if some arguments don't have is_gimple_reg_type, only punt if they
have non-POD types, or volatile, or addressable or (for now) it is
not a musttail call. Set tailr_arg_needs_copy in those cases too.
(eliminate_tail_call): Copy call arguments to params if they don't
have is_gimple_reg_type, use temporaries if the argument is used
later.
(tree_optimize_tail_calls_1): Skip !is_gimple_reg_type
tailr_arg_needs_copy parameters. Formatting fix.
2025-04-01 Jakub Jelinek <jakub@redhat.com>
PR rtl-optimization/119291
* combine.cc (try_combine): For splitting of PARALLEL with
2 independent SETs into i2 and i3 sets check reg_used_between_p
of the SET_DESTs rather than just modified_between_p.
2025-04-01 Richard Biener <rguenther@suse.de>
PR tree-optimization/119534
* tree-vect-stmts.cc (get_load_store_type): Reject
VECTOR_BOOLEAN_TYPE_P offset vector type for emulated gathers.
2025-04-01 Martin Uecker <uecker@tugraz.at>
PR c/119173
* doc/invoke.texi (Warning Options): Move to general options.
2025-04-01 Jakub Jelinek <jakub@redhat.com>
PR gcov-profile/119535
* profile.cc (branch_prob): Ignore any edges from bbs ending with
musttail call, rather than only EDGE_FAKE edges from those to EXIT.
2025-04-01 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/119493
* tree-tailcall.cc (tree_optimize_tail_calls_1): Ignore tail recursion
candidates which need accumulators if there is at least one musttail
non-recursive call.
2025-04-01 Jakub Jelinek <jakub@redhat.com>
PR middle-end/119537
* gimplify.cc (find_used_user_labels): New function.
(gimplify_call_expr): Don't remove complex assume expression at -O0
if it defines any user labels.
* gimple-low.cc: Include diagnostic-core.h.
(assume_labels): New variable.
(diagnose_assume_labels): New function.
(lower_function_body): Call it via walk_gimple_seq if assume_labels
is non-NULL, then BITMAP_FREE assume_labels.
(find_assumption_locals_r): Record in assume_labels uids of user
labels defined in assume attribute expressions.
2025-04-01 Thomas Schwinge <tschwinge@baylibre.com>
PR target/119369
* config/gcn/gcn-protos.h (gcn_asm_weaken_decl): Declare.
* config/gcn/gcn.cc (gcn_asm_weaken_decl): New.
* config/gcn/gcn-hsa.h (ASM_WEAKEN_DECL): '#define' to this.
2025-04-01 Richard Biener <rguenther@suse.de>
PR target/119549
* common/config/i386/i386-common.cc (ix86_handle_option):
Assert that both OPT_msse4 and OPT_mno_sse4 are never unset.
* config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p):
Process negated OPT_msse4 as OPT_mno_sse4.
2025-04-01 Tobias Burnus <tburnus@baylibre.com>
PR middle-end/119559
* gimplify.cc (modify_call_for_omp_dispatch): Reorder checks to avoid
asserts and bogus diagnostic.
2025-04-01 Hu, Lin1 <lin1.hu@intel.com>
Hongyu Wang <hongyu.wang@intel.com>
PR target/119473
* config/i386/sse.md
(vaesdec_<mode>): Set attr "isa" as "avx,vaes_avx512vl", "type" as
"sselog1", "mode" as "TI".
(vaesdeclast_<mode>): Ditto.
(vaesenc_<mode>): Ditto.
(vaesenclast_<mode>): Ditto.
2025-04-01 Monk Chiang <monk.chiang@sifive.com>
Kito Cheng <kito.cheng@sifive.com>
* config/riscv/riscv-v.cc: Add restrict for insert LMUL.
* config/riscv/riscv-vector-builtins-types.def:
Use RVV_REQUIRE_ELEN_64 to check LMUL number.
* config/riscv/riscv-vector-switch.def: Likewise.
* config/riscv/vector-iterators.md: Check TARGET_VECTOR_ELEN_64
rather than "TARGET_MIN_VLEN > 32" for all iterator.
2025-04-01 Lulu Cheng <chenglulu@loongson.cn>
* doc/invoke.texi: Corrected the position of '-mtls-dialect=opt'
option.
2025-03-31 Jørgen Kvalsvik <j@lambda.is>
PR gcov-profile/119553
* path-coverage.cc (find_paths): Return path count, don't
write to gcno, and rename to ...
(instrument_prime_paths): ... this.
* profile.cc (branch_prob): Write path counts to gcno.
2025-03-31 Marek Polacek <polacek@redhat.com>
PR c++/116960
PR c++/119303
* diagnostic.cc (diagnostic_context::report_diagnostic): Check for
non-zero m_lock later, after checking diagnostic_enabled.
2025-03-31 Andre Simoes Dias Vieira <andre.simoesdiasvieira@arm.com>
* config/aarch64/aarch64-option-extensions.def (SME): Remove SVE2 as
prerequisite and add in FCMA and F16FML.
* config/aarch64/aarch64.cc (aarch64_override_options_internal):
Diagnose use of SME without SVE2 and implicitly enable SVE2 when
enabling SME after streaming mode diagnosis.
* doc/invoke.texi (sme): Document that this can only be used with the
sve2 extension.
2025-03-31 Richard Biener <rguenther@suse.de>
PR tree-optimization/119532
* tree-tailcall.cc (process_assignment): FAIL for fixed-point
typed functions.
2025-03-31 Tobias Burnus <tburnus@baylibre.com>
PR middle-end/119541
* gimplify.cc (modify_call_for_omp_dispatch): Limit interop claues
processing by the number of append_args arguments.
2025-03-31 Kyrylo Tkachov <ktkachov@nvidia.com>
PR middle-end/119442
* expr.cc (store_constructor): Also allow element modes explicitly
accepted by target vec_duplicate pattern.
2025-03-31 Richard Biener <rguenther@suse.de>
PR target/119010
* config/i386/sse.md (*vmov<mode>_constm1_pternlog_false_dep):
Add mode attribute.
2025-03-31 Richard Biener <rguenther@suse.de>
PR target/119010
* config/i386/zn4zn5.md (znver4_sse_mov_fp_load,
znver5_sse_mov_fp_load): Also match ssemov2.
2025-03-31 Richard Biener <rguenther@suse.de>
PR target/119010
* config/i386/zn4zn5.md (znver4_sse_log_evex_store,
znver5_sse_log_evex_store): New reservations.
2025-03-31 Richard Biener <rguenther@suse.de>
PR target/119010
* config/i386/zn4zn5.md (znver4_sse_icvt): Use sseicvt.
(znver4_sse_icvt_store): Likewise.
(znver5_sse_icvt_store): Likewise.
(znver4_sse_icvt2): New.
2025-03-31 Richard Biener <rguenther@suse.de>
PR target/119010
* config/i386/zn4zn5.md (znver4_sse_div_pd,
znver4_sse_div_pd_load, znver5_sse_div_pd_load): Handle DFmode.
2025-03-31 Richard Biener <rguenther@suse.de>
PR target/119010
* config/i386/zn4zn5.md (znver4_sse_cmp_avx128,
znver5_sse_cmp_avx128): Handle TImode.
(znver4_sse_cmp_avx256, znver5_sse_cmp_avx256): Handle OImode.
(znver4_sse_cmp_avx512, znver5_sse_cmp_avx512): Handle XImode.
2025-03-31 Richard Biener <rguenther@suse.de>
PR target/119010
* config/i386/zn4zn5.md (znver4_sse_test): Drop test of
prefix_extra attribute.
2025-03-31 Richard Biener <rguenther@suse.de>
PR target/119010
* config/i386/zn4zn5.md (znver4_sse_log1): Rename to
znver4_sse_log1_store.
(znver5_sse_log1): Rename to znver5_sse_log1_store.
(znver4_sse_log1): New memory-less variant.
2025-03-30 Sandra Loosemore <sloosemore@baylibre.com>
* doc/extend.texi (New/Delete Builtins): Cleanup up the text and
explicitly list the builtins being documented.
2025-03-30 Sandra Loosemore <sloosemore@baylibre.com>
PR other/42270
* doc/extend.texi (Numeric Builtins): Move Integer Overflow Builtins
section here, as a subsection.
2025-03-30 Sandra Loosemore <sloosemore@baylibre.com>
PR other/42270
* doc/extend.texi (Atomic Memory Access): New section.
(__sync Builtins): Make it a subsection of the above.
(Atomic Memory Access): Likewise.
(x86 specific memory model extensions for transactional memory):
Delete this section, incorporating the text into the discussion
of __atomic builtins.
2025-03-30 Sandra Loosemore <sloosemore@baylibre.com>
PR other/42270
* doc/extend.texi (Built-in Functions): Incorporate some text
formerly in "Other Builtins" into the introduction. Adjust
menu for new sections.
(Library Builtins): New section, split from "Other Builtins".
(Numeric Builtins): Likewise.
(Stack Allocation): Likewise.
(Constructing Calls): Move __builtin_call_with_static_chain here.
(Object Size Checking): Minor copy-editing.
(Other Builtins): Move text to new sections listed above. Delete
duplicate docs for object-size checking builtins.
* doc/invoke.texi (C dialect options): Update @xref for -fno-builtin.
2025-03-30 Sandra Loosemore <sloosemore@baylibre.com>
PR other/42270
* doc/extend.texi (C Extensions): Move menu items for
builtin-related sections to...
(Built-in Functions): New chapter.
* doc/gcc.texi (Introduction): Add menu entry for new chapter.
2025-03-30 Sandra Loosemore <sloosemore@baylibre.com>
PR other/42270
* doc/extend.texi (Attributes): New section.
(Function Attributes): Make it a subsection of the new section.
(Variable Attributes): Likewise.
(Type Attributes): Likewise.
(Label Attributes): Likewise.
(Enumerator Attributes): Likewise.
(Attribute Syntax): Likewise.
2025-03-30 Sandra Loosemore <sloosemore@baylibre.com>
PR other/42270
* doc/extend.texi (Function Attributes): Merge text from "Target
Format Checks" into the main discussion of the format and
format_arg attributes.
(Target Format Checks): Delete section.
2025-03-30 Maciej W. Rozycki <macro@orcam.me.uk>
PR target/117759
* config/alpha/alpha-protos.h
(alpha_expand_unaligned_store_safe_partial): New prototype.
* config/alpha/alpha.cc (alpha_expand_movmisalign)
(alpha_expand_block_move, alpha_expand_block_clear): Handle
TARGET_SAFE_PARTIAL.
(alpha_expand_unaligned_store_safe_partial)
(alpha_expand_unaligned_store_words_safe_partial)
(alpha_expand_clear_safe_partial_nobwx): New functions.
* config/alpha/alpha.md (insvmisaligndi): Handle
TARGET_SAFE_PARTIAL.
* config/alpha/alpha.opt (msafe-partial): New option.
* config/alpha/alpha.opt.urls: Regenerate.
* doc/invoke.texi (Option Summary, DEC Alpha Options): Document
the new option.
2025-03-30 Maciej W. Rozycki <macro@orcam.me.uk>
PR target/117759
* config/alpha/alpha-modes.def (OI): New integer mode.
* config/alpha/alpha-protos.h (alpha_expand_mov_safe_bwa): New
prototype.
* config/alpha/alpha.cc (alpha_expand_mov_safe_bwa): New
function.
(alpha_secondary_reload): Handle TARGET_SAFE_BWA.
* config/alpha/alpha.md (aligned_store_safe_bwa)
(unaligned_store<mode>_safe_bwa, reload_out<mode>_safe_bwa)
(reload_out<mode>_unaligned_safe_bwa): New expanders.
(mov<mode>, movcqi, reload_out<mode>_aligned): Handle
TARGET_SAFE_BWA.
(reload_out<mode>): Guard against TARGET_SAFE_BWA.
* config/alpha/alpha.opt (msafe-bwa): New option.
* config/alpha/alpha.opt.urls: Regenerate.
* doc/invoke.texi (Option Summary, DEC Alpha Options): Document
the new option.
2025-03-30 Maciej W. Rozycki <macro@orcam.me.uk>
* function.h (struct function): Add
`split_basic_blocks_after_reload' member.
* lra.cc (lra): Handle it.
* reload1.cc (reload): Likewise.
2025-03-30 Maciej W. Rozycki <macro@orcam.me.uk>
* config/alpha/alpha-protos.h (alpha_emit_unlikely_jump): New
prototype.
* config/alpha/alpha.cc (emit_unlikely_jump): Rename to...
(alpha_emit_unlikely_jump): ... this. Return the insn emitted.
(alpha_split_atomic_op, alpha_split_compare_and_swap)
(alpha_split_compare_and_swap_12, alpha_split_atomic_exchange)
(alpha_split_atomic_exchange_12): Update call sites accordingly.
2025-03-30 LIU Hao <lh_mouse@126.com>
* config/mingw/winnt.cc (mingw_pe_file_end): Add `.p2align`.
2025-03-29 Iain Sandoe <iain@sandoe.co.uk>
PR cobol/119283
* config.in: Regenerate.
* configure: Regenerate.
* configure.ac: Check for host memrchr.
2025-03-29 Lulu Cheng <chenglulu@loongson.cn>
* doc/invoke.texi: Modify the description of '-mld-seq-sa'.
2025-03-29 Lulu Cheng <chenglulu@loongson.cn>
* config/loongarch/loongarch-def.cc
(la464_align): Add settings for labels.
(la664_align): Likewise.
* config/loongarch/loongarch-opts.cc
(loongarch_target_option_override): Likewise.
* config/loongarch/loongarch-tune.h
(struct loongarch_align): Implement the function `label_`.
2025-03-28 Jakub Jelinek <jakub@redhat.com>
* common.opt.urls: Regenerate.
2025-03-28 Jakub Jelinek <jakub@redhat.com>
* Makefile.in (gcc.srcextra): Use sed to turn .../gcc/gengtype-lex.l
in #line directives into just gengtype-lex.l.
2025-03-28 Andrew MacLeod <amacleod@redhat.com>
* range-op.cc (operator_mult::op1_range): If the LHS does not
contain zero, return non-zero.
2025-03-28 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/119483
* tree-tailcall.cc (find_tail_calls): Handle noreturn musttail
calls.
(eliminate_tail_call): Likewise.
(tree_optimize_tail_calls_1): If cfun->has_musttail and
diag_musttail, handle also basic blocks with no successors
with noreturn musttail calls.
* calls.cc (can_implement_as_sibling_call_p): Allow ECF_NORETURN
calls if they are musttail calls.
2025-03-28 Jakub Jelinek <jakub@redhat.com>
PR ipa/119484
* ipa-sra.cc (isra_analyze_call): Don't set m_return_ignored if
gimple_call_must_tail_p even if it doesn't have lhs.
2025-03-28 Richard Biener <rguenther@suse.de>
* fold-const.h (native_encode_real): Export.
* fold-const.cc (native_encode_real): Change API to take
mode and REAL_VALUE_TYPE.
(native_encode_expr): Adjust.
2025-03-27 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.cc (ix86_redzone_clobber): Use integer, not rtx
as the third argument of plus_constant.
2025-03-27 Richard Biener <rguenther@suse.de>
PR target/119010
* config/i386/zn4zn5.md (znver4_insn_both, znver5_insn_both):
New reservation for ALU ops with load and store.
2025-03-27 Richard Biener <rguenther@suse.de>
PR target/119010
* config/i386/zn4zn5.md (znver4_sse_add, znver4_sse_add_load,
znver5_sse_add_load, znver4_sse_add1, znver4_sse_add1_load,
znver5_sse_add1_load, znver4_sse_mul, znver4_sse_mul_load,
znver5_sse_mul_load, znver4_sse_cvt, znver4_sse_cvt_load,
znver5_sse_cvt_load, znver4_sse_shuf, znver5_sse_shuf,
znver4_sse_shuf_load, znver5_sse_shuf_load,
znver4_sse_cmp_avx128, znver5_sse_cmp_avx128,
znver4_sse_cmp_avx128_load, znver5_sse_cmp_avx128_load):
Also handle DFmode.
(znver4_sse_muladd_load, znver5_sse_muladd_load): Use
ssemuladd type.
2025-03-27 Tobias Burnus <tburnus@baylibre.com>
* gimplify.cc (modify_call_for_omp_dispatch): Remove sorry.
2025-03-27 Richard Earnshaw <rearnsha@arm.com>
* config/arm/neon.md (<fmaxmin><mode>3): Move pattern from here...
* config/arm/vec-common.md (<fmaxmin><mode>3): ... to here. Convert
to define_expand and disable the pattern when denormal values might
get truncated to zero. Iterate on VF to add V4HF and V8HF variants.
2025-03-27 Hu, Lin1 <lin1.hu@intel.com>
PR target/119425
* config/i386/sse.md:
(vec_set<mode>_0): Set the alternative with constraint "jm"'s
attribute "addr" to "gpr16".
(<mask_codefor>avx512dq_shuf_<shuffletype>64x2_1<mask_name>):
Ditto.
(avx512vl_shuf_<shuffletype>32x4_1<mask_name>): Ditto.
(avx2_pblendd<mode>): Ditto.
(aesenc): Ditto.
(aesenclast): Ditto.
(aesdec): Ditto.
(aesdeclast): Ditto.
(vaesdec_<mode>): Ditto.
(vaesdeclast_<mode>): Ditto.
(vaesenc_<mode>):: Ditto.
(vaesenclast_<mode>):: Ditto.
(aes<aesklvariant>u8): Ditto.
(*aes<aeswideklvariant>u8): Ditto.
2025-03-27 Lulu Cheng <chenglulu@loongson.cn>
PR target/119408
* config/loongarch/loongarch.cc
(loongarch_c_mode_for_suffix): New.
(TARGET_C_MODE_FOR_SUFFIX): Define.
2025-03-26 Jørgen Kvalsvik <j@lambda.is>
* builtins.cc (expand_builtin_fork_or_exec): Call
coverage_instrumentation_p.
* ipa-inline.cc (can_early_inline_edge_p): Likewise.
* passes.cc (finish_optimization_passes): Likewise.
* profile.cc (coverage_instrumentation_p): New function.
* profile.h (coverage_instrumentation_p): New declaration.
* tree-profile.cc (tree_profiling): Call
coverage_instrumentation_p.
(pass_ipa_tree_profile::gate): Likewise.
* value-prof.h (coverage_instrumentation_p): New declaration.
2025-03-26 Jørgen Kvalsvik <j@lambda.is>
* Makefile.in (OBJS): Add prime-paths.o, path-coverage.o.
(GTFILES): Add prime-paths.cc, path-coverage.cc
(GCOV_OBJS): Add graphds.o, prime-paths.o, bitmap.o
* builtins.cc (expand_builtin_fork_or_exec): Check
path_coverage_flag.
* collect2.cc (main): Add -fno-path-coverage to OBSTACK.
* common.opt: Add new options -fpath-coverage,
-fpath-coverage-limit, -Wcoverage-too-many-paths
* doc/gcov.texi: Add --prime-paths, --prime-paths-lines,
--prime-paths-source documentation.
* doc/invoke.texi: Add -fpath-coverage, -fpath-coverage-limit,
-Wcoverage-too-many-paths documentation.
* gcc.cc: Link gcov on -fpath-coverage.
* gcov-counter.def (GCOV_COUNTER_PATHS): New.
* gcov-io.h (GCOV_TAG_PATHS): New.
(GCOV_TAG_PATHS_LENGTH): New.
(GCOV_TAG_PATHS_NUM): New.
* gcov.cc (class path_info): New.
(struct coverage_info): Add paths, paths_covered.
(find_prime_paths): New.
(add_path_counts): New.
(find_arc): New.
(print_usage): Add -e, --prime-paths, --prime-paths-lines,
--prime-paths-source.
(process_args): Likewise.
(json_set_prime_path_coverage): New.
(output_json_intermediate_file): Call
json_set_prime_path_coverage.
(process_all_functions): Call find_prime_paths.
(generate_results): Call add_path_counts.
(read_graph_file): Read path counters.
(read_count_file): Likewise.
(function_summary): Print path counts.
(file_summary): Likewise.
(print_source_line): New.
(print_prime_path_lines): New.
(print_inlined_separator): New.
(print_prime_path_source): New.
(output_path_coverage): New.
(output_lines): Print path coverage.
* ipa-inline.cc (can_early_inline_edge_p): Check
path_coverage_flag.
* passes.cc (finish_optimization_passes): Likewise.
* profile.cc (branch_prob): Likewise.
* selftest-run-tests.cc (selftest::run_tests): Run path coverage
tests.
* selftest.h (path_coverage_cc_tests): New declaration.
* tree-profile.cc (tree_profiling): Check path_coverage_flag.
(pass_ipa_tree_profile::gate): Likewise.
* path-coverage.cc: New file.
* prime-paths.cc: New file.
2025-03-26 Jørgen Kvalsvik <j@lambda.is>
* gcov.cc (generate_results): Count branches, conditions.
(function_summary): Output branch, calls, condition count.
2025-03-26 Thomas Schwinge <thomas@codesourcery.com>
PR driver/101544
* gcc.cc (driver_handle_option): Forward host '-lstdc++' to
offloading compilation.
* config/gcn/mkoffload.cc (main): Adjust.
* config/nvptx/mkoffload.cc (main): Likewise.
2025-03-26 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/119417
* tree-ssa-math-opts.cc (convert_mult_to_widen): Before changing
typeN because actual_precision/from_unsignedN differs cast rhsN
to typeN if it has a different type.
(convert_plusminus_to_widen): Before changing
typeN because actual_precision/from_unsignedN differs cast mult_rhsN
to typeN if it has a different type.
2025-03-26 Jakub Jelinek <jakub@redhat.com>
Andi Kleen <ak@gcc.gnu.org>
PR gcov-profile/118442
* profile.cc (branch_prob): Ignore EDGE_FAKE edges from musttail calls
to EXIT.
2025-03-26 Jakub Jelinek <jakub@redhat.com>
PR target/119450
* config/i386/i386.md (narrow test peephole2): Test for
offsettable_memref_p in condition.
2025-03-26 Richard Biener <rguenther@suse.de>
PR target/119010
* config/i386/zn4zn5.md (znver4_sse_mov_fp, znver4_sse_mov_fp_load,
znver5_sse_mov_fp_load, znver4_sse_mov_fp_store,
znver5_sse_mov_fp_store): Also match V1SF and DF.
2025-03-26 Richard Biener <rguenther@suse.de>
PR target/119010
* config/i386/zn4zn5.md (znver4_imov_double_store,
znver5_imov_double_store, znver4_imov_store, znver5_imov_store):
New reservations for integer stores.
2025-03-26 Richard Biener <rguenther@suse.de>
PR middle-end/118795
* match.pd (vec_perm <vec_perm <a, b>> -> vec_perm <a, b>):
Use the appropriate check to see whether the original
outer permute was supported.
2025-03-26 Hu, Lin1 <lin1.hu@intel.com>
* config/i386/avx10_2-512convertintrin.h (_mm512_mask_cvtx2ps_ph): Formatting fixes
(_mm512_mask_cvtx_round2ps_ph): Ditto
(_mm512_maskz_cvtx_round2ps_ph): Ditto
(_mm512_cvtbiassph_bf8): Rename to _mm512_cvts_biasph_bf8.
(_mm512_mask_cvtbiassph_bf8): Rename to _mm512_mask_cvts_biasph_bf8.
(_mm512_maskz_cvtbiassph_bf8): Rename to _mm512_maskz_cvts_biasph_bf8.
(_mm512_cvtbiassph_hf8): Rename to _mm512_cvts_biasph_hf8.
(_mm512_mask_cvtbiassph_hf8): Rename to _mm512_mask_cvts_biasph_hf8.
(_mm512_maskz_cvtbiassph_hf8): Rename to _mm512_maskz_cvts_biasph_hf8.
(_mm512_cvts2ph_bf8): Rename to _mm512_cvts_2ph_bf8.
(_mm512_mask_cvts2ph_bf8): Rename to _mm512_mask_cvts_2ph_bf8.
(_mm512_maskz_cvts2ph_bf8): Rename to _mm512_maskz_cvts_2ph_bf8.
(_mm512_cvts2ph_hf8): Rename to _mm512_cvts_2ph_hf8.
(_mm512_mask_cvts2ph_hf8): Rename to _mm512_mask_cvts_2ph_hf8.
(_mm512_maskz_cvts2ph_hf8): Rename to _mm512_maskz_cvts_2ph_hf8.
(_mm512_cvtsph_bf8): Rename to _mm512_cvts_ph_bf8.
(_mm512_mask_cvtsph_bf8): Rename to _mm512_mask_cvts_ph_bf8.
(_mm512_maskz_cvtsph_bf8): Rename to _mm512_maskz_cvts_ph_bf8.
(_mm512_cvtsph_hf8): Rename to _mm512_cvts_ph_hf8.
(_mm512_mask_cvtsph_hf8): Rename to _mm512_mask_cvts_ph_hf8.
(_mm512_maskz_cvtsph_hf8): Rename to _mm512_maskz_cvts_ph_hf8.
* config/i386/avx10_2convertintrin.h
(_mm_cvtbiassph_bf8): Rename to _mm_cvts_biasph_bf8.
(_mm_mask_cvtbiassph_bf8): Rename to _mm_mask_cvts_biasph_bf8.
(_mm_maskz_cvtbiassph_bf8): Rename to _mm_maskz_cvts_biasph_bf8.
(_mm256_cvtbiassph_bf8): Rename to _mm256_cvts_biasph_bf8.
(_mm256_mask_cvtbiassph_bf8): Rename to _mm256_mask_cvts_biasph_bf8.
(_mm256_maskz_cvtbiassph_bf8): Rename to _mm256_maskz_cvts_biasph_bf8.
(_mm_cvtbiassph_hf8): Rename to _mm_cvts_biasph_hf8.
(_mm_mask_cvtbiassph_hf8): Rename to _mm_mask_cvts_biasph_hf8.
(_mm_maskz_cvtbiassph_hf8): Rename to _mm_maskz_cvts_biasph_hf8.
(_mm256_cvtbiassph_hf8): Rename to _mm256_cvts_biasph_hf8.
(_mm256_mask_cvtbiassph_hf8): Rename to _mm256_mask_cvts_biasph_hf8.
(_mm256_maskz_cvtbiassph_hf8): Rename to _mm256_maskz_cvts_biasph_hf8.
(_mm_cvts2ph_bf8): Rename to _mm_cvts_2ph_bf8.
(_mm_mask_cvts2ph_bf8): Rename to _mm_mask_cvts_2ph_bf8.
(_mm_maskz_cvts2ph_bf8): Rename to _mm_maskz_cvts_2ph_bf8.
(_mm256_cvts2ph_bf8): Rename to _mm256_cvts_2ph_bf8.
(_mm256_mask_cvts2ph_bf8): Rename to _mm256_mask_cvts_2ph_bf8.
(_mm256_maskz_cvts2ph_bf8): Rename to _mm256_maskz_cvts_2ph_bf8.
(_mm_cvts2ph_hf8): Rename to _mm_cvts_2ph_hf8.
(_mm_mask_cvts2ph_hf8): Rename to _mm_mask_cvts_2ph_hf8.
(_mm_maskz_cvts2ph_hf8): Rename to _mm_maskz_cvts_2ph_hf8.
(_mm256_cvts2ph_hf8): Rename to _mm256_cvts_2ph_hf8.
(_mm256_mask_cvts2ph_hf8): Rename to _mm256_mask_cvts_2ph_hf8.
(_mm256_maskz_cvts2ph_hf8): Rename to _mm256_maskz_cvts_2ph_hf8.
(_mm_cvtsph_bf8): Rename to _mm_cvts_ph_bf8.
(_mm_mask_cvtsph_bf8): Rename to _mm_mask_cvts_ph_bf8.
(_mm_maskz_cvtsph_bf8): Rename to _mm_maskz_cvts_ph_bf8.
(_mm256_cvtsph_bf8): Rename to _mm256_cvts_ph_bf8.
(_mm256_mask_cvtsph_bf8): Rename to _mm256_mask_cvts_ph_bf8.
(_mm256_maskz_cvtsph_bf8): Rename to _mm256_maskz_cvts_ph_bf8.
(_mm_cvtsph_hf8): Rename to _mm_cvts_ph_hf8.
(_mm_mask_cvtsph_hf8): Rename to _mm_mask_cvts_ph_hf8.
(_mm_maskz_cvtsph_hf8): Rename to _mm_maskz_cvts_ph_hf8.
(_mm256_cvtsph_hf8): Rename to _mm256_cvts_ph_hf8.
(_mm256_mask_cvtsph_hf8): Rename to _mm256_mask_cvts_ph_hf8.
(_mm256_maskz_cvtsph_hf8): Rename to _mm256_maskz_cvts_ph_hf8.
2025-03-25 Iain Sandoe <iain@sandoe.co.uk>
* gcov.cc (get_gcov_intermediate_filename): Use lbasename().
2025-03-25 Iain Sandoe <iain@sandoe.co.uk>
PR other/119250
* config.in: Regenerate.
* configure: Regenerate.
* configure.ac: Match the configure test in libiberty when checking
the basename decl.
2025-03-25 Sandra Loosemore <sloosemore@baylibre.com>
Tobias Burnus <tburnus@baylibre.com>
* gimplify.cc (modify_call_for_omp_dispatch): Adjust arguments.
Remove the "sorry" for the case where new interop objects must be
constructed, and add code to make it work instead.
(expand_variant_call_expr): Adjust arguments and call to
modify_call_for_omp_dispatch.
(gimplify_variant_call_expr): Simplify logic for calling
expand_variant_call_expr.
2025-03-25 Jakub Jelinek <jakub@redhat.com>
PR target/96226
PR target/119428
* config/i386/i386.md (splitter after *<rotate_insn><mode>3_mask,
splitter after *<rotate_insn><mode>3_mask_1): Revert 2020-12-05
changes.
2025-03-25 Vineet Gupta <vineetg@rivosinc.com>
PR target/119224
* config/riscv/autovec.md: Disable abd splitter.
2025-03-25 Tobias Burnus <tburnus@baylibre.com>
PR middle-end/119325
* doc/install.texi (gcn): Change ROCm > 6.3.2 to >6.3.3 for generic
support; mention Newlib commit that fixes a SIMD math issue.
2025-03-25 Tobias Burnus <tburnus@baylibre.com>
PR middle-end/118627
* omp-general.cc (omp_parse_access_method): Change to return void.
(omp_parse_access_methods): Return void; remove 'if' around a
function call.
(omp_parse_expr): Remove 'if' around a function call.
2025-03-25 Richard Earnshaw <rearnsha@arm.com>
* config/arm/arm.md (<US>mull): Add alternatives that allow Rs
to be tied to either Rdlo or Rdhi.
2025-03-25 Richard Earnshaw <rearnsha@arm.com>
PR middle-end/117811
* optabs.cc (expand_binop_directly): Remove LAST as an argument,
instead record the last insn on entry. Only delete insns if
we need to restart and restart by calling ourself, not expand_binop.
(expand_binop): Update callers to expand_binop_directly. If it
fails to expand the operation, delete back to LAST.
2025-03-25 Jakub Jelinek <jakub@redhat.com>
PR ipa/119376
* tree-tailcall.cc (suitable_for_tail_opt_p): Add DIAG_MUSTTAIL
argument, propagate it down to maybe_error_musttail.
(suitable_for_tail_call_opt_p): Likewise.
(maybe_error_musttail): Add DIAG_MUSTTAIL argument. Don't emit error
for gimple_call_must_tail_p calls if it is false.
(find_tail_calls): Add DIAG_MUSTTAIL argument, propagate it down to
maybe_error_musttail, suitable_for_tail_opt_p,
suitable_for_tail_call_opt_p and find_tail_calls calls.
(tree_optimize_tail_calls_1): Add DIAG_MUSTTAIL argument, propagate
it down to find_tail_calls and if set, clear cfun->has_musttail flag
at the end. Rename OPT_MUSTCALL argument to OPT_MUSTTAIL.
(execute_tail_calls): Pass true to DIAG_MUSTTAIL
tree_optimize_tail_calls_1 argument.
(pass_tail_recursion::execute): Pass false to DIAG_MUSTTAIL
tree_optimize_tail_calls_1 argument.
(pass_musttail::gate): Don't test flag_optimize_sibling_calls.
(pass_musttail::execute): Pass true to DIAG_MUSTTAIL
tree_optimize_tail_calls_1 argument.
2025-03-24 Andrew Pinski <quic_apinski@quicinc.com>
PR tree-optimization/118616
* tree-vect-generic.cc (expand_vector_conversion): Add
an assert that converts vect is non empty if
supportable_indirect_convert_operation returns true.
2025-03-24 Thomas Schwinge <tschwinge@baylibre.com>
PR target/101544
* config/nvptx/nvptx.cc (nvptx_asm_output_def_from_decls)
[ACCEL_COMPILER]: Special-case certain host-setup symbol aliases.
* varasm.cc (do_assemble_alias) [ACCEL_COMPILER]: Adjust.
2025-03-24 Thomas Schwinge <tschwinge@baylibre.com>
* config/nvptx/nvptx.cc (default_ptx_version_option): Default at
least to '-mptx=6.3'.
* doc/invoke.texi (Nvidia PTX Options): Update '-mptx=[...]'.
2025-03-24 Haochen Jiang <haochen.jiang@intel.com>
* common/config/i386/cpuinfo.h
(get_available_features): Change to FEATURE_AVX10_1.
* common/config/i386/i386-common.cc
(OPTION_MASK_ISA2_AVX10_1_512_SET): Renamed to ...
(OPTION_MASK_ISA2_AVX10_1_SET): ... this.
(OPTION_MASK_ISA2_AVX10_2_SET): Use renamed macro.
(OPTION_MASK_ISA2_AVX10_1_UNSET): Ditto.
(ix86_handle_option): Ditto.
(processor_alias_table): Use P_PROC_AVX10_1.
* common/config/i386/i386-cpuinfo.h
(enum feature_priority): Rename from AVX10_1_512 to AVX10_1.
(enum processor_features): Ditto.
* common/config/i386/i386-isas.h: Add avx10.1.
* config/i386/driver-i386.cc
(host_detect_local_cpu): Use renamed enum.
* config/i386/i386-c.cc
(ix86_target_macros_internal): Rename to avx10.1.
* config/i386/i386-isa.def (AVX10_1_512): Rename to ...
(AVX10_1): ... this.
* config/i386/i386-options.cc (isa2_opts): Rename to avx10.1.
(ix86_valid_target_attribute_inner_p): Add avx10.1.
(ix86_option_override_internal): Rename to AVX10_1.
Revise warnings to mention behavior change for option
combination in GCC 16.
* config/i386/i386.h (PTA_DIAMONDRAPIDS): Use AVX10_1.
* config/i386/i386.opt: Add avx10.1.
Add deprecate warnings for mevex512 and mavx10.1-256/512.
* config/i386/i386.opt.urls: Add avx10.1.
* doc/extend.texi: Ditto.
* doc/sourcebuild.texi: Ditto.
2025-03-24 Haochen Jiang <haochen.jiang@intel.com>
* common/config/i386/cpuinfo.h
(get_available_features): Revise the logic AVX10 version.
* common/config/i386/i386-common.cc
(OPTION_MASK_ISA2_AVX10_2_256_SET): Removed.
(OPTION_MASK_ISA2_AVX10_2_512_SET): Ditto.
(OPTION_MASK_ISA2_AVX10_2_SET): New.
(OPTION_MASK_ISA2_AMX_AVX512_SET): Use AVX10.2 macro.
(OPTION_MASK_ISA2_AVX10_2_UNSET): Ditto.
(ix86_handle_option): Remove avx10.2-256 part. Adjust avx10.2.
* common/config/i386/i386-cpuinfo.h
(enum processor_features): Remove FEATURE_AVX10_2_256 and skip
the value for it. Change the name from FEATURE_AVX10_2_512 to
FEATURE_AVX10_2.
* common/config/i386/i386-isas.h: Remove avx10.2-256/512.
* config/i386/avx10_2-512bf16intrin.h: Use avx10.2 instead of
avx10.2-256/512.
* config/i386/avx10_2-512convertintrin.h: Ditto.
* config/i386/avx10_2-512mediaintrin.h: Ditto.
* config/i386/avx10_2-512minmaxintrin.h: Ditto.
* config/i386/avx10_2-512satcvtintrin.h: Ditto.
* config/i386/avx10_2bf16intrin.h: Ditto.
* config/i386/avx10_2convertintrin.h: Ditto.
* config/i386/avx10_2mediaintrin.h: Ditto.
* config/i386/avx10_2minmaxintrin.h: Ditto.
* config/i386/avx10_2satcvtintrin.h: Ditto.
* config/i386/movrsintrin.h: Ditto.
* config/i386/sm4intrin.h: Ditto.
* config/i386/cpuid.h (bit_AVX10_256): Removed.
(bit_AVX10_512): Ditto.
* config/i386/driver-i386.cc (host_detect_local_cpu): Adjust
Diamond Rapids and -march=native condition.
* config/i386/i386-builtin.def (BDESC): Use AVX10.2 macro
instead of AVX10.2-256/512.
* config/i386/i386-c.cc (ix86_target_macros_internal): Ditto.
* config/i386/i386-expand.cc
(ix86_expand_branch): Use TARGET_AVX10_2 instead of specifying
vector size.
(ix86_prepare_fp_compare_args): Ditto.
(ix86_expand_fp_compare): Ditto.
(ix86_ssecom_setcc): Ditto.
(ix86_expand_sse_comi): Ditto.
(ix86_expand_sse_comi_round): Ditto.
(ix86_check_builtin_isa_match): Ditto.
* config/i386/i386.cc (ix86_fp_compare_code_to_integer): Ditto.
(ix86_get_mask_mode): Ditto.
* config/i386/i386.h (SSE_FLOAT_MODE_SSEMATH_OR_HFBF_P): Ditto.
* config/i386/i386.md: Ditto.
* config/i386/mmx.md: Ditto.
* config/i386/sse.md: Ditto.
* config/i386/predicates.md: Ditto.
* config/i386/i386-isa.def (AVX10_2_256): Removed.
(AVX10_2_512): Removed.
(AVX10_2): New.
* config/i386/i386-options.cc
(isa2_opts): Remove avx10.2-256/512.
(ix86_valid_target_attribute_inner_p): Ditto.
(PTA_DIAMONDRAPIDS): Use PTA_AVX10_2.
* config/i386/i386.opt: Remove avx10.2-256/512.
* config/i386/i386.opt.urls: Ditto.
* doc/extend.texi: Ditto.
* doc/invoke.texi: Ditto.
* doc/sourcebuild.texi: Ditto.
2025-03-24 Haochen Jiang <haochen.jiang@intel.com>
Revert:
2024-08-19 Hu, Lin1 <lin1.hu@intel.com>
* config.gcc: Add avx10_2roundingintrin.h.
* config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle
V4DF_FTYPE_V4DF_V4DF_V4DF_UQI_INT, V8SF_FTYPE_V8SF_V8SF_V8SF_UQI_INT,
V16HF_FTYPE_V16HF_V16HF_V16HF_UHI_INT, UQI_FTYPE_V4DF_V4DF_INT_UQI_INT,
UHI_FTYPE_V16HF_V16HF_INT_UHI_INT, UQI_FTYPE_V8SF_V8SF_INT_UQI_INT.
* config/i386/immintrin.h: Include avx10_2roundingintrin.h.
* config/i386/sse.md: Change subst_attr name due to renaming.
* config/i386/subst.md:
(<round_mode512bit_condition>): Add condition check for avx10.2
rounding control 256bit intrins and renamed to ...
(<round_mode_condition>): ...this.
(round_saeonly_mode512bit_condition): Add condition check for
avx10.2 rounding control 256 bit intris and renamed to ...
(round_saeonly_mode_condition): ...this.
* config/i386/avx10_2roundingintrin.h: New file.
2025-03-24 Haochen Jiang <haochen.jiang@intel.com>
Revert:
2024-08-19 Hu, Lin1 <lin1.hu@intel.com>
* config/i386/avx10_2roundingintrin.h: Add new intrins.
* config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle
V8SF_FTYPE_V8SI_V8SF_UQI_INT, V4SF_FTYPE_V4DF_V4SF_UQI_INT,
V8HF_FTYPE_V8SI_V8HF_UQI_INT, V8HF_FTYPE_V4DF_V8HF_UQI_INT.
* config/i386/sse.md:
(avx512fp16_vcvt<floatsuffix><sseintconvert>2ph_<mode><mask_name><round_name>):
Add condition check.
(avx512fp16_vcvtpd2ph_v4df_mask_round): New expand.
(*avx512fp16_vcvt<castmode>2ph_<mode>_mask): Change name to
avx512fp16_vcvt<castmode>2ph_<mode>_mask<round_name>_1
and extend pattern to generate 256bit insns.
(avx_cvtpd2ps256<mask_name>): Change name to
avx_cvtpd2ps256<mask_name><round_name> and extend pattern to
generate 256bit insns.
* config/i386/subst.md (round_applied): New condition.
(round_suff): New iterator.
(round_mode_condition): Add V32HI check for 512bit.
(round_saeonly_mode_condition): Ditto.
2025-03-24 Haochen Jiang <haochen.jiang@intel.com>
Revert:
2024-08-19 Hu, Lin1 <lin1.hu@intel.com>
* config/i386/avx10_2roundingintrin.h: Add new intrins.
* config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle
V4DI_FTYPE_V4DF_V4DI_UQI_INT, V4SI_FTYPE_V4DF_V4SI_UQI_INT.
* config/i386/sse.md:
(avx_cvtpd2dq256<mask_name>): Change name to
avx_cvtpd2dq256<mask_name><round_name> and extend pattern to
generate 256bit insns.
(fixuns_notrunc<mode><si2dfmodelower>2<mask_name><round_name>):
Add round_mode_condition.
* config/i386/subst.md (round_pd2udqsuff): New iterator.
2025-03-24 Haochen Jiang <haochen.jiang@intel.com>
Revert:
2024-08-19 Hu, Lin1 <lin1.hu@intel.com>
* config/i386/avx10_2roundingintrin.h: New intrins.
* config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle
V8SF_FTYPE_V8HF_V8SF_UQI_INT, V8SI_FTYPE_V8HF_V8SI_UQI_INT,
V4DF_FTYPE_V8HF_V4DF_UQI_INT, V4DI_FTYPE_V8HF_V4DI_UQI_INT.
* config/i386/sse.md:
(avx512fp16_float_extend_ph<mode>2<mask_name><round_saeonly_name>):
Add condition check.
(avx512fp16_vcvtph2<sseintconvertsignprefix><sseintconvert>_<mode>
<mask_name><round_name>):
Ditto.
(avx512fp16_float_extend_ph<mode>2<mask_name>): Extend round saeonly.
(vcvtph2ps256<mask_name>): Ditto.
* config/i386/subst.md
(round_saeonly_applied): New condition.
2025-03-24 Haochen Jiang <haochen.jiang@intel.com>
Revert:
2024-08-19 Hu, Lin1 <lin1.hu@intel.com>
* config/i386/avx10_2roundingintrin.h: New intrins.
* config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle
V16HI_FTYPE_V16HF_V16HI_UHI_INT, V4DF_FTYPE_V4SF_V4DF_UQI_INT
V8HF_FTYPE_V8SF_V8HF_UQI_INT.
* config/i386/sse.md
(avx512fp16_vcvt<castmode>2ph_<mode><mask_name><round_name>):
Add round condition check.
* config/i386/subst.md (round_mode_condition): Add V16HI check for
256bit.
2025-03-24 Haochen Jiang <haochen.jiang@intel.com>
Revert:
2024-08-19 Hu, Lin1 <lin1.hu@intel.com>
* config/i386/avx10_2roundingintrin.h: New intrins.
* config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle
V8SI_FTYPE_V8SF_V8SI_UQI_INT, V4DI_FTYPE_V4SF_V4DI_UQI_INT.
* config/i386/sse.md
(<sse2_avx_avx512f>_fix_notrunc<sf2simodelower><mode><mask_name>):
Extend to round.
(<mask_codefor><avx512>_fixuns_notrunc<sf2simodelower><mode><mask_name><round_name>):
Add round condition check.
* config/i386/subst.md (round_constraint4): New.
2025-03-24 Haochen Jiang <haochen.jiang@intel.com>
Revert:
2024-08-19 Hu, Lin1 <lin1.hu@intel.com>
* config/i386/avx10_2roundingintrin.h: New intrins.
* config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle
V4DF_FTYPE_V4DI_V4DF_UQI_INT, V4SF_FTYPE_V4DI_V4SF_UQI_INT,
V8HF_FTYPE_V4DI_V8HF_UQI_INT.
* config/i386/sse.md:
(avx512fp16_vcvt<floatsuffix>qq2ph_v4di_mask_round): New expand.
(*avx512fp16_vcvt<floatsuffix><sseintconvert>2ph_<mode>_mask):
Extend round control and add "_1" suffix.
(float<floatunssuffix><sseintvecmodelower><mode>2<mask_name><round_name>):
Add condition check.
(float<floatunssuffix><sselongvecmodelower><mode>2<mask_name><round_name>):
Ditto.
(float<floatunssuffix><mode><ssePSmode2lower>2<mask_name><round_name>):
Limit suffix output.
(unspec_fix_truncv4dfv4si2<mask_name>): Extend round control.
(unspec_fixuns_truncv4dfv4si2<mask_name>): Ditto.
* config/i386/subst.md (round_qq2pssuff): New iterator.
(round_saeonly_suff): Ditto.
2025-03-24 Haochen Jiang <haochen.jiang@intel.com>
Revert:
2024-08-19 Hu, Lin1 <lin1.hu@intel.com>
* config/i386/avx10_2roundingintrin.h: New intrins.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/sse.md (avx512fp16_fix<fixunssuffix>_trunc<mode>2<mask_name>):
Extend round control for 256bit.
(unspec_avx512fp16_fix<vcvtt_uns_suffix>_trunc<mode>2<mask_name>):
Ditto.
(avx512fp16_fix<fixunssuffix>_trunc<mode>2<mask_name><round_saeonly_name>):
Add condition check.
* config/i386/subst.md
(round_saeonly_mode_condition): Add V16HI check for 256bit.
2025-03-24 Haochen Jiang <haochen.jiang@intel.com>
Revert:
2024-08-19 Hu, Lin1 <lin1.hu@intel.com>
* config/i386/avx10_2roundingintrin.h: New intrins.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/sse.md
(unspec_fix_truncv8sfv8si2<mask_name>): Extend rounding control.
(<mask_codefor>fixuns_trunc<mode><sseintvecmodelower>2<mask_name>):
Ditto.
(<mask_codefor>floatuns<sseintvecmodelower><mode>2<mask_name><round_name>):
Add condition check.
(fix<fixunssuffix>_trunc<mode><sselongvecmodelower>2<mask_name><round_saeonly_name>):
Remove round_saeonly_name.
2025-03-24 Haochen Jiang <haochen.jiang@intel.com>
Revert:
2024-08-19 Hu, Lin1 <lin1.hu@intel.com>
* config/i386/avx10_2roundingintrin.h: New intrins.
* config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle
V16HF_FTYPE_V16HI_V16HF_UHI_INT.
2025-03-24 Haochen Jiang <haochen.jiang@intel.com>
Revert:
2024-08-19 Hu, Lin1 <lin1.hu@intel.com>
* config/i386/avx10_2roundingintrin.h: New intrins.
* config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle
V16HF_FTYPE_V16HF_V16HF_INT, V16HF_FTYPE_V16HF_V16HF_V16HF_INT,
V16HF_FTYPE_V16HF_V16HF_V16HF_UQI_INT,
V4DF_FTYPE_V4DF_V4DF_V4DI_INT_UQI_INT,
V8SF_FTYPE_V8SF_V8SF_V8SI_INT_UQI_INT.
* config/i386/sse.md:
(<avx512>_fixupimm<mode><sd_maskz_name><round_saeonly_name>):
Add condition check.
(<avx512>_fixupimm<mode>_mask<round_saeonly_name>): Ditto.
2025-03-24 Haochen Jiang <haochen.jiang@intel.com>
Revert:
2024-08-19 Hu, Lin1 <lin1.hu@intel.com>
* config/i386/avx10_2roundingintrin.h: New intrins.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/sse.md:
(<avx512>_fmadd_<mode>_mask3<round_name>): Add condition check.
2025-03-24 Haochen Jiang <haochen.jiang@intel.com>
Revert:
2024-08-19 Hu, Lin1 <lin1.hu@intel.com>
* config/i386/avx10_2roundingintrin.h: New intrins.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/sse.md:
(<avx512>_fmaddsub_<mode>_mask<round_name>): Add condition check.
(<avx512>_fmaddsub_<mode>_mask3<round_name>): Ditto.
2025-03-24 Haochen Jiang <haochen.jiang@intel.com>
Revert:
2024-08-19 Hu, Lin1 <lin1.hu@intel.com>
* config/i386/avx10_2roundingintrin.h: New intrins.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/sse.md:
(<avx512>_fmsub_<mode>_mask<round_name>): Add condition check.
2025-03-24 Haochen Jiang <haochen.jiang@intel.com>
Revert:
2024-08-19 Hu, Lin1 <lin1.hu@intel.com>
* config/i386/avx10_2roundingintrin.h: New intrins.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
2025-03-24 Haochen Jiang <haochen.jiang@intel.com>
Revert:
2024-08-19 Hu, Lin1 <lin1.hu@intel.com>
* config/i386/avx10_2roundingintrin.h: New intrins.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/sse.md:
(<avx512>_fnmsub_<mode>_mask3<round_name>): Add condition check.
2025-03-24 Haochen Jiang <haochen.jiang@intel.com>
Revert:
2024-08-19 Hu, Lin1 <lin1.hu@intel.com>
* config/i386/avx10_2roundingintrin.h: New intrins.
* config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/i386-expand.cc (ix86_expand_round_builtin): Handle
V8SF_FTYPE_V8SF_V8SF_UQI_INT, V4DF_FTYPE_V4DF_V4DF_UQI_INT,
V16HF_FTYPE_V16HF_V16HF_UHI_INT, V16HF_FTYPE_V16HF_INT_V16HF_UHI_INT,
V4DF_FTYPE_V4DF_INT_V4DF_UQI_INT, V8SF_FTYPE_V8SF_INT_V8SF_UQI_INT.
* config/i386/sse.md:
(<avx512>_getexp<mode><mask_name><round_saeonly_name>):
Add condition check.
(<avx512>_getmant<mode><mask_name><round_saeonly_name>):
Ditto.
2025-03-24 Haochen Jiang <haochen.jiang@intel.com>
Revert:
2024-08-19 Hu, Lin1 <lin1.hu@intel.com>
* config/i386/avx10_2roundingintrin.h: New intrins.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
2025-03-24 Haochen Jiang <haochen.jiang@intel.com>
Revert:
2024-08-19 Hu, Lin1 <lin1.hu@intel.com>
* config/i386/avx10_2roundingintrin.h: New intrins.
* config/i386/i386-builtin-types.def: Add new DEF_FUNCTION_TYPE.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/i386-expand.cc (ix86_expand_round_builtin):
Handle V8SF_FTYPE_V8SF_V8SF_INT_V8SF_UQI_INT,
V4DF_FTYPE_V4DF_V4DF_INT_V4DF_UQI_INT.
2025-03-24 Haochen Jiang <haochen.jiang@intel.com>
Revert:
2024-08-19 Hu, Lin1 <lin1.hu@intel.com>
* config/i386/avx10_2roundingintrin.h: New intrins.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/sse.md:
(<mask_codefor>reducep<mode><mask_name><round_saeonly_name>):
Add condition check.
(<avx512>_rndscale<mode><mask_name><round_saeonly_name>): Ditto.
2025-03-24 Haochen Jiang <haochen.jiang@intel.com>
Revert:
2024-08-19 Hu, Lin1 <lin1.hu@intel.com>
* config/i386/avx10_2roundingintrin.h: New intrins.
* config/i386/i386-builtin.def: Add new builtins.
* config/i386/sse.md:
(<avx512>_scalef<mode><mask_name><round_name>): Add condition check.
2025-03-24 Haochen Jiang <haochen.jiang@intel.com>
Revert:
2024-08-19 Hu, Lin1 <lin1.hu@intel.com>
* config/i386/avx10_2roundingintrin.h: New intrins.
* config/i386/i386-builtin.def (BDESC): Add new builtins.
2025-03-24 Haochen Jiang <haochen.jiang@intel.com>
* config/i386/avx10_2satcvtintrin.h: Remove rounding intrins.
Use non-round intrins.
* config/i386/i386-builtin.def (BDESC): Ditto.
2025-03-24 Haochen Jiang <haochen.jiang@intel.com>
* config/i386/avx10_2convertintrin.h: Remove rounding intrins.
Use non-round builtins.
* config/i386/avx10_2minmaxintrin.h: Ditto.
* config/i386/i386-builtin.def (BDESC): Ditto.
* config/i386/i386-builtin-types.def: Remove unused type.
* config/i386/i386-expand.cc
(ix86_expand_args_builtin): Ditto.
(ix86_expand_round_builtin): Ditto.
2025-03-23 Sandra Loosemore <sloosemore@baylibre.com>
PR other/42270
* doc/extend.texi (Nonlocal Gotos): Group with other built-ins
sections.
(Constructing Calls): Likewise.
(Pragmas): Move earlier in the section, before the built-ins docs.
(Thread-Local): Likewise.
(OpenMP): Likewise.
(OpenACC): Likewise.
2025-03-23 Sandra Loosemore <sloosemore@baylibre.com>
PR other/42270
* doc/extend.texi (Syntax Extensions): New section.
(Statement Exprs): Make it a subsection of the above.
(Local Labels): Likewise.
(Labels as Values): Likewise.
(Nested Functions): Likewise.
(Typeof): Likewise.
(Offsetof): Likewise.
(Alignment): Likewise.
(Incomplete Enums): Likewise.
(Variadic Macros): Likewise.
(Conditionals): Likewise.
(Case Ranges): Likewise.
(Mixed Labels and Declarations): Likewise.
(C++ Comments): Likewise.
(Escaped Newlines): Likewise.
(Hex Floats): Likewise.
(Binary constants): Likewise.
(Dollar Signs): Likewise.
(Character Escapes): Likewise.
(Alternate Keywords): Likewise.
(Function Names): Likewise.
(Semantic Extensions): New section.
(Function Prototypes): Make it a subsection of the above.
(Pointer Arith): Likewise.
(Variadic Pointer Args): Likewise.
(Pointers to Arrays): Likewise.
(Const and Volatile Functions): Likewise.
2025-03-23 Sandra Loosemore <sloosemore@baylibre.com>
PR other/42270
* doc/extend.texi (Aggregate Types): New section.
(Variable Length): Make it a subsection of the above.
(Zero Length): Likewise.
(Empty Structures): Likewise.
(Flexible Array Members in Unions): Likewise.
(Flexible Array Members alone in Structures): Likewise.
(Unnamed Fields): Likewise.
(Cast to Union): Likewise.
(Subscripting): Likewise.
(Initializers): Likewise.
(Compound Literals): Likewise.
(Designated Inits): Likewise.
2025-03-23 Sandra Loosemore <sloosemore@baylibre.com>
PR other/42270
* doc/extend.texi (Additional Numeric Types): New section.
(__int128): Make it a subsection of the above.
(Long Long): Likewise.
(Complex): Likewise.
(Floating Types): Likewise.
(Half-Precision): Likewise.
(Decimal Float): Likewise.
(Fixed-Point): Likewise.
2025-03-23 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr-mcus.def: Add AVR32SD20, AVR32SD28, AVR32SD32,
AVR64SD28, AVR64SD32, AVR64SD48.
* doc/avr-mmcu.texi: Rebuild.
2025-03-23 Georg-Johann Lay <avr@gjlay.de>
* doc/invoke.texi (AVR Optimization Options)
<-maccumulate-args>: Refer to -fdefer-pop.
<-muse-nonzero-bits>: Re-formulate what the option does.
2025-03-22 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr.cc (avr_option_override): Use
"avr-peep2-after-fuse-move" as dump name instead of "peephole2".
2025-03-22 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr.opt.urls: Add -muse-nonzero-bits.
2025-03-22 Georg-Johann Lay <avr@gjlay.de>
PR target/119421
* config/avr/avr.opt (-muse-nonzero-bits): New option.
* config/avr/avr-protos.h (avr_nonzero_bits_lsr_operands_p): New.
(make_avr_pass_split_nzb): New.
* config/avr/avr.cc (avr_nonzero_bits_lsr_operands_p): New function.
(avr_rtx_costs_1): Return costs for the new insns.
* config/avr/avr.md (nzb): New insn attribute.
(*nzb=1.<code>...): New insns to better support some bit
operations for <code> in AND, IOR, XOR.
* config/avr/avr-passes.def (avr_pass_split_nzb): Insert pass
atfer combine.
* config/avr/avr-passes.cc (avr_pass_data_split_nzb). New pass data.
(avr_pass_split_nzb): New pass.
(make_avr_pass_split_nzb): New function.
* common/config/avr/avr-common.cc (avr_option_optimization_table):
Enable -muse-nonzero-bits for -O2 and higher.
* doc/invoke.texi (AVR Options): Document -muse-nonzero-bits.
2025-03-22 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr.cc (avr_attrs_section_name): New function.
(avr_insert_attributes): Add "used" attribute to functions
in .initN and .finiN.
2025-03-22 Iain Sandoe <iain@sandoe.co.uk>
* config/darwin.h (DL_LIBRARY): New.
2025-03-22 Jakub Jelinek <jakub@redhat.com>
* gimplify.cc (warn_switch_unreachable_and_auto_init_r): Add missing
space in the middle of diagnostics.
* tree-vect-stmts.cc (vectorizable_load): Add missing space in the
middle of debug dump message.
* sym-exec/sym-exec-state.cc (state::check_args_compatibility):
Likewise.
2025-03-21 Surya Kumari Jangala <jskumari@linux.ibm.com>
Jakub Jelinek <jakub@redhat.com>
PR rtl-optimization/116028
PR rtl-optimization/118615
* lra-constraints.cc (first_call_insn): New variable.
(split_reg): Spill register before first_call_insn if call_save_p
and the call is in a different bb in the ebb.
(split_if_necessary): Formatting fix.
(inherit_in_ebb): Set first_call_insn when handling a CALL_INSN.
For successful split_if_necessary with before_p, only change
use_insn if it emitted any new instructions before curr_insn.
Clear first_call_insn before returning.
2025-03-21 Paul-Antoine Arras <parras@baylibre.com>
Tobias Burnus <tburnus@baylibre.com>
* builtin-types.def
(BT_FN_VOID_INT_INT_PTR_PTR_PTR_INT_PTR_INT_PTR_UINT_PTR): New.
* gimple-low.cc (lower_stmt): Handle GIMPLE_OMP_INTEROP.
* gimple-pretty-print.cc (dump_gimple_omp_interop): New function.
(pp_gimple_stmt_1): Handle GIMPLE_OMP_INTEROP.
* gimple.cc (gimple_build_omp_interop): New function.
(gimple_copy): Handle GIMPLE_OMP_INTEROP.
* gimple.def (GIMPLE_OMP_INTEROP): Define.
* gimple.h (gimple_build_omp_interop): Declare.
(gimple_omp_interop_clauses): New function.
(gimple_omp_interop_clauses_ptr): Likewise.
(gimple_omp_interop_set_clauses): Likewise.
(gimple_return_set_retval): Handle GIMPLE_OMP_INTEROP.
* gimplify.cc (gimplify_scan_omp_clauses): Handle OMP_CLAUSE_INIT,
OMP_CLAUSE_USE and OMP_CLAUSE_DESTROY.
(gimplify_omp_interop): New function.
(gimplify_expr): Replace sorry with call to gimplify_omp_interop.
* omp-builtins.def (BUILT_IN_GOMP_INTEROP): Define.
* omp-low.cc (scan_sharing_clauses): Handle OMP_CLAUSE_INIT,
OMP_CLAUSE_USE and OMP_CLAUSE_DESTROY.
(scan_omp_1_stmt): Handle GIMPLE_OMP_INTEROP.
(lower_omp_interop_action_clauses): New function.
(lower_omp_interop): Likewise.
(lower_omp_1): Handle GIMPLE_OMP_INTEROP.
2025-03-21 Jason Merrill <jason@redhat.com>
PR c++/114992
* multiple_target.cc (create_dispatcher_calls):
remove_from_same_comdat_group before add_to_same_comdat_group.
2025-03-21 Dhruv Chawla <dhruvc@nvidia.com>
* config/aarch64/aarch64-cores.def (olympus): New entry.
* config/aarch64/aarch64-tune.md: Regenerate.
* doc/invoke.texi (AArch64 Options): Document the above.
2025-03-21 Antoni Boucher <bouanto@zoho.com>
* config/i386/i386-rust-and-jit.inc: New file.
* config/i386/i386-rust.cc: Move code to i386-rust-and-jit.inc.
2025-03-21 Jakub Jelinek <jakub@redhat.com>
PR ipa/119376
* ipa-icf-gimple.cc (func_checker::compare_gimple_call): Return false
for gimple_call_must_tail_p mismatches.
2025-03-21 Jakub Jelinek <jakub@redhat.com>
PR ipa/119376
* ipa-split.cc (split_function): Call gimple_call_set_must_tail
on the call to outlined partition if has_musttail and
!add_tsan_func_exit.
2025-03-21 Jakub Jelinek <jakub@redhat.com>
PR ipa/119376
* tree-inline.cc (remap_gimple_stmt): Silently clear
gimple_call_must_tail_p on inlined call stmts if id->call_stmt
is a call without that flag set.
2025-03-21 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
PR target/119235
* config/s390/s390.cc (s390_hard_regno_mode_ok): Accept only
Pmode for registers AP/FP/RA.
2025-03-21 Richard Biener <rguenther@suse.de>
* cgraphunit.cc (symbol_table::finalize_compilation_unit):
Put early debug generation under TV_SYMOUT.
2025-03-21 Andrew Pinski <quic_apinski@quicinc.com>
PR rtl-optimization/118914
* combine.cc (recog_for_combine): Add old_nregs and new_nregs
argument (defaulting to 0). Update call to recog_for_combine_1.
(combine_split_insns): Add old_nregs and new_nregs arguments,
store the old and new max registers to them.
(try_combine): Update calls to combine_split_insns and
pass old_nregs and new_nregs for the i3 call to recog_for_combine.
(find_split_point): Update call to combine_split_insns; ignoring
the values there.
(recog_for_combine_1): Add old_nregs and new_nregs arguments,
if the insn was recognized (and not to no-op move), add the
REG_DEAD notes to pnotes argument.
2025-03-20 Richard Biener <rguenther@suse.de>
PR tree-optimization/119389
* tree-ssa-sccvn.cc (dominated_by_p_w_unex): Limit the number
of predecessors of a CFG merge we try to skip.
2025-03-20 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
Revert:
2025-03-11 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* config.gcc: Fail in case of option --with-mode=esa.
* config/s390/s390.cc (s390_option_override_internal): Default
to z/Architecture mode.
* config/s390/s390.h (DRIVER_SELF_SPECS): Ditto.
* config/s390/s390.opt: Emit a warning for option -mesa.
* doc/invoke.texi: Document the change.
2025-03-20 Filip Kastl <fkastl@suse.cz>
* gimple-ssa-sccopy.cc (scc_copy_prop::propagate): Don't
increment after vec::unordered_remove().
2025-03-20 Richard Biener <rguenther@suse.de>
* tree-core.h (function_decl_type): Make a scoped enum.
* tree.h (set_function_decl_type): Adjust.
(DECL_IS_OPERATOR_NEW_P): Likewise.
(DECL_SET_IS_OPERATOR_NEW): Likewise.
(DECL_IS_OPERATOR_DELETE_P): Likewise.
(DECL_SET_IS_OPERATOR_DELETE): Likewise.
(DECL_LAMBDA_FUNCTION_P): Likewise.
(DECL_SET_LAMBDA_FUNCTION): Likewise.
* lto-streamer-out.cc (hash_tree): Hash all of
FUNCTION_DECL_DECL_TYPE.
* tree-streamer-out.cc (pack_ts_function_decl_value_fields):
Adjust.
* config/aarch64/aarch64-simd-pragma-builtins.def (vcombine_mf8):
Use literal zero instead of NONE.
2025-03-20 liuhongt <hongtao.liu@intel.com>
PR target/117452
* config/i386/i386.md (cbranchbf4): Use
ix86_fp_comparison_operator instead of comparison_operator.
2025-03-20 Hu, Lin1 <lin1.hu@intel.com>
* config/i386/avx10_2-512satcvtintrin.h: Add "s_" before
intrinsics' core name.
* config/i386/avx10_2satcvtintrin.h: Ditto.
2025-03-20 Hu, Lin1 <lin1.hu@intel.com>
* config/i386/avx10_2-512satcvtintrin.h: Add new intrinsics.
* config/i386/avx10_2satcvtintrin.h: Ditto.
* config/i386/i386-builtin-types.def:
Add DEF_FUNCTION_TYPE (V32HI, V32HF, V32HI, USI),
(V16SI, V16SF, V16SI, UHI), (V8DI, V8SF, V8DI, UQI),
(V8DI, V8DF, V8DI, UQI), (V8SI, V8DF, V8SI, UQI).
* config/i386/i386-builtin.def: Add new builtins.
* config/i386/i386-expand.cc: Handle V16SI_FTYPE_V16SF_V16SI_UHI,
V32HI_FTYPE_V32HF_V32HI_USI, V8DI_FTYPE_V8SF_V8DI_UQI,
V8DI_FTYPE_V8DF_V8DI_UQI, V8SI_FTYPE_V8DF_V8SI_UQI.
2025-03-20 Hu, Lin1 <lin1.hu@intel.com>
* config/i386/avx10_2-512satcvtintrin.h: Change *i[u]bs's type suffix
of intrin name.
* config/i386/avx10_2satcvtintrin.h: Ditto.
2025-03-19 Vladimir N. Makarov <vmakarov@redhat.com>
PR target/119270
* ira-costs.cc (calculate_equiv_gains): Ignore equiv init insns
only for invariants.
2025-03-19 David Malcolm <dmalcolm@redhat.com>
PR c/119366
* diagnostic-format-sarif.cc (test_message_with_embedded_link):
Convert diagnostic_context from one urlifier to a stack of
urlifiers, where each node in the stack tracks whether the
urlifier is owned or borrowed.
* diagnostic.cc (diagnostic_context::initialize): Likewise.
(diagnostic_context::finish): Likewise.
(diagnostic_context::set_urlifier): Delete.
(diagnostic_context::push_owned_urlifier): New.
(diagnostic_context::push_borrowed_urlifier): New.
(diagnostic_context::pop_urlifier): New.
(diagnostic_context::get_urlifier): Reimplement in terms of stack.
(diagnostic_context::override_urlifier): Delete.
* diagnostic.h (diagnostic_context::set_urlifier): Delete decl.
(diagnostic_context::override_urlifier): Delete decl.
(diagnostic_context::push_owned_urlifier): New decl.
(diagnostic_context::push_borrowed_urlifier): New decl.
(diagnostic_context::pop_urlifier): New decl.
(diagnostic_context::get_urlifier): Make return value const; hide
implementation.
(diagnostic_context::m_urlifier): Replace with...
(diagnostic_context::urlifier_stack_node): ... this and...
(diagnostic_context::m_urlifier_stack): ...this.
* gcc-urlifier.cc
(auto_override_urlifier::auto_override_urlifier): Reimplement.
(auto_override_urlifier::~auto_override_urlifier): Reimplement.
* gcc-urlifier.h (class auto_override_urlifier): Reimplement.
(auto_urlify_attributes::auto_urlify_attributes): Update for
pass-by-reference.
* gcc.cc (driver::global_initializations): Update for
reimplementation of urlifiers in terms of a stack.
* toplev.cc (general_init): Likewise.
2025-03-19 Jakub Jelinek <jakub@redhat.com>
PR target/119357
* config/i386/sse.md (pmovmskb 0xffff to ptest splitter,
*pmovsk_ptest_<mode>_avx512): Force operands[0] into a REG.
2025-03-19 Kyrylo Tkachov <ktkachov@nvidia.com>
* config/aarch64/aarch64-arches.def (...): Add SVE2p1.
* doc/invoke.texi (AArch64 Options): Document +sve2p1 in
-march=armv9.4-a.
2025-03-19 Xi Ruoyao <xry111@xry111.site>
* config/loongarch/loongarch.h (ADDITIONAL_REGISTER_NAMES): Add
fa0-fa7, ft0-ft16, and fs0-fs7.
2025-03-18 Georg-Johann Lay <avr@gjlay.de>
PR target/119355
* config/avr/avr-passes.cc (memento_t::apply): Only
read values[p.arg] when it is actually used.
2025-03-18 Iain Sandoe <iain@sandoe.co.uk>
PR cobol/119301
* config.in: Regenerate.
* configure: Regenerate.
* configure.ac: Add check for get_current_dir_name.
2025-03-18 Jakub Jelinek <jakub@redhat.com>
PR c/116545
* doc/extend.texi (musttail statement attribute): Document
that musttail GNU attribute can be used as well.
2025-03-18 Michael Matz <matz@suse.de>
* config/rs6000/rs6000.opt.urls: Regenerate.
2025-03-18 Jakub Jelinek <jakub@redhat.com>
* doc/sourcebuild.texi (dg-output-file): Document.
2025-03-18 Andrew Pinski <quic_apinski@quicinc.com>
* gimple-ssa-sccopy.cc (scc_copy_prop::replace_scc_by_value): Dump
what is being replaced with what.
2025-03-18 Jakub Jelinek <jakub@redhat.com>
PR rtl-optimization/119307
* lra.cc (lra_rtx_hash): Handle SUBREG.
2025-03-18 Richard Biener <rguenther@suse.de>
PR debug/101533
* dwarf2out.cc (gen_type_die_with_usage): When we have
output the typedef already do nothing for a typedef variant.
Do not set TREE_ASM_WRITTEN on the type.
2025-03-18 Jeff Law <jlaw@ventanamicro.com>
* config/riscv/riscv.md (equality shifted-arith splitter): Do not
create op AND -1 as it won't be cleaned up post-reload.
2025-03-18 Andrew Pinski <quic_apinski@quicinc.com>
* configure: Regenerate.
* configure.ac: s/gcc_cv_ld64_macosx_version_min/gcc_cv_ld64_macos_version_min/.
2025-03-17 Jeff Law <jlaw@ventanamicro.com>
* config/riscv/bitmanip.md (*<or_optab>i<mode>_extrabit): Reject cases
where we only need to twiddle one bit. Fix formatting.
(*andi<mode>extrabit): Likewise.
2025-03-17 Vladimir N. Makarov <vmakarov@redhat.com>
PR rtl-optimization/119285
* ira-costs.cc (equiv_can_be_consumed_p): Use 2 ways for
recognizing a valid insn after equiv insertion.
2025-03-17 Michael Matz <matz@suse.de>
PR target/112980
* config/rs6000/rs6000.opt (msplit-patch-nops): New option.
* doc/invoke.texi (RS/6000 and PowerPC Options): Document it.
* config/rs6000/rs6000.h (machine_function.stop_patch_area_print):
New member.
* config/rs6000/rs6000.cc (rs6000_print_patchable_function_entry):
Emit split nops under control of that one.
* config/rs6000/rs6000-logue.cc (rs6000_output_function_prologue):
Add handling of split patch nops.
2025-03-17 Michal Jires <mjires@suse.cz>
* common.opt.urls: Regenerate.
2025-03-17 Michal Jires <mjires@suse.cz>
* doc/invoke.texi: (Optimize Options):
Add incremental LTO flags.
2025-03-17 Robin Dapp <rdapp@ventanamicro.com>
PR target/119114
* config/riscv/autovec.md: Apply & 0x1 mask when initializing
bitmask vector.
2025-03-17 Ayan Shafqat <ayan.x.shafqat@gmail.com>
* config/aarch64/arm_acle.h (__fma, __fmaf): New functions.
2025-03-17 Richard Biener <rguenther@suse.de>
* opts.cc (gen_producer_string): Record -D and -U
with _FORTIFY_SOURCE prefix.
2025-03-16 Jeff Law <jlaw@ventanamicro.com>
PR target/116256
* config/riscv/riscv.md (reassociation splitters): Do not load the
adjusted addend into a register if it fits in a simm12.
2025-03-16 Andrew Pinski <quic_apinski@quicinc.com>
PR middle-end/113546
* tree-cfg.cc (first_non_label_stmt): Rename to ...
(first_non_label_nondebug_stmt): This and use gsi_start_nondebug_after_labels_bb.
(assign_discriminators): Update call to first_non_label_nondebug_stmt.
2025-03-16 Iain Sandoe <iain@sandoe.co.uk>
Backported from master:
2025-03-16 Iain Sandoe <iain@sandoe.co.uk>
PR target/119172
* config.in: Regenerate.
* config/darwin.h (DARWIN_PLATFORM_ID): Add the option to
use -macos_version_min where available.
* configure: Regenerate.
* configure.ac: Check for ld64 support of -macos_version_min.
2025-03-14 Martin Jambor <mjambor@suse.cz>
PR ipa/116572
* cgraph.cc (cgraph_update_edges_for_call_stmt): Do not update
edges of clones that are unexpanded thunk. Assert that the node
passed as the parameter is not an unexpanded thunk.
2025-03-14 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/119287
* match.pd (((X >> C1) & C2) * (1 << C1) to X & (C2 << C1)): Use
(convert @0) instead of @0 in the substitution.
2025-03-14 Thomas Schwinge <thomas@codesourcery.com>
PR target/92713
PR target/101544
* config/gcn/gcn.h (LIBSTDCXX): Don't set.
* config/nvptx/nvptx.h (LIBSTDCXX): Likewise.
2025-03-14 Richard Biener <rguenther@suse.de>
PR tree-optimization/119274
* tree-ssa-sccvn.cc (dominated_by_p_w_unex): Handle the
top block being the only executable forwarder to a CFG
merge.
2025-03-14 Richard Sandiford <richard.sandiford@arm.com>
* tree-vect-slp.cc (vect_build_slp_instance): Pass the new group
size (i) rather than 1 to vect_slp_prefer_store_lanes_p.
(vect_analyze_slp): Only force the use of load-lanes and
store-lanes if that is preferred for at least one load/store pair.
2025-03-14 Richard Biener <rguenther@suse.de>
PR tree-optimization/119155
* tree-vect-stmts.cc (vectorizable_store): Do not always
use vector element alignment for VMAT_STRIDED_SLP but
a more correct alignment towards both ends.
(vectorizable_load): Likewise.
2025-03-14 Sandra Loosemore <sloosemore@baylibre.com>
* doc/extend.texi (Alternate Keywords): Clean up text and remove
discussion of "restrict", which is not a GNU extension at all.
* doc/invoke.texi (C Dialect Options): Remove detailed discussion.
2025-03-13 Jan Hubicka <hubicka@ucw.cz>
PR ipa/119147
* ipa-inline.cc: Include ipa-modref-tree.h and
ipa-modref.h.
(speculation_useful_p): If target is a clone, speculation is usef;
fix mixup of caller and callee; speculate also calls not considered
hot; consider modref summary also possibly useful for optimization.
* ipa-profile.cc (ipa_profile): Keep non-hot speculations.
2025-03-13 Richard Biener <rguenther@suse.de>
* tree.h (DECL_NOT_GIMPLE_REG_P): Update description.
2025-03-13 Wilco Dijkstra <wilco.dijkstra@arm.com>
* common/config/aarch64/cpuinfo.h: Remove FEAT_PREDRES and FEAT_LS64*.
* config/aarch64/aarch64-option-extensions.def: Remove FMV support
for PREDRES.
2025-03-13 Richard Sandiford <richard.sandiford@arm.com>
* match.pd: Extend pointer alignment folds so that they handle
the case where a constant is added before or after the alignment.
2025-03-13 Richard Sandiford <richard.sandiford@arm.com>
* match.pd: Fold ((X >> C1) & C2) * (1 << C1) to X & (C2 << C1).
2025-03-13 Robin Dapp <rdapp@ventanamicro.com>
PR target/119115
* config/riscv/riscv-vsetvl.cc (reg_used): New function.
(reg_single_use_in_avl): Ditto.
(pre_vsetvl::fuse_local_vsetvl_info): Use reg_single_use_in_avl
when checking if vsetvl can be deleted.
2025-03-13 Robin Dapp <rdapp@ventanamicro.com>
PR target/117955
* config/riscv/riscv-vsetvl.cc: Use LMUL/ratio from vsetvl with
larger SEW.
2025-03-13 Matthias Klose <doko@ubuntu.com>
* configure.ac: Add option --enable-versioned-jit.
* configure: Regenerate.
* Makefile.in: Move from jit/Make-lang.in, setting value from
configure.ac.
* doc/install.texi: Document option --enable-versioned-jit.
2025-03-13 Xi Ruoyao <xry111@xry111.site>
PR target/119238
* config/loongarch/simd.md (<su>dot_prod<wvec_half><mode>):
Stop using structured binding.
2025-03-12 Alex Coplan <alex.coplan@arm.com>
PR rtl-optimization/116564
* df-problems.cc (df_simulate_defs): For partial defs, mark the
register live (treat it as a RMW operation).
2025-03-12 Richard Earnshaw <rearnsha@arm.com>
PR target/115439
* config/arm/predicates.md (vpr_register_operand): Allow type-punning
subregs.
2025-03-12 Richard Sandiford <richard.sandiford@arm.com>
PR target/116901
* config/aarch64/aarch64.cc (aarch64_vector_costs::count_ops): Allow
stmt_info to be null.
(aarch64_vector_costs::add_stmt_cost): Call count_ops even if
stmt_info is null.
2025-03-12 Richard Sandiford <richard.sandiford@arm.com>
PR tree-optimization/116901
* tree-vect-loop.cc (vectorizable_reduction): Set ncopies to
SLP_TREE_NUMBER_OF_VEC_STMTS for SLP.
2025-03-12 Jakub Jelinek <jakub@redhat.com>
* tree.def (RAW_DATA_CST): Document meaning of NULL RAW_DATA_OWNER.
(CONSTRUCTOR): Document meaning of RAW_DATA_CST used as element
value.
2025-03-12 Jakub Jelinek <jakub@redhat.com>
PR middle-end/119204
PR middle-end/119219
* builtins.cc (fold_builtin_2): Pass type as another argument
to fold_builtin_strspn and fold_builtin_strcspn.
(fold_builtin_strspn): Add type argument, use it instead of
size_type_node.
(fold_builtin_strcspn): Add type argument, use it instead of
TREE_TYPE (expr).
2025-03-12 Jeff Law <jlaw@ventanamicro.com>
Revert:
2025-03-09 Jeff Law <jlaw@ventanamicro.com>
PR rtl-optimization/117467
* ext-dce.cc (ext_dce_process_uses): When trivially possible advance
the iterator over the destination of a SET.
2025-03-11 Andrew Pinski <quic_apinski@quicinc.com>
PR target/119131
* config/aarch64/aarch64.cc (aarch64_valid_fp_move): Remove check
for !DECIMAL_FLOAT_MODE_P.
(aarch64_float_const_representable_p): Reject decimal floating modes.
* config/aarch64/aarch64.md (mov<mode>): Likewise.
2025-03-11 Jonathan Wakely <jwakely@redhat.com>
* doc/extend.texi (Common Variable Attributes): Fix grammar in
final sentence of -ftrivial-auto-var-init description.
2025-03-11 Juergen Christ <jchrist@linux.ibm.com>
* config/s390/s390.cc (s390_delegitimize_address): Add missing case.
2025-03-11 Martin Jambor <mjambor@suse.cz>
* tree-ssa-alias.cc (ao_compare::compare_ao_refs): Fix a
copy-and-paste error.
2025-03-11 Jakub Jelinek <jakub@redhat.com>
* dwarf2out.cc (gen_compile_unit_die): Use DW_LANG_Cobol85 if
language_string is "GCC COBOL" rather than "Cobol".
2025-03-11 Richard Biener <rguenther@suse.de>
PR middle-end/119204
* builtins.cc (fold_builtin_strcspn): Preserve the original
expression type.
2025-03-11 Jakub Jelinek <jakub@redhat.com>
PR c/119183
* tree.cc (skip_simple_arithmetic): If first operand of binary
expr is TREE_CONSTANT or TREE_READONLY with no side-effects, call
tree_invariant_p on that operand first instead of on the second.
2025-03-11 Jakub Jelinek <jakub@redhat.com>
PR debug/119190
* tree-complex.cc (update_complex_assignment, tree_lower_complex):
Perform simple dce on dce_worklist only if optimize.
2025-03-11 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* config.gcc: Fail in case of option --with-mode=esa.
* config/s390/s390.cc (s390_option_override_internal): Default
to z/Architecture mode.
* config/s390/s390.h (DRIVER_SELF_SPECS): Ditto.
* config/s390/s390.opt: Emit a warning for option -mesa.
* doc/invoke.texi: Document the change.
2025-03-11 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
PR target/115835
* config/s390/s390.cc (s390_insn_cost): Implement.
(TARGET_INSN_COST): Define.
2025-03-11 Richard Biener <rguenther@suse.de>
PR tree-optimization/119166
* tree-vect-stmts.cc (get_load_store_type): Guard SLP tree
access.
2025-03-11 James K. Lowden <jklowden@symas.com>
* doc/contrib.texi: Update for gcobol.
* doc/frontends.texi: Likewise.
* doc/install.texi: Likewise.
* doc/invoke.texi: Likewise.
* doc/sourcebuild.texi: Likewise.
* doc/standards.texi: Likewise.
2025-03-11 James K. Lowden <jklowden@symas.com>
* Makefile.in (installdirs): Create man3 directory.
* common.opt (static-libgcobol): New driver option.
* dwarf2out.cc (gen_compile_unit_die): Support Cobol as
source language.
2025-03-10 Richard Sandiford <richard.sandiford@arm.com>
Kugan Vivekanandarajah <kvivekananda@nvidia.com>
PR target/115258
* config/aarch64/aarch64.cc (aarch64_vectorize_vec_perm_const): Use
d.one_vector_p to decide whether op1 should be a copy of op0.
2025-03-10 Vladimir N. Makarov <vmakarov@redhat.com>
PR target/114991
* ira-costs.cc (equiv_can_be_consumed_p): Add new argument invariant_p.
Add code for dealing with the invariant.
(calculate_equiv_gains): Don't consider init insns. Pass the new
argument to equiv_can_be_consumed_p. Don't treat invariant as
memory.
2025-03-10 Sandra Loosemore <sloosemore@baylibre.com>
* doc/invoke.texi (Instrumentation Options): Fix typo introduced
in commit 313edeeeb607fe32da5633cfb6f91977add446f6.
2025-03-10 Christophe Lyon <christophe.lyon@linaro.org>
PR target/115439
* config/arm/mve.md (vec_vcmp, vec_vcmpu, vcond_mask): Use
vpr_register_operand predicate for MVE_VPRED operands.
2025-03-10 Xi Ruoyao <xry111@xry111.site>
PR target/119127
* config/loongarch/loongarch.cc
(loongarch_reassoc_shift_bitwise): Sign extend mask to mode,
specially handle the case it's extended to -1.
* config/loongarch/loongarch.md
(loongarch_reassoc_shift_bitwise): Update the comment for the
special case.
2025-03-10 Jakub Jelinek <jakub@redhat.com>
PR c/117178
* gimple-ssa-warn-access.cc (maybe_warn_nonstring_arg): Look through
multi-dimensional array types, stop at the innermost ARRAY_TYPE.
2025-03-09 Jeff Law <jlaw@ventanamicro.com>
PR rtl-optimization/117467
* ext-dce.cc (ext_dce_process_sets): Handle FP destinations better.
2025-03-09 Jeff Law <jlaw@ventanamicro.com>
PR rtl-optimization/117467
* ext-dce.cc (ext_dce_process_uses): When trivially possible advance
the iterator over the destination of a SET.
2025-03-09 Andrew Pinski <quic_apinski@quicinc.com>
PR tree-optimization/118922
* tree-ssa-phiopt.cc (value_replacement): Set empty_or_with_defined_p
to false when there is phi nodes for the middle bb.
2025-03-09 Sandra Loosemore <sloosemore@baylibre.com>
PR middle-end/118457
* gimplify.cc (modify_call_for_omp_dispatch): New, containing
code split from gimplify_call_expr and modified to emit tree
instead of gimple. Remove the error for falling through to a call
to the base function.
(expand_variant_call_expr): New, split from gimplify_variant_call_expr.
Call modify_call_for_omp_dispatch on calls to
variants in a dispatch construct context.
(gimplify_variant_call_expr): Make it call expand_variant_call_expr
to do the actual work.
(gimplify_call_expr): Remove sorry for calls involving both
dynamic/late selectors and adjust_args/append_args, and adjust
for new interface. Move adjust_args/append_args code to
modify_call_for_omp_dispatch.
(gimplify_omp_dispatch): Add some comments.
2025-03-08 Sandra Loosemore <sloosemore@baylibre.com>
* doc/extend.texi (Basic Asm): Document that AssemblerInstructions
can be an asm constexpr.
(Extended Asm): Move the notes about asm constexprs for
AssemblerTemplate and Clobbers to the corresponding subsections.
Remove the notes for OutputOperands and InputOperands and reword
misleading descriptions of the list item syntax. Note that
constraint strings can be asm constexprs.
(Asm constexprs): Use "title case" for subsection name. Be
explicit about what parts of the asm syntax this applies to and
that the parentheses are required. Correct markup and terminology.
2025-03-08 Sandra Loosemore <sloosemore@baylibre.com>
PR c/67301
* doc/extend.texi (Extended Asm): Clarify that the square brackets
around the asmSymbolicName of operands are a required part of
the syntax.
2025-03-07 Jakub Jelinek <jakub@redhat.com>
PR c/117178
* tree.cc (get_attr_nonstring_decl): Look through all ARRAY_REFs, not
just one and handle COMPONENT_REF and MEM_REF after skipping those
rather than only when there wasn't ARRAY_REF. Formatting fix.
2025-03-07 Kees Cook <kees@kernel.org>
Jakub Jelinek <jakub@redhat.com>
PR c/117178
* doc/invoke.texi (Wunterminated-string-initialization): Document
the new interaction between this warning and -Wc++-compat and that
initialization of decls with nonstring attribute aren't warned about.
2025-03-07 Sandra Loosemore <sloosemore@baylibre.com>
PR sanitizer/56682
* doc/invoke.texi (Instrumentation Options): Document that -g
is useful with -fsanitize=thread and -fsanitize=address.
Also mention -fno-omit-frame-pointer per the asan wiki.
2025-03-07 Richard Sandiford <richard.sandiford@arm.com>
Jan Hubicka <hubicka@ucw.cz>
H.J. Lu <hjl.tools@gmail.com>
PR rtl-optimization/117477
* config/aarch64/aarch64.cc (aarch64_count_saves): New function.
(aarch64_count_above_hard_fp_saves, aarch64_callee_save_cost)
(aarch64_frame_allocation_cost): Likewise.
(TARGET_CALLEE_SAVE_COST): Define.
(TARGET_FRAME_ALLOCATION_COST): Likewise.
* config/i386/i386.cc (ix86_ira_callee_saved_register_cost_scale):
Replace with...
(ix86_callee_save_cost): ...this new hook.
(TARGET_IRA_CALLEE_SAVED_REGISTER_COST_SCALE): Delete.
(TARGET_CALLEE_SAVE_COST): Define.
* target.h (spill_cost_type, frame_cost_type): New enums.
* target.def (callee_save_cost, frame_allocation_cost): New hooks.
(ira_callee_saved_register_cost_scale): Delete.
* doc/tm.texi.in (TARGET_IRA_CALLEE_SAVED_REGISTER_COST_SCALE): Delete.
(TARGET_CALLEE_SAVE_COST, TARGET_FRAME_ALLOCATION_COST): New hooks.
* doc/tm.texi: Regenerate.
* hard-reg-set.h (hard_reg_set_popcount): New function.
* ira-color.cc (allocated_memory_p): New variable.
(allocated_callee_save_regs): Likewise.
(record_allocation): New function.
(assign_hard_reg): Use targetm.frame_allocation_cost to model
the cost of the first spill or first caller save. Use
targetm.callee_save_cost to model the cost of using new callee-saved
registers. Apply the exit rather than entry frequency to the cost
of restoring a register or deallocating the frame. Update the
new variables above.
(improve_allocation): Use record_allocation.
(color): Initialize allocated_callee_save_regs.
(ira_color): Initialize allocated_memory_p.
* targhooks.h (default_callee_save_cost): Declare.
(default_frame_allocation_cost): Likewise.
* targhooks.cc (default_callee_save_cost): New function.
(default_frame_allocation_cost): Likewise.
2025-03-07 Sandra Loosemore <sloosemore@baylibre.com>
PR target/116708
* doc/invoke.texi (x86 Options): Clarify how -msse4 and -mno-sse4
interact with other SSE options.
2025-03-07 Martin Jambor <mjambor@suse.cz>
PR ipa/118318
* ipa-cp.cc (adjust_clone_incoming_counts): Add a compatible_p check.
2025-03-07 Richard Earnshaw <rearnsha@arm.com>
* config/arm/arm_neon.h: Try harder to detect if we have
the softfp ABI enabled.
2025-03-07 Jakub Jelinek <jakub@redhat.com>
PR c/112960
PR c/117029
* doc/extend.texi (Complex): Add I and J suffixes to the list of
complex suffixes, adjust for all of those being part of ISO C2Y,
clarify that for -fno-ext-numeric-literals none of those are
recognized as GNU extensions and for C++14 i is considered UDL
even for -fext-numeric-literals when <complex> is included.
2025-03-07 Simon Martin <simon@nasilyan.com>
* tree-vect-data-refs.cc: Define INCLUDE_ALGORITHM.
2025-03-07 Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/118464
PR tree-optimization/116855
* doc/invoke.texi (min-pagesize): Update docs with vectorizer use.
* tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Delay
checks.
(vect_compute_data_ref_alignment): Remove alignment checks and move to
get_load_store_type, increase group access alignment.
(vect_enhance_data_refs_alignment): Add note to comment needing
investigating.
(vect_analyze_data_refs_alignment): Likewise.
(vect_supportable_dr_alignment): For group loads look at first DR.
* tree-vect-stmts.cc (get_load_store_type):
Perform safety checks for early break pfa.
* tree-vectorizer.h (dr_set_safe_speculative_read_required,
dr_safe_speculative_read_required, DR_SCALAR_KNOWN_BOUNDS): New.
(need_peeling_for_alignment): Renamed to...
(safe_speculative_read_required): .. This
(class dr_vec_info): Add scalar_access_known_in_bounds.
2025-03-07 Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/118464
PR tree-optimization/116855
* config/aarch64/aarch64-sve.md (@extract_<last_op>_<mode>,
@fold_extract_<last_op>_<mode>,
@aarch64_fold_extract_vector_<last_op>_<mode>): Change SVE_FULL to
SVE_ALL.
* config/aarch64/iterators.md (vccore): Add more partial types.
2025-03-07 Richard Biener <rguenther@suse.de>
PR tree-optimization/119145
* tree-vectorizer.cc (try_vectorize_loop_1): Avoid BB
vectorizing an if-converted loop body when there's a .MASK_CALL
in the loop body.
2025-03-07 Christophe Lyon <christophe.lyon@linaro.org>
PR target/115485
* config/arm/arm.cc (require_pic_register): Fix typos in
comment. Handle fixed arm_pic_register.
2025-03-07 Richard Sandiford <richard.sandiford@arm.com>
PR tree-optimization/116125
* tree-vect-data-refs.cc (vect_prune_runtime_alias_test_list): Make
the dr_with_seg_len alignment fields describe tha access sizes as
well as the pointer alignment.
* tree-data-ref.cc (create_intersect_range_checks): Don't compensate
for invalid alignment fields here.
2025-03-07 Richard Sandiford <richard.sandiford@arm.com>
PR target/119133
* config/aarch64/aarch64.md
(*aarch64_bfi<GPI:mode><ALLX:mode>_<SUBDI_BITS>): Use
force_lowpart_subreg.
2025-03-07 Richard Biener <rguenther@suse.de>
PR middle-end/118801
* tree-ssa-dce.cc (eliminate_unnecessary_stmts): Prune
sequences of uninterrupted DEBUG BEGIN_STMTs, keeping only
the last of a set with unique location.
2025-03-07 Sandra Loosemore <sloosemore@baylibre.com>
PR c/113515
* doc/invoke.texi (Warning Options): Improve -Wstringop-overflow
documentation.
2025-03-07 Haochen Jiang <haochen.jiang@intel.com>
* config/i386/avx10_2-512convertintrin.h
(_mm512_mask_cvtbf8_ph): Correct mask width.
(_mm512_maskz_cvtbf8_ph): Ditto.
* config/i386/avx10_2convertintrin.h
(_mm256_mask_cvtbf8_ph): Ditto.
(_mm256_maskz_cvtbf8_ph): Ditto.
2025-03-06 Alexey Merzlyakov <alexey.merzlyakov@samsung.com>
PR rtl-optimization/119099
* ext-dce.cc (ext_dce_rd_transfer_n): Do not allow the livein
set to shrink.
2025-03-06 Simon Martin <simon@nasilyan.com>
* config/i386/x86-tune-sched.cc (ix86_fuse_mov_alu_p): Fix
comment typo, paramter -> parameter.
* config/lm32/lm32.cc (lm32_std_gimplify_va_arg_expr): Likewise.
2025-03-06 Wilco Dijkstra <wilco.dijkstra@arm.com>
PR target/118351
PR other/38768
* common/config/aarch64/aarch64-common.cc: Enable early scheduling with
-O3 and higher.
* doc/invoke.texi (-fschedule-insns): Update comment.
2025-03-06 Richard Sandiford <richard.sandiford@arm.com>
Revert:
2025-03-06 Richard Sandiford <richard.sandiford@arm.com>
Jan Hubicka <hubicka@ucw.cz>
PR rtl-optimization/117477
* config/aarch64/aarch64.cc (aarch64_count_saves): New function.
(aarch64_count_above_hard_fp_saves, aarch64_callee_save_cost)
(aarch64_frame_allocation_cost): Likewise.
(TARGET_CALLEE_SAVE_COST): Define.
(TARGET_FRAME_ALLOCATION_COST): Likewise.
* config/i386/i386.cc (ix86_ira_callee_saved_register_cost_scale):
Replace with...
(ix86_callee_save_cost): ...this new hook.
(TARGET_IRA_CALLEE_SAVED_REGISTER_COST_SCALE): Delete.
(TARGET_CALLEE_SAVE_COST): Define.
* target.h (spill_cost_type, frame_cost_type): New enums.
* target.def (callee_save_cost, frame_allocation_cost): New hooks.
(ira_callee_saved_register_cost_scale): Delete.
* doc/tm.texi.in (TARGET_IRA_CALLEE_SAVED_REGISTER_COST_SCALE): Delete.
(TARGET_CALLEE_SAVE_COST, TARGET_FRAME_ALLOCATION_COST): New hooks.
* doc/tm.texi: Regenerate.
* hard-reg-set.h (hard_reg_set_popcount): New function.
* ira-color.cc (allocated_memory_p): New variable.
(allocated_callee_save_regs): Likewise.
(record_allocation): New function.
(assign_hard_reg): Use targetm.frame_allocation_cost to model
the cost of the first spill or first caller save. Use
targetm.callee_save_cost to model the cost of using new callee-saved
registers. Apply the exit rather than entry frequency to the cost
of restoring a register or deallocating the frame. Update the
new variables above.
(improve_allocation): Use record_allocation.
(color): Initialize allocated_callee_save_regs.
(ira_color): Initialize allocated_memory_p.
* targhooks.h (default_callee_save_cost): Declare.
(default_frame_allocation_cost): Likewise.
* targhooks.cc (default_callee_save_cost): New function.
(default_frame_allocation_cost): Likewise.
2025-03-06 Richard Biener <rguenther@suse.de>
PR lto/114501
* ipa-free-lang-data.cc (find_decls_types_r): Explicitly
handle CONSTRUCTORs as walk_tree handling of those is
incomplete.
2025-03-06 Alex Coplan <alex.coplan@arm.com>
PR rtl-optimization/114492
* pair-fusion.cc (pair_fusion_bb_info::fuse_pair): Check for singleton
move range before calling restrict_movement.
(pair_fusion::try_promote_writeback): Likewise.
2025-03-06 Richard Sandiford <richard.sandiford@arm.com>
Jan Hubicka <hubicka@ucw.cz>
PR rtl-optimization/117477
* config/aarch64/aarch64.cc (aarch64_count_saves): New function.
(aarch64_count_above_hard_fp_saves, aarch64_callee_save_cost)
(aarch64_frame_allocation_cost): Likewise.
(TARGET_CALLEE_SAVE_COST): Define.
(TARGET_FRAME_ALLOCATION_COST): Likewise.
* config/i386/i386.cc (ix86_ira_callee_saved_register_cost_scale):
Replace with...
(ix86_callee_save_cost): ...this new hook.
(TARGET_IRA_CALLEE_SAVED_REGISTER_COST_SCALE): Delete.
(TARGET_CALLEE_SAVE_COST): Define.
* target.h (spill_cost_type, frame_cost_type): New enums.
* target.def (callee_save_cost, frame_allocation_cost): New hooks.
(ira_callee_saved_register_cost_scale): Delete.
* doc/tm.texi.in (TARGET_IRA_CALLEE_SAVED_REGISTER_COST_SCALE): Delete.
(TARGET_CALLEE_SAVE_COST, TARGET_FRAME_ALLOCATION_COST): New hooks.
* doc/tm.texi: Regenerate.
* hard-reg-set.h (hard_reg_set_popcount): New function.
* ira-color.cc (allocated_memory_p): New variable.
(allocated_callee_save_regs): Likewise.
(record_allocation): New function.
(assign_hard_reg): Use targetm.frame_allocation_cost to model
the cost of the first spill or first caller save. Use
targetm.callee_save_cost to model the cost of using new callee-saved
registers. Apply the exit rather than entry frequency to the cost
of restoring a register or deallocating the frame. Update the
new variables above.
(improve_allocation): Use record_allocation.
(color): Initialize allocated_callee_save_regs.
(ira_color): Initialize allocated_memory_p.
* targhooks.h (default_callee_save_cost): Declare.
(default_frame_allocation_cost): Likewise.
* targhooks.cc (default_callee_save_cost): New function.
(default_frame_allocation_cost): Likewise.
2025-03-06 Richard Biener <rguenther@suse.de>
PR middle-end/119119
* gimplify.cc (is_gimple_mem_rhs_or_call): All empty CTORs
are OK when not a register type.
2025-03-05 Hannes Braun <hannes@hannesbraun.net>
PR target/118942
* config/arm/arm_neon.h (vld1q_s8_x3): Use int8_t instead of
uint16_t.
(vld1q_s16_x3): Use int16_t instead of uint16_t.
(vld1q_s8_x4): Likewise.
(vld1q_s16_x4): Likewise.
2025-03-05 Kyrylo Tkachov <ktkachov@nvidia.com>
PR rtl-optimization/119046
* config/aarch64/aarch64.cc (aarch64_evpc_dup): Use VOIDmode for
PARALLEL.
2025-03-05 Kyrylo Tkachov <ktkachov@nvidia.com>
PR rtl-optimization/119046
* rtlanal.cc (may_trap_p_1): Don't mark FP-mode PARALLELs as trapping.
2025-03-05 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/118953
* value-range.cc (irange::union_bitmask): Update m_bitmask if
get_bitmask () is unknown_p and m_bitmask is not even when the
semantic bitmask didn't change and returning false.
2025-03-05 Richard Biener <rguenther@suse.de>
PR middle-end/97323
* tree.cc (gimple_canonical_types_compatible_p): Ignore
TYPE_MODE also for ARRAY_TYPE.
(verify_type): Likewise.
2025-03-05 Xi Ruoyao <xry111@xry111.site>
PR target/119084
* config/loongarch/lasx.md (UNSPEC_LASX_XVLDX): Remove.
(lasx_xvldx): Remove.
* config/loongarch/lsx.md (UNSPEC_LSX_VLDX): Remove.
(lsx_vldx): Remove.
* config/loongarch/simd.md (QIVEC): New define_mode_iterator.
(<simd_isa>_<x>vldx): New define_expand.
* config/loongarch/loongarch.cc (loongarch_address_insns_1): New
static function with most logic factored out from ...
(loongarch_address_insns): ... here. Call
loongarch_address_insns_1 with reg_reg_cost = 1.
(loongarch_address_cost): Call loongarch_address_insns_1 with
reg_reg_cost = la_addr_reg_reg_cost.
2025-03-04 Georg-Johann Lay <avr@gjlay.de>
* doc/invoke.texi (AVR Optimization Options): New @subsubsection
for pure optimization options.
2025-03-04 Oscar Gustafsson <oscar.gustafsson@gmail.com>
* doc/extend.texi: Improve example for __builtin_bswap16.
2025-03-04 Jan Hubicka <hubicka@ucw.cz>
* config/i386/i386.h (TARGET_AVOID_FALSE_DEP_FOR_TZCNT): New macro.
(TARGET_AVOID_FALSE_DEP_FOR_BLS): New macro.
* config/i386/i386.md (*bmi_blsi_<mode>): Add splitter for false
dependency.
(*bmi_blsi_<mode>_ccno): Add splitter for false dependency.
(*bmi_blsi_<mode>_falsedep): New pattern.
(*bmi_blsmsk_<mode>): Add splitter for false dependency.
(*bmi_blsmsk_<mode>_falsedep): New pattern.
(*bmi_blsr_<mode>): Add splitter for false dependency.
(*bmi_blsr_<mode>_cmp): Add splitter for false dependency
(*bmi_blsr_<mode>_cmp_falsedep): New pattern.
* config/i386/x86-tune.def (X86_TUNE_AVOID_FALSE_DEP_FOR_TZCNT): New tune.
(X86_TUNE_AVOID_FALSE_DEP_FOR_BLS): New tune.
2025-03-04 Jan Hubicka <hubicka@ucw.cz>
* config/i386/i386.h (TARGET_FUSE_ALU_AND_BRANCH_MEM): New macro.
(TARGET_FUSE_ALU_AND_BRANCH_MEM_IMM): New macro.
(TARGET_FUSE_ALU_AND_BRANCH_RIP_RELATIVE): New macro.
* config/i386/x86-tune-sched.cc (ix86_fuse_mov_alu_p): Support
non-single-set.
(ix86_macro_fusion_pair_p): Allow ALU which only clobbers;
be more careful about immediates; check TARGET_FUSE_ALU_AND_BRANCH_MEM,
TARGET_FUSE_ALU_AND_BRANCH_MEM_IMM, TARGET_FUSE_ALU_AND_BRANCH_RIP_RELATIVE;
verify that we never use unsigned checks with inc/dec.
* config/i386/x86-tune.def (X86_TUNE_FUSE_ALU_AND_BRANCH): New tune.
(X86_TUNE_FUSE_ALU_AND_BRANCH_MEM): New tune.
(X86_TUNE_FUSE_ALU_AND_BRANCH_MEM_IMM): New tune.
(X86_TUNE_FUSE_ALU_AND_BRANCH_RIP_RELATIVE): New tune.
2025-03-04 Tamar Christina <tamar.christina@arm.com>
PR target/118892
* config/aarch64/aarch64.md (copysign<GPF:mode>3): Use
force_lowpart_subreg instead of lowpart_subreg.
2025-03-04 Richard Sandiford <richard.sandiford@arm.com>
PR tree-optimization/118976
* fold-const.cc (const_unop): Use ~ rather than - for BIT_NOT_EXPR.
* config/aarch64/aarch64.cc (aarch64_test_sve_folding): New function.
(aarch64_run_selftests): Run it.
2025-03-04 Richard Sandiford <richard.sandiford@arm.com>
Jakub Jelinek <jakub@redhat.com>
PR rtl-optimization/119002
* simplify-rtx.cc
(simplify_context::simplify_logical_relational_operation): Handle
comparisons between CC values. If there is no evidence that the
CC values are unsigned, restrict the fold to always-true or
always-false results.
2025-03-04 Richard Biener <rguenther@suse.de>
PR tree-optimization/119096
* tree-vect-loop.cc (vect_transform_reduction): Use the
correct else value for .COND_fn.
2025-03-03 Andrew Carlotti <andrew.carlotti@arm.com>
* common/config/aarch64/aarch64-common.cc
(struct aarch64_extension_info): Add field.
(aarch64_get_required_features): New.
* config/aarch64/aarch64-builtins.cc
(aarch64_simd_switcher::aarch64_simd_switcher): Rename to...
(aarch64_target_switcher::aarch64_target_switcher): ...this,
and extend to handle sve, nosimd and target pragmas.
(aarch64_simd_switcher::~aarch64_simd_switcher): Rename to...
(aarch64_target_switcher::~aarch64_target_switcher): ...this,
and extend to handle sve, nosimd and target pragmas.
(handle_arm_acle_h): Use aarch64_target_switcher.
(handle_arm_neon_h): Rename switcher and pass explicit flags.
(aarch64_general_init_builtins): Ditto.
* config/aarch64/aarch64-protos.h
(class aarch64_simd_switcher): Rename to...
(class aarch64_target_switcher): ...this, and add new members.
(aarch64_get_required_features): New prototype.
* config/aarch64/aarch64-sve-builtins.cc
(sve_switcher::sve_switcher): Delete
(sve_switcher::~sve_switcher): Delete
(sve_alignment_switcher::sve_alignment_switcher): New
(sve_alignment_switcher::~sve_alignment_switcher): New
(register_builtin_types): Use alignment switcher
(init_builtins): Rename switcher.
(handle_arm_neon_sve_bridge_h): Ditto.
(handle_arm_sme_h): Ditto.
(handle_arm_sve_h): Ditto, and use alignment switcher.
* config/aarch64/aarch64-sve-builtins.h
(class sve_switcher): Delete.
(class sme_switcher): Delete.
(class sve_alignment_switcher): New.
* config/aarch64/t-aarch64 (aarch64-builtins.o): Add $(REGS_H).
(aarch64-sve-builtins.o): Remove $(REG_H).
2025-03-03 Richard Earnshaw <rearnsha@arm.com>
* config/arm/thumb1.md (split patterns for GEU and LEU): New.
2025-03-03 Uros Bizjak <ubizjak@gmail.com>
Revert:
2025-03-03 Uros Bizjak <ubizjak@gmail.com>
* combine.cc (distribute_notes):
Reverse negative logic in ternary operators.
2025-03-03 Uros Bizjak <ubizjak@gmail.com>
* combine.cc (distribute_notes):
Reverse negative logic in ternary operators.
2025-03-03 Uros Bizjak <ubizjak@gmail.com>
PR rtl-optimization/118739
* combine.cc (distribute_notes) <case REG_UNUSED>: Correct the
logic when the register is used by I3.
2025-03-03 Martin Jambor <mjambor@suse.cz>
PR ipa/118785
* ipa-cp.cc (ipa_vr_intersect_with_arith_jfunc): Handle non-conversion
unary operations separately before doing any conversions. Check
expr_type_first_operand_type_p for non-unary operations too. Fix type
of op_res.
2025-03-03 Richard Biener <rguenther@suse.de>
PR tree-optimization/119057
* tree-vect-loop.cc (check_reduction_path): Add argument
specifying whether we're analyzing the inner loop of a
double reduction. Do not allow extra uses outside of the
double reduction cycle in this case.
(vect_is_simple_reduction): Adjust.
2025-03-03 Richard Biener <rguenther@suse.de>
PR ipa/119067
* ipa-devirt.cc (odr_types_equivalent_p): Check
TYPE_VECTOR_SUBPARTS for vectors.
2025-03-02 Jeff Law <jlaw@ventanamicro.com>
PR target/118934
* config/riscv/corev.md (cv_branch): Adjust output template.
(branch): Likewise.
* config/riscv/riscv.md (branch): Likewise.
* config/riscv/riscv.cc (riscv_asm_output_opcode): Handle 'r' rather
than 'n'.
2025-03-02 Jakub Jelinek <jakub@redhat.com>
PR translation/118991
* config/avr/avr.cc (avr_print_operand): Print ival into
a temporary buffer and use %s in output_operand_lossage to make
the diagnostics translatable.
2025-03-02 Filip Kastl <fkastl@suse.cz>
PR tree-optimization/117919
* gimple-ssa-sccopy.cc (scc_copy_prop::propagate): Prune
statements that 'replace_uses_by ()' removed.
2025-03-01 Gerald Pfeifer <gerald@pfeifer.com>
PR target/69374
* doc/install.texi (Specific, *-*-freebsd*): Simplify description.
2025-03-01 Jakub Jelinek <jakub@redhat.com>
PR jit/117047
* ggc-common.cc (ggc_internal_cleared_alloc_no_dtor): Pass size
rather than s as the first argument to ggc_internal_cleared_alloc.
2025-03-01 Yuriy Kolerov <Yuriy.Kolerov@synopsys.com>
PR target/118906
* common/config/riscv/riscv-common.cc: fix zce to zcf
implication.
2025-03-01 Jan Dubiec <jdx@o2.pl>
PR target/114222
* config/h8300/h8300.cc (h8300_init_libfuncs): For HImode override
calls to external ffs() (from newlib) with calls to __ffshi2() from
libgcc. The implementation of ffs() in newlib calls __builtin_ffs()
what causes infinite recursion and finally a stack overflow.
2025-03-01 Jakub Jelinek <jakub@redhat.com>
PR other/119052
* input.cc (check_line): Don't call sscanf on non-null terminated
buffer, instead copy line.length () bytes from line.get_buffer ()
to a local buffer, null terminate it and call sscanf on that.
Formatting fix.
(test_replacement): Just allocate maxline * 5 rather than maxline * 15
bytes for the file. Formatting fix.
2025-03-01 Jakub Jelinek <jakub@redhat.com>
PR jit/117047
* acinclude.m4 (gcc_CHECK_ATTRIBUTE_ALIAS): New.
* configure.ac: Add gcc_CHECK_ATTRIBUTE_ALIAS.
* ggc.h (ggc_internal_alloc): Remove ATTRIBUTE_MALLOC from
overload with finalizer pointer. Call ggc_internal_alloc_no_dtor
in inline overload without finalizer pointer.
(ggc_internal_alloc_no_dtor): Declare.
(ggc_internal_cleared_alloc): Remove ATTRIBUTE_MALLOC from
overload with finalizer pointer. Call
ggc_internal_cleared_alloc_no_dtor in inline overload without
finalizer pointer.
(ggc_internal_cleared_alloc_no_dtor): Declare.
(ggc_alloc): Call ggc_internal_alloc_no_dtor if no finalization
is needed.
(ggc_alloc_no_dtor): Call ggc_internal_alloc_no_dtor.
(ggc_cleared_alloc): Call ggc_internal_cleared_alloc_no_dtor if no
finalization is needed.
(ggc_vec_alloc): Call ggc_internal_alloc_no_dtor if no finalization
is needed.
(ggc_cleared_vec_alloc): Call ggc_internal_cleared_alloc_no_dtor if no
finalization is needed.
* ggc-page.cc (ggc_internal_alloc): If HAVE_ATTRIBUTE_ALIAS, turn
overload with finalizer into alias to ggc_internal_alloc_ and
rename it to ...
(ggc_internal_alloc_): ... this, make it extern "C".
(ggc_internal_alloc_no_dtor): New alias if HAVE_ATTRIBUTE_ALIAS,
otherwise new noinline wrapper.
* ggc-common.cc (ggc_internal_cleared_alloc): If HAVE_ATTRIBUTE_ALIAS,
turn overload with finalizer into alias to ggc_internal_alloc_ and
rename it to ...
(ggc_internal_cleared_alloc_): ... this, make it extern "C".
(ggc_internal_cleared_alloc_no_dtor): New alias if
HAVE_ATTRIBUTE_ALIAS, otherwise new noinline wrapper.
* ggc-none.cc (ggc_internal_alloc): If HAVE_ATTRIBUTE_ALIAS, turn
overload with finalizer into alias to ggc_internal_alloc_ and
rename it to ...
(ggc_internal_alloc_): ... this, make it extern "C".
(ggc_internal_alloc_no_dtor): New alias if HAVE_ATTRIBUTE_ALIAS,
otherwise new wrapper.
(ggc_internal_cleared_alloc): If HAVE_ATTRIBUTE_ALIAS, turn overload
with finalizer into alias to ggc_internal_alloc_ and rename it to ...
(ggc_internal_cleared_alloc_): ... this, make it extern "C".
(ggc_internal_cleared_alloc_no_dtor): New alias if
HAVE_ATTRIBUTE_ALIAS, otherwise new wrapper.
* genmatch.cc (ggc_internal_cleared_alloc, ggc_free): Formatting fix.
(ggc_internal_cleared_alloc_no_dtor): Define.
* config.in: Regenerate.
* configure: Regenerate.
2025-03-01 Jakub Jelinek <jakub@redhat.com>
PR middle-end/115871
* omp-simd-clone.cc (simd_clone_adjust): For SIMD_CLONE_ARG_TYPE_MASK
and sc->mask_mode not VOIDmode, set elem_type to the characteristic
type rather than boolean_type_node.
2025-03-01 Jan Dubiec <jdx@o2.pl>
PR target/109189
* config/h8300/h8300.cc (h8300_print_operand): Replace %ld format
strings with HOST_WIDE_INT_PRINT_DEC macro in order to silence
-Wformat warnings when building on Windows/MinGW64.
2025-02-28 Martin Jambor <mjambor@suse.cz>
PR ipa/118243
* ipa-sra.cc (pull_accesses_from_callee): New parameters
caller_ipcp_ts and param_idx. Check that scalar pulled accesses would
not clash with a known IPA-CP aggregate constant.
(param_splitting_across_edge): Pass IPA-CP transformation summary and
caller parameter index to pull_accesses_from_callee.
2025-02-28 Richard Biener <rguenther@suse.de>
PR ipa/111245
* ipa-modref.cc (modref_access_analysis::analyze_store): Do
not guard the check of whether the stmt could throw by
cfun->can_throw_non_call_exceptions.
2025-02-28 Jakub Jelinek <jakub@redhat.com>
PR rtl-optimization/117712
* expr.cc (force_operand): Handle {,UNSIGNED_}FIX with
FIX operand using expand_fix on the inner FIX operand.
2025-02-28 Richard Biener <rguenther@suse.de>
PR tree-optimization/87984
* tree-ssa-dom.cc (dom_opt_dom_walker::optimize_stmt): Do
not perform redundant store elimination to hard register
variables.
* tree-ssa-sccvn.cc (eliminate_dom_walker::eliminate_stmt):
Likewise.
2025-02-28 Richard Biener <rguenther@suse.de>
PR middle-end/66279
* gimplify.cc (gimplify_asm_expr): Copy TREE_PURPOSE before
rewriting it for "+" processing.
2025-02-28 H.J. Lu <hjl.tools@gmail.com>
* config/i386/i386.h (TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P):
Moved to ...
* config/i386/i386.cc (TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P):
Here.
2025-02-27 Pan Li <pan2.li@intel.com>
PR target/118931
* config/riscv/riscv-v.cc (expand_const_vector): Add overflow to
smode check and clean up highest bits if overflow.
2025-02-27 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/119030
* gimple-fold.cc (fold_truth_andor_for_ifcombine): Fix a pasto,
ll_unsignedp -> rl_unsignedp.
2025-02-27 Jakub Jelinek <jakub@redhat.com>
PR middle-end/118860
* input.h (file_cache::tune): No longer static. Rename argument
from num_file_slots_ to num_file_slots. Formatting fix.
(file_cache::num_file_slots): Renamed to ...
(file_cache::m_num_file_slots): ... this. No longer static.
* input.cc (file_cache_slot::tune): Change return type from void to
size_t, return previous file_cache_slot::line_record_size value.
Formatting fixes.
(file_cache::tune): Rename argument from num_file_slots_ to
num_file_slots. Set m_num_file_slots rather than num_file_slots.
If m_num_file_slots or file_cache_slot::line_record_size changes,
delete[] m_file_slots and new it again.
(file_cache::num_file_slots): Remove definition.
(file_cache::lookup_file): Use m_num_file_slots rather than
num_file_slots.
(file_cache::evicted_cache_tab_entry): Likewise.
(file_cache::file_cache): Likewise. Initialize m_num_file_slots
to 16.
(file_cache::dump): Use m_num_file_slots rather than num_file_slots.
(file_cache_slot::get_next_line): Formatting fixes.
(file_cache_slot::read_line_num): Likewise.
(get_source_text_between): Likewise.
* toplev.cc (toplev::main): Call global_dc->get_file_cache ().tune
rather than file_cache::tune.
2025-02-27 Thomas Schwinge <tschwinge@baylibre.com>
* config/nvptx/nvptx.h (MAX_FIXED_MODE_SIZE): '#define'.
2025-02-27 Thomas Schwinge <tschwinge@baylibre.com>
* config/nvptx/nvptx.opt (-mfake-ptx-alloca): New.
* config/nvptx/nvptx-protos.h (nvptx_output_fake_ptx_alloca):
Declare.
* config/nvptx/nvptx.cc (nvptx_output_fake_ptx_alloca): New.
* config/nvptx/nvptx.md (define_insn "@nvptx_alloca_<mode>")
[!(TARGET_PTX_7_3 && TARGET_SM52)]: Use it for
'-mfake-ptx-alloca'.
2025-02-27 Thomas Schwinge <tschwinge@baylibre.com>
* config/nvptx/nvptx.md (define_expand "allocate_stack")
[!TARGET_SOFT_STACK]: Move
'sorry ("dynamic stack allocation not supported");'...
(define_insn "@nvptx_alloca_<mode>"): ... here.
2025-02-27 Jerry DeLisle <jvdelisle@gcc.gnu.org>
PR fortran/108369
* doc/invoke.texi: Add a note to clarify. Adjust some wording.
2025-02-27 Haochen Jiang <haochen.jiang@intel.com>
* config/i386/x86-tune.def
(X86_TUNE_DEST_FALSE_DEP_FOR_GLC): Add GNR, GNR-D, DMR.
(X86_TUNE_AVOID_256FMA_CHAINS): Ditto.
(X86_TUNE_AVX512_MOVE_BY_PIECES): Ditto.
(X86_TUNE_AVX512_STORE_BY_PIECES): Ditto.
2025-02-27 Jakub Jelinek <jakub@redhat.com>
* gimple-range-phi.cc (phi_analyzer::process_phi): Fix comment typo,
dpoesn;t -> doesn't.
2025-02-27 Jakub Jelinek <jakub@redhat.com>
PR testsuite/116143
* Makefile.in (EXTRA_BACKEND_OBJS): New variable.
(BACKEND): Use it before libbackend.a.
2025-02-27 Jakub Jelinek <jakub@redhat.com>
PR middle-end/118819
* alias.cc (memrefs_conflict_p): Perform arithmetics on c, xsize and
ysize in poly_offset_int and return -1 if it is not representable in
poly_int64.
2025-02-26 Jakub Jelinek <jakub@redhat.com>
PR c/119001
* varasm.cc (output_constructor_regular_field): Don't fail
assertion if next is non-NULL and FIELD_DECL if
TREE_CODE (local->type) is UNION_TYPE.
2025-02-26 Jakub Jelinek <jakub@redhat.com>
PR c/114870
* ginclude/stddef.h (__STDC_VERSION_STDDEF_H__, unreachable): Don't
redefine multiple times if stddef.h is first included without __need_*
defines and later with them. Move nullptr_t and unreachable and
__STDC_VERSION_STDDEF_H__ definitions into the same
defined (__STDC_VERSION__) && __STDC_VERSION__ > 201710L #if block.
2025-02-26 Jakub Jelinek <jakub@redhat.com>
PR rtl-optimization/119002
* config/arm/arm.h (REVERSE_CONDITION): Use CODE - the macro
argument - in the macro rather than code.
2025-02-26 Vladimir N. Makarov <vmakarov@redhat.com>
PR middle-end/119021
* lra.cc (lra_asm_insn_error): Use lra_invalidate_insn_data
instead of lra_update_insn_regno_info.
* lra-assigns.cc (lra_split_hard_reg_for): Restore old code.
2025-02-26 Alexandre Oliva <oliva@adacore.com>
* doc/sourcebuild.texi: Add x86 effective target.
2025-02-26 Alexandre Oliva <oliva@adacore.com>
* doc/sourcebuild.texi (dg-do-if): Document.
2025-02-26 Jakub Jelinek <jakub@redhat.com>
PR testsuite/116143
* simple-diagnostic-path.h (simple_diagnostic_path::num_events): Define
inline.
(simple_diagnostic_path::num_threads): Likewise.
* simple-diagnostic-path.cc (simple_diagnostic_path::num_events):
Remove out of line definition.
(simple_diagnostic_path::num_threads): Likewise.
2025-02-25 Jason Merrill <jason@redhat.com>
* doc/install.texi: 10.5 won't bootstrap with C++98.
2025-02-25 Vladimir N. Makarov <vmakarov@redhat.com>
PR target/115458
* lra-int.h (LRA_MAX_FAILED_SPLITS): Define and check its value.
(lra_split_hard_reg_for): Change prototype.
* lra.cc (lra): Try to split hard reg range several times after a
failure.
* lra-assigns.cc (lra_split_hard_reg_for): Add an arg, a flag of
giving up. Report asm error and nullify the asm insn depending on
the arg value.
2025-02-25 Jakub Jelinek <jakub@redhat.com>
PR translation/118991
* config/pru/pru-pragma.cc (pru_pragma_ctable_entry): Use %wd
instead of %" HOST_WIDE_INT_PRINT "d to print a hwi in error.
2025-02-25 Iain Buclaw <ibuclaw@gdcproject.org>
PR d/118654
* config/i386/i386-d.cc (ix86_d_target_versions): Predefine GNU_CET.
(ix86_d_handle_target_cf_protection): New.
(ix86_d_register_target_info): Add 'CET' TargetInfo key.
2025-02-24 Robin Dapp <rdapp@ventanamicro.com>
PR target/114516
* config/riscv/riscv-vector-costs.cc (compute_estimated_lmul):
Add pattern statements to program points.
2025-02-24 Robin Dapp <rdapp@ventanamicro.com>
PR middle-end/118950
* tree-vect-patterns.cc (vect_recog_gather_scatter_pattern): Use
original LHS's type.
2025-02-24 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/118915
* tree-ssa-reassoc.cc (optimize_range_tests_to_bit_test): For
highj == NULL_TREE use TYPE_MAX_VALUE (TREE_TYPE (lowj)) rather
than TYPE_MAX_VALUE (type).
2025-02-24 Richard Biener <rguenther@suse.de>
PR tree-optimization/118973
* tree-ssa-dce.cc (mark_stmt_if_obviously_necessary): Calls
that alter control flow in unpredictable ways need to be
preserved.
2025-02-24 Jakub Jelinek <jakub@redhat.com>
PR middle-end/118993
* gimplify.cc (gimplify_scan_omp_clauses): Fix diagnostics typo,
undfined -> undefined.
2025-02-24 Jakub Jelinek <jakub@redhat.com>
PR c/117023
* builtin-attrs.def (ATTR_NONNULL_IF_NONZERO): New DEF_ATTR_IDENT.
(ATTR_NOTHROW_NONNULL_IF12_LEAF, ATTR_NOTHROW_NONNULL_IF13_LEAF,
ATTR_NOTHROW_NONNULL_IF123_LEAF, ATTR_NOTHROW_NONNULL_IF23_LEAF,
ATTR_NOTHROW_NONNULL_1_IF23_LEAF, ATTR_PURE_NOTHROW_NONNULL_IF12_LEAF,
ATTR_PURE_NOTHROW_NONNULL_IF13_LEAF,
ATTR_PURE_NOTHROW_NONNULL_IF123_LEAF,
ATTR_WARN_UNUSED_RESULT_NOTHROW_NONNULL_IF12_LEAF,
ATTR_MALLOC_WARN_UNUSED_RESULT_NOTHROW_NONNULL_IF12_LEAF): New
DEF_ATTR_TREE_LIST.
* builtins.def (BUILT_IN_STRNDUP): Use
ATTR_MALLOC_WARN_UNUSED_RESULT_NOTHROW_NONNULL_IF12_LEAF instead of
ATTR_MALLOC_WARN_UNUSED_RESULT_NOTHROW_NONNULL_LEAF.
(BUILT_IN_STRNCAT, BUILT_IN_STRNCAT_CHK): Use
ATTR_NOTHROW_NONNULL_1_IF23_LEAF instead of ATTR_NOTHROW_NONNULL_LEAF.
(BUILT_IN_BCOPY, BUILT_IN_MEMCPY, BUILT_IN_MEMCPY_CHK,
BUILT_IN_MEMMOVE, BUILT_IN_MEMMOVE_CHK, BUILT_IN_STRNCPY,
BUILT_IN_STRNCPY_CHK): Use ATTR_NOTHROW_NONNULL_IF123_LEAF instead of
ATTR_NOTHROW_NONNULL_LEAF.
(BUILT_IN_MEMPCPY, BUILT_IN_MEMPCPY_CHK, BUILT_IN_STPNCPY,
BUILT_IN_STPNCPY_CHK): Use ATTR_NOTHROW_NONNULL_IF123_LEAF instead of
ATTR_RETNONNULL_NOTHROW_LEAF.
(BUILT_IN_BZERO, BUILT_IN_MEMSET, BUILT_IN_MEMSET_CHK): Use
ATTR_NOTHROW_NONNULL_IF13_LEAF instead of ATTR_NOTHROW_NONNULL_LEAF.
(BUILT_IN_BCMP, BUILT_IN_MEMCMP, BUILT_IN_STRNCASECMP,
BUILT_IN_STRNCMP): Use ATTR_PURE_NOTHROW_NONNULL_IF123_LEAF instead of
ATTR_PURE_NOTHROW_NONNULL_LEAF.
(BUILT_IN_STRNLEN): Use ATTR_PURE_NOTHROW_NONNULL_IF12_LEAF instead of
ATTR_PURE_NOTHROW_NONNULL_LEAF.
(BUILT_IN_MEMCHR): Use ATTR_PURE_NOTHROW_NONNULL_IF13_LEAF instead of
ATTR_PURE_NOTHROW_NONNULL_LEAF.
2025-02-24 Lino Hsing-Yu Peng <linopeng@andestech.com>
* config/riscv/riscv.cc: Set multi push regs bits.
2025-02-22 Thomas Schwinge <tschwinge@baylibre.com>
* config/bpf/bpf.md (define_expand "allocate_stack"): Emit
'sorry, unimplemented: dynamic stack allocation not supported'.
* config/nvptx/nvptx.md (define_expand "allocate_stack")
[!TARGET_SOFT_STACK && !(TARGET_PTX_7_3 && TARGET_SM52)]: Likewise.
2025-02-21 H.J. Lu <hjl.tools@gmail.com>
* sese.cc (debug_edge): Append a newline.
2025-02-21 Richard Biener <rguenther@suse.de>
PR tree-optimization/118954
* tree-predcom.cc (ref_at_iteration): Make sure to not
associate the constant offset with DR_BASE_ADDRESS when
that is an offsetted pointer.
2025-02-20 David Malcolm <dmalcolm@redhat.com>
* diagnostic-core.h: Add comments making clear that these
functions implicitly use global_dc.
2025-02-20 David Malcolm <dmalcolm@redhat.com>
* libsarifreplay.cc
(sarif_replayer::make_plain_text_within_result_message): Capture
which json::string was used. When reporting on unescaped "{" or
"}" in SARIF message strings, use that string rather than the
message object, and refer the user to §3.11.5 ("Messages with
placeholders") rather than §3.11.11 ("arguments"). Ideally we'd
place the error at the precise character, but that can't be done
without reworking json-parsing.cc's lexer::lex_string, which is
too invasive for stage 4.
(sarif_replayer::get_plain_text_from_mfms): Capture which
json::string was used.
(sarif_replayer::lookup_plain_text_within_result_message):
Likewise.
2025-02-20 Gerald Pfeifer <gerald@pfeifer.com>
PR target/69374
* doc/install.texi (Specific, aarch64*-*-*): Drop note for
Binutils pre 2.24.
2025-02-20 Richard Sandiford <richard.sandiford@arm.com>
* config/aarch64/aarch64-protos.h (aarch64_expand_sve_vec_cmp_float):
Remove can_invert_p argument and change return type to void.
* config/aarch64/aarch64.cc (aarch64_expand_sve_vec_cmp_float):
Likewise.
* config/aarch64/aarch64-sve.md (vec_cmp<mode><vpred>): Update call
accordingly.
2025-02-20 Richard Biener <rguenther@suse.de>
PR tree-optimization/118521
* tree-scalar-evolution.cc (final_value_replacement_loop):
Fold uses of the replaced PHI def.
2025-02-20 Filip Kastl <fkastl@suse.cz>
* doc/invoke.texi: Fix typo file-cache-files ->
file-cache-lines.
2025-02-20 Richard Biener <rguenther@suse.de>
PR tree-optimization/86270
* tree-outof-ssa.cc (insert_backedge_copies): Pattern
match a single conflict in a loop condition and adjust
that avoiding the conflict if possible.
2025-02-20 H.J. Lu <hjl.tools@gmail.com>
Revert:
2025-02-16 H.J. Lu <hjl.tools@gmail.com>
PR target/109780
PR target/109093
* config/i386/i386.cc (ix86_update_stack_alignment): New.
(ix86_find_all_reg_use_1): Likewise.
(ix86_find_all_reg_use): Likewise.
(ix86_find_max_used_stack_alignment): Also check memory accesses
from registers defined by stack or frame registers.
2025-02-20 H.J. Lu <hjl.tools@gmail.com>
Revert:
2025-02-17 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.cc (ix86_find_all_reg_use):
Scan only for SET RTX in PARALLEL.
2025-02-19 David Malcolm <dmalcolm@redhat.com>
PR other/118919
* input.cc (file_cache_slot::m_file_path): Make non-const.
(file_cache_slot::evict): Free m_file_path.
(file_cache_slot::create): Store a copy of file_path if non-null.
(file_cache_slot::~file_cache_slot): Free m_file_path.
2025-02-19 Pan Li <pan2.li@intel.com>
PR middle-end/116351
* tree-vect-loop.cc (vect_verify_loop_lens): Return false if the
loop_vinfo has relevant mode such as DImode.
2025-02-19 Xi Ruoyao <xry111@xry111.site>
* config/loongarch/lasx.md (UNSPEC_LASX_XVSRARI): Remove.
(UNSPEC_LASX_XVSRLRI): Remove.
(lasx_xvsrari_<lsxfmt>): Remove.
(lasx_xvsrlri_<lsxfmt>): Remove.
* config/loongarch/lsx.md (UNSPEC_LSX_VSRARI): Remove.
(UNSPEC_LSX_VSRLRI): Remove.
(lsx_vsrari_<lsxfmt>): Remove.
(lsx_vsrlri_<lsxfmt>): Remove.
* config/loongarch/simd.md (simd_<optab>_imm_round_<mode>): New
define_insn.
(<simd_isa>_<x>v<insn>ri_<simdfmt>): New define_expand.
2025-02-19 Xi Ruoyao <xry111@xry111.site>
* config/loongarch/simd.md (wvec_half): New define_mode_attr.
(<su>dot_prod<wvec_half><mode>): New define_expand.
2025-02-19 Xi Ruoyao <xry111@xry111.site>
* config/loongarch/simd.md (even_odd): New define_int_attr.
(vec_widen_<su>mult_<even_odd>_<mode>): New define_expand.
2025-02-19 Xi Ruoyao <xry111@xry111.site>
* config/loongarch/simd.md (LVEC): New define_mode_attr.
(simdfmt_as_i): Make it same as simdfmt for integer vector
modes.
(_f): New define_mode_attr.
* config/loongarch/lsx.md (lsx_vpickev_b): Remove.
(lsx_vpickev_h): Remove.
(lsx_vpickev_w): Remove.
(lsx_vpickev_w_f): Remove.
(lsx_vpickod_b): Remove.
(lsx_vpickod_h): Remove.
(lsx_vpickod_w): Remove.
(lsx_vpickev_w_f): Remove.
(lsx_pick_evod_<mode>): New define_insn.
(lsx_<x>vpick<ev_od>_<simdfmt_as_i><_f>): New
define_expand.
2025-02-19 Xi Ruoyao <xry111@xry111.site>
* config/loongarch/lasx.md (UNSPEC_LASX_XVMADDWEV): Remove.
(UNSPEC_LASX_XVMADDWEV2): Remove.
(UNSPEC_LASX_XVMADDWEV3): Remove.
(UNSPEC_LASX_XVMADDWOD): Remove.
(UNSPEC_LASX_XVMADDWOD2): Remove.
(UNSPEC_LASX_XVMADDWOD3): Remove.
(lasx_xvmaddwev_h_b<u>): Remove.
(lasx_xvmaddwev_w_h<u>): Remove.
(lasx_xvmaddwev_d_w<u>): Remove.
(lasx_xvmaddwev_q_d): Remove.
(lasx_xvmaddwod_h_b<u>): Remove.
(lasx_xvmaddwod_w_h<u>): Remove.
(lasx_xvmaddwod_d_w<u>): Remove.
(lasx_xvmaddwod_q_d): Remove.
(lasx_xvmaddwev_q_du): Remove.
(lasx_xvmaddwod_q_du): Remove.
(lasx_xvmaddwev_h_bu_b): Remove.
(lasx_xvmaddwev_w_hu_h): Remove.
(lasx_xvmaddwev_d_wu_w): Remove.
(lasx_xvmaddwev_q_du_d): Remove.
(lasx_xvmaddwod_h_bu_b): Remove.
(lasx_xvmaddwod_w_hu_h): Remove.
(lasx_xvmaddwod_d_wu_w): Remove.
(lasx_xvmaddwod_q_du_d): Remove.
* config/loongarch/lsx.md (UNSPEC_LSX_VMADDWEV): Remove.
(UNSPEC_LSX_VMADDWEV2): Remove.
(UNSPEC_LSX_VMADDWEV3): Remove.
(UNSPEC_LSX_VMADDWOD): Remove.
(UNSPEC_LSX_VMADDWOD2): Remove.
(UNSPEC_LSX_VMADDWOD3): Remove.
(lsx_vmaddwev_h_b<u>): Remove.
(lsx_vmaddwev_w_h<u>): Remove.
(lsx_vmaddwev_d_w<u>): Remove.
(lsx_vmaddwev_q_d): Remove.
(lsx_vmaddwod_h_b<u>): Remove.
(lsx_vmaddwod_w_h<u>): Remove.
(lsx_vmaddwod_d_w<u>): Remove.
(lsx_vmaddwod_q_d): Remove.
(lsx_vmaddwev_q_du): Remove.
(lsx_vmaddwod_q_du): Remove.
(lsx_vmaddwev_h_bu_b): Remove.
(lsx_vmaddwev_w_hu_h): Remove.
(lsx_vmaddwev_d_wu_w): Remove.
(lsx_vmaddwev_q_du_d): Remove.
(lsx_vmaddwod_h_bu_b): Remove.
(lsx_vmaddwod_w_hu_h): Remove.
(lsx_vmaddwod_d_wu_w): Remove.
(lsx_vmaddwod_q_du_d): Remove.
* config/loongarch/simd.md (simd_maddw_evod_<mode>_<su>):
New define_insn.
(<simd_isa>_<x>vmaddw<ev_od>_<simdfmt_w>_<simdfmt><u>): New
define_expand.
(simd_maddw_evod_<mode>_hetero): New define_insn.
(<simd_isa>_<x>vmaddw<ev_od>_<simdfmt_w>_<simdfmt>u_<simdfmt>):
New define_expand.
(<simd_isa>_maddw<ev_od>_q_d<u>_punned): New define_expand.
(<simd_isa>_maddw<ev_od>_q_du_d_punned): New define_expand.
* config/loongarch/loongarch-builtins.cc
(CODE_FOR_lsx_vmaddwev_q_d): Define as a macro to override it
with the punned expand.
(CODE_FOR_lsx_vmaddwev_q_du): Likewise.
(CODE_FOR_lsx_vmaddwev_q_du_d): Likewise.
(CODE_FOR_lsx_vmaddwod_q_d): Likewise.
(CODE_FOR_lsx_vmaddwod_q_du): Likewise.
(CODE_FOR_lsx_vmaddwod_q_du_d): Likewise.
(CODE_FOR_lasx_xvmaddwev_q_d): Likewise.
(CODE_FOR_lasx_xvmaddwev_q_du): Likewise.
(CODE_FOR_lasx_xvmaddwev_q_du_d): Likewise.
(CODE_FOR_lasx_xvmaddwod_q_d): Likewise.
(CODE_FOR_lasx_xvmaddwod_q_du): Likewise.
(CODE_FOR_lasx_xvmaddwod_q_du_d): Likewise.
2025-02-19 Xi Ruoyao <xry111@xry111.site>
* config/loongarch/lasx.md (UNSPEC_LASX_XVHADDW_Q_D): Remove.
(UNSPEC_LASX_XVHSUBW_Q_D): Remove.
(UNSPEC_LASX_XVHADDW_QU_DU): Remove.
(UNSPEC_LASX_XVHSUBW_QU_DU): Remove.
(lasx_xvh<addsub:optab>w_h<u>_b<u>): Remove.
(lasx_xvh<addsub:optab>w_w<u>_h<u>): Remove.
(lasx_xvh<addsub:optab>w_d<u>_w<u>): Remove.
(lasx_xvhaddw_q_d): Remove.
(lasx_xvhsubw_q_d): Remove.
(lasx_xvhaddw_qu_du): Remove.
(lasx_xvhsubw_qu_du): Remove.
(reduc_plus_scal_v4di): Call gen_lasx_haddw_q_d_punned instead
of gen_lasx_xvhaddw_q_d.
(reduc_plus_scal_v8si): Likewise.
* config/loongarch/lsx.md (UNSPEC_LSX_VHADDW_Q_D): Remove.
(UNSPEC_ASX_VHSUBW_Q_D): Remove.
(UNSPEC_ASX_VHADDW_QU_DU): Remove.
(UNSPEC_ASX_VHSUBW_QU_DU): Remove.
(lsx_vh<addsub:optab>w_h<u>_b<u>): Remove.
(lsx_vh<addsub:optab>w_w<u>_h<u>): Remove.
(lsx_vh<addsub:optab>w_d<u>_w<u>): Remove.
(lsx_vhaddw_q_d): Remove.
(lsx_vhsubw_q_d): Remove.
(lsx_vhaddw_qu_du): Remove.
(lsx_vhsubw_qu_du): Remove.
(reduc_plus_scal_v2di): Change the temporary register mode to
V1TI, and pun the mode calling gen_vec_extractv2didi.
(reduc_plus_scal_v4si): Change the temporary register mode to
V1TI.
* config/loongarch/simd.md (simd_h<optab>w_<mode>_<su>): New
define_insn.
(<simd_isa>_<x>vh<optab>w_<simdfmt_w><u>_<simdfmt><u>): New
define_expand.
(<simd_isa>_h<optab>w_q<u>_d<u>_punned): New define_expand.
* config/loongarch/loongarch-builtins.cc
(CODE_FOR_lsx_vhaddw_q_d): Define as a macro to override with
punned expand.
(CODE_FOR_lsx_vhaddw_qu_du): Likewise.
(CODE_FOR_lsx_vhsubw_q_d): Likewise.
(CODE_FOR_lsx_vhsubw_qu_du): Likewise.
(CODE_FOR_lasx_xvhaddw_q_d): Likewise.
(CODE_FOR_lasx_xvhaddw_qu_du): Likewise.
(CODE_FOR_lasx_xvhsubw_q_d): Likewise.
(CODE_FOR_lasx_xvhsubw_qu_du): Likewise.
2025-02-19 Xi Ruoyao <xry111@xry111.site>
* config/loongarch/lasx.md (UNSPEC_LASX_XVADDWEV): Remove.
(UNSPEC_LASX_XVADDWEV2): Remove.
(UNSPEC_LASX_XVADDWEV3): Remove.
(UNSPEC_LASX_XVSUBWEV): Remove.
(UNSPEC_LASX_XVSUBWEV2): Remove.
(UNSPEC_LASX_XVMULWEV): Remove.
(UNSPEC_LASX_XVMULWEV2): Remove.
(UNSPEC_LASX_XVMULWEV3): Remove.
(UNSPEC_LASX_XVADDWOD): Remove.
(UNSPEC_LASX_XVADDWOD2): Remove.
(UNSPEC_LASX_XVADDWOD3): Remove.
(UNSPEC_LASX_XVSUBWOD): Remove.
(UNSPEC_LASX_XVSUBWOD2): Remove.
(UNSPEC_LASX_XVMULWOD): Remove.
(UNSPEC_LASX_XVMULWOD2): Remove.
(UNSPEC_LASX_XVMULWOD3): Remove.
(lasx_xv<addsubmul:optab>wev_h_b<u>): Remove.
(lasx_xv<addsubmul:optab>wev_w_h<u>): Remove.
(lasx_xv<addsubmul:optab>wev_d_w<u>): Remove.
(lasx_xvaddwev_q_d): Remove.
(lasx_xvsubwev_q_d): Remove.
(lasx_xvmulwev_q_d): Remove.
(lasx_xv<addsubmul:optab>wod_h_b<u>): Remove.
(lasx_xv<addsubmul:optab>wod_w_h<u>): Remove.
(lasx_xv<addsubmul:optab>wod_d_w<u>): Remove.
(lasx_xvaddwod_q_d): Remove.
(lasx_xvsubwod_q_d): Remove.
(lasx_xvmulwod_q_d): Remove.
(lasx_xvaddwev_q_du): Remove.
(lasx_xvsubwev_q_du): Remove.
(lasx_xvmulwev_q_du): Remove.
(lasx_xvaddwod_q_du): Remove.
(lasx_xvsubwod_q_du): Remove.
(lasx_xvmulwod_q_du): Remove.
(lasx_xv<addmul:optab>wev_h_bu_b): Remove.
(lasx_xv<addmul:optab>wev_w_hu_h): Remove.
(lasx_xv<addmul:optab>wev_d_wu_w): Remove.
(lasx_xv<addmul:optab>wod_h_bu_b): Remove.
(lasx_xv<addmul:optab>wod_w_hu_h): Remove.
(lasx_xv<addmul:optab>wod_d_wu_w): Remove.
(lasx_xvaddwev_q_du_d): Remove.
(lasx_xvsubwev_q_du_d): Remove.
(lasx_xvmulwev_q_du_d): Remove.
(lasx_xvaddwod_q_du_d): Remove.
(lasx_xvsubwod_q_du_d): Remove.
* config/loongarch/lsx.md (UNSPEC_LSX_XVADDWEV): Remove.
(UNSPEC_LSX_VADDWEV2): Remove.
(UNSPEC_LSX_VADDWEV3): Remove.
(UNSPEC_LSX_VSUBWEV): Remove.
(UNSPEC_LSX_VSUBWEV2): Remove.
(UNSPEC_LSX_VMULWEV): Remove.
(UNSPEC_LSX_VMULWEV2): Remove.
(UNSPEC_LSX_VMULWEV3): Remove.
(UNSPEC_LSX_VADDWOD): Remove.
(UNSPEC_LSX_VADDWOD2): Remove.
(UNSPEC_LSX_VADDWOD3): Remove.
(UNSPEC_LSX_VSUBWOD): Remove.
(UNSPEC_LSX_VSUBWOD2): Remove.
(UNSPEC_LSX_VMULWOD): Remove.
(UNSPEC_LSX_VMULWOD2): Remove.
(UNSPEC_LSX_VMULWOD3): Remove.
(lsx_v<addsubmul:optab>wev_h_b<u>): Remove.
(lsx_v<addsubmul:optab>wev_w_h<u>): Remove.
(lsx_v<addsubmul:optab>wev_d_w<u>): Remove.
(lsx_vaddwev_q_d): Remove.
(lsx_vsubwev_q_d): Remove.
(lsx_vmulwev_q_d): Remove.
(lsx_v<addsubmul:optab>wod_h_b<u>): Remove.
(lsx_v<addsubmul:optab>wod_w_h<u>): Remove.
(lsx_v<addsubmul:optab>wod_d_w<u>): Remove.
(lsx_vaddwod_q_d): Remove.
(lsx_vsubwod_q_d): Remove.
(lsx_vmulwod_q_d): Remove.
(lsx_vaddwev_q_du): Remove.
(lsx_vsubwev_q_du): Remove.
(lsx_vmulwev_q_du): Remove.
(lsx_vaddwod_q_du): Remove.
(lsx_vsubwod_q_du): Remove.
(lsx_vmulwod_q_du): Remove.
(lsx_v<addmul:optab>wev_h_bu_b): Remove.
(lsx_v<addmul:optab>wev_w_hu_h): Remove.
(lsx_v<addmul:optab>wev_d_wu_w): Remove.
(lsx_v<addmul:optab>wod_h_bu_b): Remove.
(lsx_v<addmul:optab>wod_w_hu_h): Remove.
(lsx_v<addmul:optab>wod_d_wu_w): Remove.
(lsx_vaddwev_q_du_d): Remove.
(lsx_vsubwev_q_du_d): Remove.
(lsx_vmulwev_q_du_d): Remove.
(lsx_vaddwod_q_du_d): Remove.
(lsx_vsubwod_q_du_d): Remove.
(lsx_vmulwod_q_du_d): Remove.
* config/loongarch/loongarch-modes.def: Add V4TI and V1DI.
* config/loongarch/loongarch-protos.h
(loongarch_gen_stepped_int_parallel): New function prototype.
* config/loongarch/loongarch.cc (loongarch_print_operand):
Accept 'O' for printing "ev" or "od."
(loongarch_gen_stepped_int_parallel): Implement.
* config/loongarch/predicates.md
(vect_par_cnst_even_or_odd_half): New define_predicate.
* config/loongarch/simd.md (WVEC_HALF): New define_mode_attr.
(simdfmt_w): Likewise.
(zero_one): New define_int_iterator.
(ev_od): New define_int_attr.
(simd_<optab>w_evod_<mode:IVEC>_<su>): New define_insn.
(<simd_isa>_<x>v<optab>w<ev_od>_<simdfmt_w>_<simdfmt><u>): New
define_expand.
(simd_<optab>w_evod_<mode>_hetero): New define_insn.
(<simd_isa>_<x>v<optab>w<ev_od>_<simdfmt_w>_<simdfmt>u_<simdfmt>):
New define_expand.
(DIVEC): New define_mode_iterator.
(<simd_isa>_<optab>w<ev_od>_q_d<u>_punned): New define_expand.
(<simd_isa>_<optab>w<ev_od>_q_du_d_punned): Likewise.
* config/loongarch/loongarch-builtins.cc
(CODE_FOR_lsx_vaddwev_q_d): Define as a macro to override it
with the punned expand.
(CODE_FOR_lsx_vaddwev_q_du): Likewise.
(CODE_FOR_lsx_vsubwev_q_d): Likewise.
(CODE_FOR_lsx_vsubwev_q_du): Likewise.
(CODE_FOR_lsx_vmulwev_q_d): Likewise.
(CODE_FOR_lsx_vmulwev_q_du): Likewise.
(CODE_FOR_lsx_vaddwod_q_d): Likewise.
(CODE_FOR_lsx_vaddwod_q_du): Likewise.
(CODE_FOR_lsx_vsubwod_q_d): Likewise.
(CODE_FOR_lsx_vsubwod_q_du): Likewise.
(CODE_FOR_lsx_vmulwod_q_d): Likewise.
(CODE_FOR_lsx_vmulwod_q_du): Likewise.
(CODE_FOR_lsx_vaddwev_q_du_d): Likewise.
(CODE_FOR_lsx_vmulwev_q_du_d): Likewise.
(CODE_FOR_lsx_vaddwod_q_du_d): Likewise.
(CODE_FOR_lsx_vmulwod_q_du_d): Likewise.
(CODE_FOR_lasx_xvaddwev_q_d): Likewise.
(CODE_FOR_lasx_xvaddwev_q_du): Likewise.
(CODE_FOR_lasx_xvsubwev_q_d): Likewise.
(CODE_FOR_lasx_xvsubwev_q_du): Likewise.
(CODE_FOR_lasx_xvmulwev_q_d): Likewise.
(CODE_FOR_lasx_xvmulwev_q_du): Likewise.
(CODE_FOR_lasx_xvaddwod_q_d): Likewise.
(CODE_FOR_lasx_xvaddwod_q_du): Likewise.
(CODE_FOR_lasx_xvsubwod_q_d): Likewise.
(CODE_FOR_lasx_xvsubwod_q_du): Likewise.
(CODE_FOR_lasx_xvmulwod_q_d): Likewise.
(CODE_FOR_lasx_xvmulwod_q_du): Likewise.
(CODE_FOR_lasx_xvaddwev_q_du_d): Likewise.
(CODE_FOR_lasx_xvmulwev_q_du_d): Likewise.
(CODE_FOR_lasx_xvaddwod_q_du_d): Likewise.
(CODE_FOR_lasx_xvmulwod_q_du_d): Likewise.
2025-02-19 Xi Ruoyao <xry111@xry111.site>
* config/loongarch/lsx.md (mov<LSX:mode>): Remove.
(movmisalign<LSX:mode>): Remove.
(mov<LSX:mode>_lsx): Remove.
* config/loongarch/lasx.md (mov<LASX:mode>): Remove.
(movmisalign<LASX:mode>): Remove.
(mov<LASX:mode>_lasx): Remove.
* config/loongarch/loongarch-modes.def (V1TI): Add.
(V2TI): Mention in the comment.
* config/loongarch/loongarch.md (mode): Add V1TI and V2TI.
* config/loongarch/simd.md (ALLVEC_TI): New mode iterator.
(mov<ALLVEC_TI:mode): New define_expand.
(movmisalign<ALLVEC_TI:mode>): Likewise.
(mov<ALLVEC_TI:mode>_simd): New define_insn_and_split.
2025-02-19 Xi Ruoyao <xry111@xry111.site>
* config/loongarch/loongarch-protos.h
(loongarch_const_vector_vrepli): New function prototype.
* config/loongarch/loongarch.cc (loongarch_const_vector_vrepli):
Implement.
(loongarch_const_insns): Call loongarch_const_vector_vrepli
instead of loongarch_const_vector_same_int_p.
(loongarch_split_vector_move_p): Likewise.
(loongarch_output_move): Use loongarch_const_vector_vrepli to
pun operend[1] into a better mode if it's a const int vector,
and decide the suffix of [x]vrepli with the new mode.
* config/loongarch/constraints.md (YI): Call
loongarch_const_vector_vrepli instead of
loongarch_const_vector_same_int_p.
2025-02-19 Xi Ruoyao <xry111@xry111.site>
PR target/115478
* config/loongarch/loongarch.md (any_or_plus): New
define_code_iterator.
(bstrins_<mode>_for_ior_mask): Use any_or_plus instead of ior.
(bytepick_w_<bytepick_imm>): Likewise.
(bytepick_d_<bytepick_imm>): Likewise.
(bytepick_d_<bytepick_imm>_rev): Likewise.
2025-02-19 Jeff Law <jlaw@ventanamicro.com>
PR middle-end/113525
* doc/invoke.texi (dump-rtl-sibling): Drop documentation for pass
removed long ago.
(dump-rtl-unshare): Likewise.
2025-02-18 Andi Kleen <ak@gcc.gnu.org>
* doc/invoke.texi:
2025-02-18 David Malcolm <dmalcolm@redhat.com>
* opts-diagnostic.cc (sarif_scheme_handler::make_sink): Put
properties in alphabetical order.
2025-02-18 Robin Dapp <rdapp@ventanamicro.com>
PR target/115703
* config/riscv/riscv-vsetvl.cc: Use max_sew for calculating the
new LMUL.
2025-02-18 Richard Sandiford <richard.sandiford@arm.com>
PR rtl-optimization/108840
* late-combine.cc (late_combine::check_register_pressure):
Take only allocatable registers into account when checking
the permissiveness of register classes.
2025-02-18 Alex Coplan <alex.coplan@arm.com>
PR rtl-optimization/118320
* pair-fusion.cc (pair_fusion_bb_info::fuse_pair): Tweak wording in dump
message when punting on invalid use arrays.
2025-02-18 Soumya AR <soumyaa@nvidia.com>
* config/aarch64/tuning_models/generic_armv8_a.h: Updated prefetch
struct pointer.
2025-02-18 Richard Biener <rguenther@suse.de>
PR tree-optimization/98845
* tree-ssa-tail-merge.cc (stmt_local_def): Consider a
def with no uses not local.
2025-02-18 Pan Li <pan2.li@intel.com>
PR target/118540
* config/riscv/riscv-target-attr.cc (riscv_target_attr_parser::parse_arch):
Report error when cmd xlen is different with target attribute.
2025-02-18 Haochen Jiang <haochen.jiang@intel.com>
* config/i386/i386.opt.urls: Adjust the order for avx10.2
and avx10.2-512 due to their order change in i386.opt.
2025-02-18 Alexandre Oliva <oliva@adacore.com>
PR tree-optimization/118805
* gimple-fold.cc (fold_truth_andor_for_combine): Detect and
cope with zero-extension in signbit tests. Reject swapping
right-compare operands if rsignbit.
2025-02-17 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.cc (ix86_find_all_reg_use):
Scan only for SET RTX in PARALLEL.
2025-02-17 Uros Bizjak <ubizjak@gmail.com>
PR middle-end/118288
* builtins.cc (expand_builtin_crc_table_based):
Use gen_int_mode to emit constant integers with MSB set.
2025-02-17 Richard Biener <rguenther@suse.de>
PR tree-optimization/118895
* tree-ssa-sccvn.cc (vn_nary_build_or_lookup_1): Only allow
CSE if we can verify the result is available.
2025-02-17 Georg-Johann Lay <avr@gjlay.de>
PR target/118764
* config/avr/gen-avr-mmcu-specs.cc (print_mcu)
[has CVT]: Mention CVT in header comment of generated specs file.
2025-02-17 Haochen Jiang <haochen.jiang@intel.com>
* config/i386/i386.opt.urls: Regenetated.
2025-02-17 Haochen Jiang <haochen.jiang@intel.com>
* common/config/i386/i386-common.cc
(OPTION_MASK_ISA2_AVX10_1_UNSET): Adjust macro.
(OPTION_MASK_ISA2_AVX10_2_256_UNSET): Removed.
(OPTION_MASK_ISA2_AVX10_2_512_UNSET): Ditto.
(OPTION_MASK_ISA2_AVX10_2_UNSET): New.
(ix86_handle_option): Remove disable part for avx10.2-256.
Rename avx10.2-512 switch case to avx10.2 and adjust disable
part macro.
* common/config/i386/i386-isas.h: Adjust avx10.2 and
avx10.2-512.
* config/i386/driver-i386.cc
(host_detect_local_cpu): Do not append -mno-avx10.x-256
for -march=native.
* config/i386/i386-options.cc
(ix86_valid_target_attribute_inner_p): Adjust avx10.2 and
avx10.2-512.
* config/i386/i386.opt: Reject Negative for mavx10.2-256.
Alias mavx10.2-512 to mavx10.2. Reject Negative for
mavx10.2-512.
* doc/extend.texi: Adjust documentation.
* doc/sourcebuild.texi: Ditto.
2025-02-17 Haochen Jiang <haochen.jiang@intel.com>
* common/config/i386/i386-common.cc
(OPTION_MASK_ISA2_AVX2_UNSET): Change AVX10.1 unset macro.
(OPTION_MASK_ISA2_AVX10_1_256_UNSET): Removed.
(OPTION_MASK_ISA2_AVX10_1_512_UNSET): Removed.
(OPTION_MASK_ISA2_AVX10_1_UNSET): New.
(ix86_handle_option): Adjust AVX10.1 unset macro.
* common/config/i386/i386-isas.h: Remove avx10.1.
* config/i386/i386-options.cc
(ix86_valid_target_attribute_inner_p): Ditto.
(ix86_option_override_internal): Adjust warning message.
* config/i386/i386.opt: Remove mavx10.1.
* doc/extend.texi: Remove avx10.1 and adjust doc.
* doc/sourcebuild.texi: Ditto.
2025-02-17 Haochen Jiang <haochen.jiang@intel.com>
PR target/118815
* config/i386/i386-options.cc (ix86_option_override_internal):
Do not check vector size conflict when AVX512 is not explicitly
set.
2025-02-16 Jakub Jelinek <jakub@redhat.com>
PR target/118248
* config/riscv/riscv-string.cc (riscv_block_move_straight): Only
allocate REGS buffer if it will be needed.
2025-02-16 Georg-Johann Lay <avr@gjlay.de>
PR target/118764
* config/avr/avr-c.cc (avr_cpu_cpp_builtins)
[TARGET_CVT]: Define __AVR_CVT__.
* doc/invoke.texi (AVR Built-in Macros): Document __AVR_CVT__.
2025-02-16 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr.cc (avr_result_regno_unused_p): New static function.
(avr_out_bitop): Only output result bytes that are used.
(avr_out_plus_1): Same.
2025-02-16 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr-protos.h (avr_builtin_supported_p): Remove.
* config/avr/avr.cc (avr_init_builtins): Don't initialize
non-available built-ins with NULL_TREE.
(avr_builtin_supported_p): Move to...
* config/avr/avr-c.cc: ...here.
(avr_resolve_overloaded_builtin): Run avr_builtin_supported_p.
2025-02-16 H.J. Lu <hjl.tools@gmail.com>
PR target/109780
PR target/109093
* config/i386/i386.cc (ix86_update_stack_alignment): New.
(ix86_find_all_reg_use_1): Likewise.
(ix86_find_all_reg_use): Likewise.
(ix86_find_max_used_stack_alignment): Also check memory accesses
from registers defined by stack or frame registers.
2025-02-15 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/98028
* vr-values.cc (check_for_binary_op_overflow): Try to use a known
relationship betwen op0/op1 to statically determine overflow state.
2025-02-15 Robin Dapp <rdapp.gcc@gmail.com>
* config/riscv/autovec-opt.md
(*single_widen_first_<any_widen_binop:optab><any_extend:su><mode>):
New combine "bridge" pattern.
2025-02-15 Keith Packard <keithp@keithp.com>
* config/rx/rx.md (rx_cmpstrn): Correctly handle len=0 case.
2025-02-15 David Malcolm <dmalcolm@redhat.com>
* libsarifreplay.cc (sarif_replayer::handle_result_obj): Call
handle_fix_object if we see a single-element "fixes" array.
(sarif_replayer::handle_fix_object): New.
(sarif_replayer::handle_artifact_change_object): New.
2025-02-15 David Malcolm <dmalcolm@redhat.com>
* libsarifreplay.cc (should_add_rule_p): New.
(sarif_replayer::handle_result_obj): Use it to filter out rules
that don't make sense.
2025-02-15 David Malcolm <dmalcolm@redhat.com>
* libsarifreplay.cc (sarif_replayer::handle_result_obj): Treat any
relatedLocations without messages as secondary ranges within the
diagnostic. Doing so requires stashing the notes until after
the diagnostic has been finished, so that relatedLocations can be
walked in one pass.
2025-02-15 David Malcolm <dmalcolm@redhat.com>
PR sarif-replay/118881
* doc/libgdiagnostics/topics/physical-locations.rst: Add
diagnostic_physical_location_get_file.
* libgdiagnostics++.h (physical_location::get_file): New wrapper.
(diagnostic::add_location): Likewise.
* libgdiagnostics.cc (diagnostic_manager::get_file_by_name): New.
(diagnostic_physical_location::get_file): New.
(diagnostic_physical_location_get_file): New.
* libgdiagnostics.h (diagnostic_physical_location_get_file): New.
* libgdiagnostics.map (diagnostic_physical_location_get_file): New.
* libsarifreplay.cc (class annotation): New.
(add_any_annotations): New.
(sarif_replayer::handle_result_obj): Collect vectors of
annotations in the calls to handle_location_object and apply them
to "err" and to "note" as appropriate.
(sarif_replayer::handle_thread_flow_location_object): Pass nullptr
for annotations.
(sarif_replayer::handle_location_object): Handle §3.28.6
"annotations" property, using it to populate a new
"out_annotations" param.
2025-02-15 Thomas Schwinge <thomas@codesourcery.com>
* config/nvptx/nvptx.cc (nvptx_record_needed_fndecl): Tag as
'static'.
2025-02-15 Jin Ma <jinma@linux.alibaba.com>
PR target/118872
* config/riscv/riscv.cc (riscv_fntype_abi): Strengthen the logic
of the check to avoid missing the error report.
2025-02-14 Georg-Johann Lay <avr@gjlay.de>
PR target/118878
* config/avr/avr.cc (avr_out_plus_1): Don't ICE on result of
paradoxical reg's register allocation.
2025-02-14 Thomas Schwinge <tschwinge@baylibre.com>
PR target/94282
PR target/113331
* common/config/gcn/gcn-common.cc (gcn_except_unwind_info): 'return UI_TARGET;'.
* config/gcn/gcn.cc (gcn_asm_init_sections): New function.
(TARGET_ASM_INIT_SECTIONS): '#define'.
2025-02-14 Thomas Schwinge <tschwinge@baylibre.com>
PR target/86660
* common/config/nvptx/nvptx-common.cc (nvptx_except_unwind_info):
'return UI_TARGET;'.
* config/nvptx/nvptx.cc (nvptx_assemble_integer): Handle
'exception_section'.
(nvptx_output_section_asm_op, nvptx_asm_init_sections): New
functions.
(TARGET_ASM_INIT_SECTIONS): '#define'.
* config/nvptx/nvptx.h (TEXT_SECTION_ASM_OP, DATA_SECTION_ASM_OP):
Don't '#define'.
(ASM_OUTPUT_DWARF_DELTA): '#define'.
2025-02-14 Thomas Schwinge <tschwinge@baylibre.com>
* config/nvptx/nvptx.cc (init_frag): New 'bool active' member.
(output_init_frag, nvptx_assemble_value, nvptx_assemble_integer)
(nvptx_output_skip, nvptx_assemble_decl_begin)
(nvptx_assemble_decl_end): Sanity-check its state.
2025-02-14 Thomas Schwinge <tschwinge@baylibre.com>
* config/nvptx/nvptx.cc (nvptx_output_skip): Clarify case of
no or incomplete initializer.
2025-02-14 Richard Biener <rguenther@suse.de>
PR tree-optimization/118852
* tree-vect-slp.cc (vect_analyze_slp): For early-break
forced-live IVs make sure we create an appropriate
entry into the SLP graph.
2025-02-14 Jakub Jelinek <jakub@redhat.com>
PR debug/118790
* tree.cc (struct gt_value_expr_mark_data): New type.
(gt_value_expr_mark_2): Don't call ggc_set_mark, instead check
ggc_marked_p. Treat data as gt_value_expr_mark_data * with pset
in it rather than address of the pset itself and push to be marked
VAR_DECLs into to_mark vec.
(gt_value_expr_mark_1): Change argument from hash_set<tree> *
to gt_value_expr_mark_data * and find pset in it.
(gt_value_expr_mark): Pass to traverse_noresize address of
gt_value_expr_mark_data object rather than hash_table<tree> and
for all entries in the to_mark vector after the traversal call
gt_ggc_mx.
2025-02-14 Lulu Cheng <chenglulu@loongson.cn>
* config/loongarch/genopts/loongarch.opt.in: Add
option '-maddr-reg-reg-cost='.
* config/loongarch/loongarch-def.cc
(loongarch_rtx_cost_data::loongarch_rtx_cost_data): Initialize
addr_reg_reg_cost to 3.
* config/loongarch/loongarch-opts.cc
(loongarch_target_option_override): If '-maddr-reg-reg-cost='
is not used, set it to the initial value.
* config/loongarch/loongarch-tune.h
(struct loongarch_rtx_cost_data): Add the member
addr_reg_reg_cost and its assignment function to the structure
loongarch_rtx_cost_data.
* config/loongarch/loongarch.cc (loongarch_address_insns):
Use la_addr_reg_reg_cost to set the cost of ADDRESS_REG_REG.
* config/loongarch/loongarch.opt: Regenerate.
* config/loongarch/loongarch.opt.urls: Regenerate.
* doc/invoke.texi: Add description of '-maddr-reg-reg-cost='.
2025-02-14 Lulu Cheng <chenglulu@loongson.cn>
PR target/118843
* config/loongarch/loongarch-c.cc
(loongarch_update_cpp_builtins): Fix macro definition issues.
2025-02-14 Lulu Cheng <chenglulu@loongson.cn>
PR target/118828
* config/loongarch/loongarch-c.cc (loongarch_pragma_target_parse):
Update the predefined macros.
2025-02-14 Lulu Cheng <chenglulu@loongson.cn>
* config/loongarch/loongarch-c.cc (builtin_undef): New macro.
(loongarch_cpu_cpp_builtins): Split to loongarch_update_cpp_builtins
and loongarch_define_unconditional_macros.
(loongarch_def_or_undef): New functions.
(loongarch_define_unconditional_macros): Likewise.
(loongarch_update_cpp_builtins): Likewise.
2025-02-14 Lulu Cheng <chenglulu@loongson.cn>
* config/loongarch/loongarch-target-attr.cc
(loongarch_pragma_target_parse): Move to ...
(loongarch_register_pragmas): Move to ...
* config/loongarch/loongarch-c.cc
(loongarch_pragma_target_parse): ... here.
(loongarch_register_pragmas): ... here.
* config/loongarch/loongarch-protos.h
(loongarch_process_target_attr): Function Declaration.
2025-02-14 Richard Biener <rguenther@suse.de>
PR tree-optimization/90579
* tree-ssa-forwprop.cc (simplify_bitfield_ref): Move to
match.pd.
(pass_forwprop::execute): Adjust.
* match.pd (bit_field_ref (vec_perm ...)): New pattern
modeled after simplify_bitfield_ref.
* tree-vect-loop.cc (vect_expand_fold_left): Fold the
element extract stmt, combining it with the vector def.
2025-02-13 Robin Dapp <rdapp.gcc@gmail.com>
PR target/118832
* config/riscv/riscv-v.cc (expand_const_vector): Expand as
vlmax insn during lra.
2025-02-13 Marek Polacek <polacek@redhat.com>
PR driver/117739
* doc/invoke.texi: Tweak wording for -Whardened.
* gcc.cc (driver_handle_option): If -z lazy or -z norelro was
specified, don't enable linker hardening.
(process_command): Don't check warn_hardened.
2025-02-13 Ed Catmur <ed@catmur.uk>
Jason Merrill <jason@redhat.com>
PR c++/70536
* dwarf2out.cc (gen_formal_parameter_pack_die): Add name attr.
2025-02-13 Jakub Jelinek <jakub@redhat.com>
PR debug/118790
* gengtype.cc (write_roots): Remove cache variable, instead break from
the loop on match and test o for NULL. If the cache option has
non-empty string argument, call the specified function with v->name
as argument before calling gt_cleare_cache on it.
* tree.cc (gt_value_expr_mark_2, gt_value_expr_mark_1,
gt_value_expr_mark): New functions.
(value_expr_for_decl): Use GTY ((cache ("gt_value_expr_mark"))) rather
than just GTY ((cache)).
* doc/gty.texi (cache): Document optional argument of cache option.
2025-02-13 Christophe Lyon <christophe.lyon@linaro.org>
PR target/114522
* config/arm/arm-builtins.cc (arm_fold_aes_op): New function.
(arm_general_gimple_fold_builtin): New function.
* config/arm/arm-builtins.h (arm_general_gimple_fold_builtin): New
prototype.
* config/arm/arm.cc (arm_gimple_fold_builtin): Call
arm_general_gimple_fold_builtin as needed.
2025-02-13 Jakub Jelinek <jakub@redhat.com>
PR c++/118822
PR c++/118833
* tree-iterator.h (tsi_split_stmt_list): Declare.
* tree-iterator.cc (tsi_split_stmt_list): New function.
2025-02-13 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* configure.ac (gcc_cv_ld_eh_frame_ciev3): Remove.
* configure, config.in: Regenerate.
* config/sol2.cc (solaris_override_options): Remove.
* config/sol2.h (SUBTARGET_OVERRIDE_OPTIONS): Remove.
* config/sol2-protos.h (solaris_override_options): Remove.
2025-02-13 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* doc/install.texi (Specific, *-*-solaris2*): Updates for newer
Solaris 11.4 SRUs and binutils 2.44.
2025-02-13 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
PR target/118835
* config/s390/s390.cc (s390_valid_shift_count): Reject shift
count operands which do not trivially fit the scheme of
address operands.
2025-02-13 Richard Biener <rguenther@suse.de>
PR tree-optimization/118817
* tree-ssa-sccvn.cc (vn_nary_simplify): Do not process
CONSTRUCTOR NARY or update from CONSTRUCTOR simplified
gimple_match_op.
2025-02-12 Andrew Pinski <quic_apinski@quicinc.com>
PR rtl-optimization/102150
* loop-invariant.cc (find_invariant_insn): Treat inline-asm similar to
trapping instruction and only move them if always executed.
2025-02-12 Andrew Pinski <quic_apinski@quicinc.com>
PR rtl-optimization/102150
* ifcvt.cc (cheap_bb_rtx_cost_p): Return false if the insn
has an inline-asm in it.
2025-02-12 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr.opt.urls: Add -mcall-main.
2025-02-12 Georg-Johann Lay <avr@gjlay.de>
PR target/118806
* config/avr/avr.opt (-mcall-main): New option and...
(avropt_call_main): ...variable.
* config/avr/avr.cc (avr_no_call_main_p): New variable.
(avr_insert_attributes) [-mno-call-main, main]: Add attributes
noreturn and section(".init9") to main. Set avr_no_call_main_p.
(avr_file_end) [avr_no_call_main_p]: Define symbol __call_main.
* doc/invoke.texi (AVR Options) <-mno-call-main>: Document.
<-mnodevicelib>: Extend explanation.
2025-02-12 Alex Coplan <alex.coplan@arm.com>
PR tree-optimization/117790
* tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
Set profile counts for {main,alt}_loop_exit_block.
2025-02-12 Vineet Gupta <vineetg@rivosinc.com>
* config/riscv/vector.md: vncvt substitute vnsrl.
vnsrl with x0 replace with immediate 0.
vneg substitute vrsub.
2025-02-12 Jin Ma <jinma@linux.alibaba.com>
PR target/118601
* config/riscv/riscv-string.cc (expand_block_move): Check with new
constraint 'vl' instead of 'K'.
(expand_vec_setmem): Likewise.
(expand_vec_cmpmem): Likewise.
* config/riscv/riscv-v.cc (force_vector_length_operand): Likewise.
(expand_load_store): Likewise.
(expand_strided_load): Likewise.
(expand_strided_store): Likewise.
(expand_lanes_load_store): Likewise.
2025-02-12 Sandra Loosemore <sloosemore@baylibre.com>
* doc/install.texi: Add missing comma after @xref to fix warning.
2025-02-12 Sandra Loosemore <sloosemore@baylibre.com>
* doc/extend.texi: Fix a bunch of typos and other writing bugs.
* doc/invoke.texi: Likewise.
2025-02-12 Sandra Loosemore <sloosemore@baylibre.com>
* Makefile.in (TEXI_GCCINT_FILES): Remove interface.texi.
* doc/gccint.texi (Top): Remove menu entry for the "interface" node,
and include of interface.texi.
* doc/interface.texi: Delete.
2025-02-12 Yangyu Chen <cyy@cyyself.name>
* config/riscv/riscv-feature-bits.h (RISCV_VENDOR_FEATURE_BITS_LENGTH): Drop.
(struct riscv_vendor_feature_bits): Drop.
2025-02-11 Jeff Law <jlaw@ventanamicro.com>
PR target/115478
* config/aarch64/iterators.md (any_or_plus): New code iterator.
* config/aarch64/aarch64.md (extr<mode>5_insn): Use any_or_plus.
(extr<mode>5_insn_alt, extrsi5_insn_uxtw): Likewise.
(extrsi5_insn_uxtw_alt, extrsi5_insn_di): Likewise.
2025-02-11 Jason Merrill <jason@redhat.com>
PR c++/188574
* doc/invoke.texi: Adjust -frange-for-ext-temps documentation.
2025-02-11 Andrew Carlotti <andrew.carlotti@arm.com>
* config/aarch64/aarch64-option-extensions.def
(SSVE_FP8FMA): Adjust formatting.
(FP8DOT4): Replace FP8FMA dependency with FP8.
(SSVE_FP8DOT4): Replace SSVE_FP8FMA dependency with SME2+FP8.
(FP8DOT2): Replace FP8DOT4 dependency with FP8.
(SSVE_FP8DOT2): Replace SSVE_FP8DOT4 dependency with SME2+FP8.
2025-02-11 Sandra Loosemore <sloosemore@baylibre.com>
* omp-general.cc (omp_check_context_selector): Change
metadirective_p argument to a 3-way flag. Add extra check for
OMP_CTX_BEGIN_DECLARE_VARIANT.
* omp-general.h (enum omp_ctx_directive): New.
(omp_check_context_selector): Adjust declaration.
2025-02-11 Sandra Loosemore <sloosemore@baylibre.com>
* omp-general.cc (omp_context_selector_props_compare): Handle
arbitrary expressions in the "user" and "device_num" selectors.
(omp_context_selector_set_compare): Detect mismatch when one
selector specifies a score and the other doesn't.
2025-02-11 Martin Jambor <mjambor@suse.cz>
PR lto/118125
* ipa-fnsummary.cc (redirect_to_unreachable): Add checking assert
that the builtin_unreachable decl has attribute cold.
2025-02-11 David Malcolm <dmalcolm@redhat.com>
PR sarif-replay/118792
* libsarifreplay.cc (sarif_replayer::handle_region_object): Fix
off-by-one in handling of endColumn property so that the code
matches the comment and the SARIF spec (§3.30.8).
2025-02-11 Richard Biener <rguenther@suse.de>
PR tree-optimization/118817
* tree-ssa-pre.cc (fully_constant_expression): Fold into
the single caller.
(phi_translate_1): Refactor folded in fully_constant_expression.
* tree-ssa-sccvn.cc (vn_nary_simplify): Update the NARY with
the simplified expression.
2025-02-11 H.J. Lu <hjl.tools@gmail.com>
PR target/118825
* config/i386/i386.h (ASM_OUTPUT_SYMBOL_REF): Replace x with
SYM.
2025-02-11 YunQiang Su <syq@debian.org>
* config.gcc: Add mips*64*-linux-muslabi64 triple support.
2025-02-11 Jie Mei <jie.mei@oss.cipunited.com>
Xi Ruoyao <xry111@xry111.site>
* config/mips/i6400.md (i6400_fpu_minmax): Include
fclass type.
(i6400_fpu_fadd): Include frint type.
* config/mips/mips.cc (AVAIL_NON_MIPS16): Add an entry
for __builtin_mipsr6_xxx.
(MIPSR6_BUILTIN_PURE): Same as above.
(CODE_FOR_mipsr6_min_a_s, CODE_FOR_mipsr6_min_a_d)
(CODE_FOR_mipsr6_max_a_s, CODE_FOR_mipsr6_max_a_d)
(CODE_FOR_mipsr6_class_s, CODE_FOR_mipsr6_class_d):
New code_aliasing macros.
(mips_builtins): Add mips32r6 min_a_s, min_a_d, max_a_s,
max_a_d, class_s, class_d builtins.
* config/mips/mips.h (ISA_HAS_FRINT): Define a new macro.
(ISA_HAS_FCLASS): Same as above.
* config/mips/mips.md (UNSPEC_FRINT): New unspec.
(UNSPEC_FCLASS): Same as above.
(type): Add frint and fclass.
(fmin_a_<mode>): Generates MINA.fmt instructions.
(fmax_a_<mode>): Generates MAXA.fmt instructions.
(rint<mode>2): Generates RINT.fmt instructions.
(fclass_<mode>): Generates CLASS.fmt instructions.
* config/mips/p6600.md (p6600_fpu_fadd): Include
frint type.
(p6600_fpu_fabs): Include fclass type.
2025-02-11 Haochen Jiang <haochen.jiang@intel.com>
PR target/118813
* config/i386/avx512bwintrin.h: Fix wrong __OPTIMIZE__
wrap.
2025-02-10 Tobias Burnus <tburnus@baylibre.com>
* config/gcn/mkoffload.cc (enum elf_arch_code): Add
EF_AMDGPU_MACH_AMDGCN_NONE.
(elf_arch): Use enum elf_arch_code as type.
(tool_cleanup): Silence warning by removing tailing '.' from error.
(get_arch_name): Return enum elf_arch_code.
(check_for_missing_lib): New; print fatal error if the multilib
is not available but it is for the associate generic ISA.
(main): Call it.
2025-02-10 Tobias Burnus <tburnus@baylibre.com>
* doc/install.texi (GCN): Update section about multilibs and
required LLVM version.
2025-02-10 Martin Jambor <mjambor@suse.cz>
PR ipa/118097
* ipa-cp.cc (ipa_get_jf_arith_result): Adjust comment.
(ipa_get_jf_pass_through_result): Removed.
(ipa_value_from_jfunc): Use directly ipa_get_jf_arith_result, do
not specify operation type but make sure we check and possibly
convert the result.
(get_val_across_arith_op): Remove the last parameter, always pass
NULL_TREE to ipa_get_jf_arith_result in its last argument.
(propagate_vals_across_arith_jfunc): Do not pass res_type to
get_val_across_arith_op.
(propagate_vals_across_pass_through): Add checking assert that
parm_type is not NULL.
2025-02-10 Jakub Jelinek <jakub@redhat.com>
PR target/118623
* config/i386/i386.md (*bt<mode>): Represent bt as
compare:CCC of const0_rtx and zero_extract rather than
zero_extract and const0_rtx.
(*bt<SWI48:mode>_mask): Likewise.
(*jcc_bt<mode>): Likewise. Use LTU and GEU as flags test
instead of EQ and NE.
(*jcc_bt<mode>_mask): Likewise.
(*jcc_bt<SWI48:mode>_mask_1): Likewise.
(Help combine recognize bt followed by cmov splitter): Likewise.
(*bt<mode>_setcqi): Likewise.
(*bt<mode>_setncqi): Likewise.
(*bt<mode>_setnc<mode>): Likewise.
(*bt<mode>_setncqi_2): Likewise.
(*bt<mode>_setc<mode>_mask): Likewise.
2025-02-09 Dario Gjorgjevski <dario.gjorgjevski@gmail.com>
PR middle-end/117263
* genautomata.cc (output_statistics): Avoid set but unnused warnings
when compiling with NDEBUG.
2025-02-09 Jeff Law <jlaw@ventanamicro.com>
PR target/118146
* config/riscv/riscv.cc (riscv_legitimize_move): Handle subreg
of vector source better to avoid ICE.
2025-02-08 Georg-Johann Lay <avr@gjlay.de>
PR target/118764
* doc/invoke.texi (AVR Options): Fix typos.
2025-02-08 Thomas Schwinge <tschwinge@baylibre.com>
* config/gcn/gcn.md (exception_receiver): 'define_expand'.
* config/nvptx/nvptx.md (exception_receiver): Likewise.
2025-02-08 Thomas Schwinge <tschwinge@baylibre.com>
* doc/sourcebuild.texi (Effective-Target Keywords): Clarify that
effective-target 'exceptions' and 'exceptions_enabled' are
orthogonal.
2025-02-08 Jakub Jelinek <jakub@redhat.com>
PR target/118776
* config/i386/sse.md (<code><mode>3_mask): Use VI1248_AVX512VLBW
iterator rather than VI48_AVX512VL.
(<mask_codefor><code><mode>3<mask_name>): Rename to ...
(*avx512bw_<code><mode>3<mask_name>): ... this. Use
nonimmediate_operand rather than register_operand predicate and %v
rather than v constraint for operand 1 and adjust condition to reject
MEMs in both operand 1 and 2.
2025-02-07 Andrew Pinski <quic_apinski@quicinc.com>
PR target/114522
* config/aarch64/aarch64-builtins.cc (aarch64_fold_aes_op): New function.
(aarch64_general_gimple_fold_builtin): Call aarch64_fold_aes_op for crypto_aese
and crypto_aesd.
2025-02-07 Andi Kleen <ak@gcc.gnu.org>
PR preprocessor/118168
* input.cc (file_cache::m_line_recent,
m_line_recent_first, m_line_recent_last): Add.
(file_cache_slot::evict): Clear new fields.
(file_cache_slot::create): Clear new fields.
(file_cache_slot::file_cache_slot): Initialize new fields.
(file_cache_slot::~file_cache_slot): Release m_line_recent.
(file_cache_slot::get_next_line): Maintain ring buffer of lines
in m_line_recent.
(file_cache_slot::read_line_num): Use m_line_recent to look up
recent lines quickly.
2025-02-07 Richard Earnshaw <rearnsha@arm.com>
PR target/118089
* config/arm/arm.cc (arm_emit_multi_reg_pop): Restructure.
Don't emit LDR on thumb2 when POP can be used for smaller code.
Don't add a CFA adjust note when SP is popped off the stack.
2025-02-07 Richard Earnshaw <rearnsha@arm.com>
PR target/118089
* config/arm/arm.cc (arm_emit_multi_reg_pop): Add a CFA adjust
note to single-register POP instructions.
2025-02-07 Jeff Law <jlaw@ventanamicro.com>
PR rtl-optimization/116244
* ira-build.cc (create_insn_allocnos): Do not restrict the check for
subreg uses to allocno creation time. Do it for all uses.
2025-02-07 Richard Biener <rguenther@suse.de>
PR jit/118780
* system.h: Check INCLUDE_DLFCN_H for including dlfcn.h instead
of ENABLE_PLUGIN.
* plugin.cc: Define INCLUDE_DLFCN_H.
2025-02-07 Pan Li <pan2.li@intel.com>
PR target/118103
* config/riscv/riscv.cc (riscv_conditional_register_usage): Add
the VXRM as the global_regs.
2025-02-07 Andrew Pinski <quic_apinski@quicinc.com>
PR target/118771
* config/aarch64/aarch64.cc (aarch64_split_move): Assert that npieces is
greater than 0.
2025-02-07 Richard Biener <rguenther@suse.de>
PR tree-optimization/115538
* tree-vectorizer.h (vect_get_slp_scalar_def): Declare.
* tree-vect-slp.cc (vect_get_slp_scalar_def): New helper.
* tree-vect-generic.cc (expand_vector_conversion): Adjust.
* tree-vect-stmts.cc (vectorizable_conversion): For SLP
correctly look at ranges of the scalar defs of the SLP operand.
(supportable_indirect_convert_operation): Likewise.
2025-02-07 Tobias Burnus <tburnus@baylibre.com>
* config/gcn/gcn.cc (gcn_hsa_declare_function_name): Update
'amdhsa.version' output to match used code version.
* config/gcn/gen-gcn-device-macros.awk: Add a comment to
crosslink.
2025-02-07 Xi Ruoyao <xry111@xry111.site>
* config/loongarch/loongarch.md
(*sel<code><GPR:mode>_using_<GPR2:mode>): Rename to ...
(*sel<code><GPR:mode>_using_<X:mode>): ... here.
(GPR2): Remove as nothing uses it now.
2025-02-07 Alexandre Oliva <oliva@adacore.com>
PR tree-optimization/118514
PR tree-optimization/118706
* gimple-fold.cc (decode_field_reference): Refuse to consider
merging out-of-bounds BIT_FIELD_REFs.
(make_bit_field_load): Drop too-strict assert.
* tree-eh.cc (bit_field_ref_in_bounds_p): Rename to...
(access_in_bounds_of_type_p): ... this. Change interface,
export.
(tree_could_trap_p): Adjust.
* tree-eh.h (access_in_bounds_of_type_p): Declare.
2025-02-07 Tobias Burnus <tburnus@baylibre.com>
* config/gcn/gcn-devices.def (GCN_DEVICE): Add gfx9-generic,
gfx902, gfx904, gfx909, gfx1031, gfx1032, gfx1033, gfx1034,
gfx1035, gfx1101, gfx1102, gfx1150, gfx1151, gfx1152, and gfx1153.
Add a currently unused column linking, a specific ISA to a generic
one (if it exists).
* config/gcn/gcn-tables.opt: Regenerate
* doc/invoke.texi (AMD GCN): Add the the new gfc... and the older
gfx{10-3,11}-generic to -march= as 'experimental'.
2025-02-07 Tobias Burnus <tburnus@baylibre.com>
* config/gcn/gcn-devices.def (GCN_DEVICE): Change sramecc for
gfx906 to 'any'.
* config/gcn/gcn.cc (GCN_DEVICE): Add tailing ... to #define.
2025-02-07 H.J. Lu <hjl.tools@gmail.com>
PR rtl-optimization/111673
PR rtl-optimization/115932
PR rtl-optimization/116028
PR rtl-optimization/117081
PR rtl-optimization/117082
PR rtl-optimization/118497
* ira-color.cc (assign_hard_reg): Call the target hook for the
callee-saved register cost scale in epilogue and prologue.
* target.def (ira_callee_saved_register_cost_scale): New target
hook.
* targhooks.cc (default_ira_callee_saved_register_cost_scale):
New.
* targhooks.h (default_ira_callee_saved_register_cost_scale):
Likewise.
* config/i386/i386.cc (ix86_ira_callee_saved_register_cost_scale):
New.
(TARGET_IRA_CALLEE_SAVED_REGISTER_COST_SCALE): Likewise.
* doc/tm.texi: Regenerated.
* doc/tm.texi.in (TARGET_IRA_CALLEE_SAVED_REGISTER_COST_SCALE):
New.
2025-02-06 Craig Blackmore <craig.blackmore@embecosm.com>
* config/riscv/riscv.md: Move UNSPEC_SSP_SET and UNSPEC_SSP_TEST
to unspec enum.
2025-02-06 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr.opt.urls: Add mcvt.
2025-02-06 Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/118756
* tree-ssa-loop-ivopts.cc (contain_complex_addr_expr): Remove.
2025-02-06 Georg-Johann Lay <avr@gjlay.de>
PR target/118764
* config/avr/avr.opt (-mcvt): New target option.
* config/avr/avr-arch.h (AVR_CVT): New enum value.
* config/avr/avr-mcus.def: Add AVR_CVT flag for devices that
support it.
* config/avr/avr.cc (avr_handle_isr_attribute) [TARGET_CVT]: Issue
an error when a vector number larger that 3 is used.
* config/avr/gen-avr-mmcu-specs.cc (McuInfo.have_cvt): New property.
(print_mcu) <*avrlibc_startfile>: Use crt<mcu>-cvt.o depending
on -mcvt (or issue an error when the device doesn't support a CVT).
* doc/invoke.texi (AVR Options): Document -mcvt.
2025-02-06 Jakub Jelinek <jakub@redhat.com>
PR rtl-optimization/117506
* loop-iv.cc (get_biv_step_1): For {ZERO,SIGN}_EXTEND
of PLUS apply {ZERO,SIGN}_EXTEND to op1.
2025-02-06 Georg-Johann Lay <avr@gjlay.de>
PR target/118768
* config/avr/genmultilib.awk: Parse the AVR_MCU lines in
a more robust way w.r.t. white spaces.
2025-02-06 Lulu Cheng <chenglulu@loongson.cn>
PR target/118561
* config/loongarch/loongarch-builtins.cc
(loongarch_expand_builtin_lsx_test_branch):
NULL_RTX will not be returned when an error is detected.
(loongarch_expand_builtin): Likewise.
2025-02-06 Richard Sandiford <richard.sandiford@arm.com>
PR tree-optimization/110449
* tree-ssa-loop-manip.h (insert_iv_increment): Declare.
* tree-ssa-loop-manip.cc (insert_iv_increment): New function,
split out from...
(create_iv): ...here and generalized to gimple_seqs.
* tree-vect-loop.cc (vectorizable_induction): Use
standard_iv_increment_position and insert_iv_increment
to insert the IV increment.
2025-02-06 Richard Biener <rguenther@suse.de>
PR rtl-optimization/117922
* fold-mem-offsets.cc (pass_fold_mem_offsets::execute):
Do nothing for a highly connected CFG.
2025-02-06 Richard Biener <rguenther@suse.de>
PR tree-optimization/118749
* tree-vect-data-refs.cc (vector_alignment_reachable_p): Pass
in the vectorization factor, when that cannot maintain
the DRs target alignment do not claim we can reach that
by peeling.
2025-02-05 Jeff Law <jlaw@ventanamicro.com>
* config/bfin/bfin.md (abssi): Disable pattern.
2025-02-05 Vladimir N. Makarov <vmakarov@redhat.com>
PR rtl-optimization/115568
* lra-remat.cc (create_cands): Check that output reload insn is
adjacent to given insn. Update a comment.
2025-02-05 Richard Sandiford <richard.sandiford@arm.com>
* config/aarch64/aarch64.cc (aarch64_insn_cost): Give PARALLELs
the same cost as the costliest SET.
2025-02-05 Jakub Jelinek <jakub@redhat.com>
PR rtl-optimization/117239
* cselib.cc (cselib_init): Remove spurious closing paren in
the #ifdef STACK_ADDRESS_OFFSET specific code.
2025-02-05 Jakub Jelinek <jakub@redhat.com>
PR rtl-optimization/117239
* cselib.cc: Include predict.h.
(callmem): Change type from rtx to rtx[2].
(cselib_preserve_only_values): Use callmem[0] rather than callmem.
(cselib_invalidate_mem): Optimize and don't try to invalidate
for the mem_rtx == callmem[1] case MEMs which clearly can't be
below the stack pointer.
(cselib_process_insn): Use callmem[0] rather than callmem.
For const/pure calls also call cselib_invalidate_mem (callmem[1])
in !ACCUMULATE_OUTGOING_ARGS or cfun->calls_alloca functions.
(cselib_init): Initialize callmem[0] rather than callmem and also
initialize callmem[1].
2025-02-05 Richard Earnshaw <rearnsha@arm.com>
PR target/118089
* config/arm/arm.cc (thumb2_expand_return): Use LDM SP!, {PC}
when optimizing for size, or when there's no performance benefit over
LDR PC, [SP], #4.
(arm_expand_epilogue): Likewise.
2025-02-05 Richard Earnshaw <rearnsha@arm.com>
* config/arm/arm.md (*pop_multiple_with_writeback_and_return): Remove
constraints. Don't validate the first transfer register here.
2025-02-05 Richard Earnshaw <rearnsha@arm.com>
* config/arm/arm.cc (decompose_addr_for_ldm_stm): New function.
(ldm_stm_operation_p): Rework to clarify logic. Allow single
registers to be pushed or popped using LDM/STM.
2025-02-05 Xi Ruoyao <xry111@xry111.site>
PR tree-optimization/118727
* tree-vect-patterns.cc (vect_recog_sad_pattern): Don't call
vect_look_through_possible_promotion on ABD inputs.
2025-02-05 Sebastian Huber <sebastian.huber@embedded-brains.de>
* config/arm/t-rtems: Add Cortex-M33 multilib.
2025-02-04 Andi Kleen <ak@gcc.gnu.org>
* doc/invoke.texi: Document file cache tunables.
* params.opt: Move auto tuning description to lines.
2025-02-04 Ilya Leoshkevich <iii@linux.ibm.com>
* config/s390/s390.cc (print_operand): Remove the no longer
necessary 31-bit and weak symbol handling.
* config/s390/s390.md (*movdi_64): Do not use @PLT with larl.
(*movsi_larl): Likewise.
(main_base_64): Likewise.
(reload_base_64): Likewise.
2025-02-04 Richard Biener <rguenther@suse.de>
PR tree-optimization/117113
* gimple-loop-jam.cc (unroll_jam_possible_p): Detect when
we cannot handle virtual SSA update.
2025-02-04 Andrew Pinski <quic_apinski@quicinc.com>
PR middle-end/116926
* optabs-query.cc (find_widening_optab_handler_and_mode): Fix
limit for `vec-mode -> scalar-mode` case.
2025-02-04 Richard Biener <rguenther@suse.de>
PR rtl-optimization/117611
* combine.cc (simplify_shift_const_1): Bail if not
scalar int mode.
2025-02-04 Richard Biener <rguenther@suse.de>
PR lto/113207
* ipa-free-lang-data.cc (free_lang_data_in_type): First drop
const/volatile qualifiers from function argument types,
then build a simplified type.
2025-02-03 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (*sibcall_pop_memory):
Disable for TARGET_INDIRECT_BRANCH_REGISTER
* config/i386/predicates.md (call_insn_operand): Enable when
"satisfies_constraint_Bw (op)" is true, instead of open-coding
constraint here.
(sibcall_insn_operand): Ditto with "satisfies_constraint_Bs (op)"
2025-02-03 Richard Sandiford <richard.sandiford@arm.com>
* config/aarch64/aarch64.cc (aarch64_choose_vector_init_constant):
New function, split out from...
(aarch64_expand_vector_init_fallback): ...here. Use a bit-
reversed increment to find a constant index. Add support for
stepped constants.
2025-02-03 John David Anglin <danglin@gcc.gnu.org>
PR rtl-optimization/117248
* config/pa/predicates.md (r25_operand): New predicate.
(r26_operand): Likewise.
* config/pa/pa.md: Use match_operand for r25 and r26 hard
register operands in mult, div, udiv, mod and umod millicode
patterns.
2025-02-03 Richard Biener <rguenther@suse.de>
PR tree-optimization/118717
* tree-ssa-phiopt.cc (cond_if_else_store_replacement_1):
Do not common stores referencing abnormal SSA names.
* tree-ssa-sink.cc (sink_common_stores_to_bb): Likewise.
2025-02-03 Andi Kleen <ak@gcc.gnu.org>
* input.cc (check_line): New.
(test_replacement): New function to test line caching.
(input_cc_tests): Call test_replacement
2025-02-03 Andi Kleen <ak@gcc.gnu.org>
PR preprocessor/118168
* input.cc (file_cache_slot::get_next_line): Implement
dynamic sizing of m_line_record based on input length.
* params.opt: (param_file_cache_lines): Set to 0 to size
dynamically.
2025-02-03 Andi Kleen <ak@gcc.gnu.org>
PR preprocessor/118168
* input.cc (total_lines_num): Remove.
(file_cache_slot::evict): Ditto.
(file_cache_slot::create): Ditto.
(file_cache_slot::set_content): Ditto.
(file_cache_slot::file_cache_slot): Ditto.
(file_cache_slot::dump): Ditto.
2025-02-03 Andi Kleen <ak@gcc.gnu.org>
PR preprocessor/118168
* input.cc (file_cache_slot::get_next_line): Use new algorithm
to maintain
(file_cache_slot::read_line_num): Use binary search for lookup.
2025-02-03 Andi Kleen <ak@gcc.gnu.org>
PR preprocessor/118168
* input.cc (file_cache::tune): New function.
* input.h (class file_cache): Make tunables non const.
* params.opt: Add new tunables.
* toplev.cc (toplev::main): Initialize input buffer context
tunables.
2025-02-02 Gaius Mulley <gaiusmod2@gmail.com>
PR modula2/117411
* doc/gm2.texi (Exception handling): New section.
(The ISO system module): Add description of COFF_T.
(Assembler language): Tidy up last sentance.
2025-02-02 Lewis Hyatt <lhyatt@gmail.com>
PR middle-end/115913
* optc-save-gen.awk (cl_optimization_compare): Skip options with
CL_WARNING flag.
2025-02-01 H.J. Lu <hjl.tools@gmail.com>
PR target/118713
* config/i386/i386-expand.cc (ix86_expand_call): Change "if
(TARGET_X32 ...)" back to "else if (TARGET_X32 ...)".
2025-02-01 H.J. Lu <hjl.tools@gmail.com>
PR target/118713
* config/i386/constraints.md (Bs): Always disable if
TARGET_INDIRECT_BRANCH_REGISTER is true.
(Bw): Likewise.
* config/i386/i386-expand.cc (ix86_expand_call): Force indirect
call via register for x32 GOT slot call if
TARGET_INDIRECT_BRANCH_REGISTER is true.
* config/i386/i386-protos.h (ix86_nopic_noplt_attribute_p): New.
* config/i386/i386.cc (ix86_nopic_noplt_attribute_p): Make it
global.
* config/i386/i386.md (*call_got_x32): Disable indirect call via
memory for TARGET_INDIRECT_BRANCH_REGISTER.
(*call_value_got_x32): Likewise.
(*sibcall_value_pop_memory): Likewise.
* config/i386/predicates.md (constant_call_address_operand):
Return false if both TARGET_INDIRECT_BRANCH_REGISTER and
ix86_nopic_noplt_attribute_p are true.
2025-02-01 David Malcolm <dmalcolm@redhat.com>
* libsarifreplay.cc (sarif_replayer::handle_run_obj): Pass run to
handle_result_obj.
(sarif_replayer::handle_result_obj): Add run_obj param and pass it
to handle_location_object and handle_thread_flow_object.
(sarif_replayer::handle_thread_flow_object): Add run_obj param and
pass it to handle_thread_flow_location_object.
(sarif_replayer::handle_thread_flow_location_object): Add run_obj
param and pass it to handle_location_object.
(sarif_replayer::handle_location_object): Add run_obj param and
pass it to handle_logical_location_object.
(sarif_replayer::handle_logical_location_object): Add run_obj
param. If the run_obj is non-null and has "logicalLocations",
then use these "cached" logical locations if we see an "index"
property, as per §3.33.3
2025-02-01 Jeff Law <jlaw@ventanamicro.com>
PR tree-optimization/114277
* match.pd (a * (a || b) -> a): New pattern.
(a * !(a || b) -> 0): Likewise.
2025-01-31 Jakub Jelinek <jakub@redhat.com>
PR ipa/117432
* ipa-icf-gimple.cc (func_checker::compare_asm_inputs_outputs):
Also return_false if operands have incompatible types.
(func_checker::compare_gimple_call): Check fntype1 vs. fntype2
compatibility for all non-internal calls and assume fntype1 and
fntype2 are non-NULL for those. For calls to non-prototyped
calls or for stdarg_p functions after the last named argument (if any)
check type compatibility of call arguments.
2025-01-31 Vladimir N. Makarov <vmakarov@redhat.com>
PR rtl-optimization/116234
* lra-constraints.cc (multiple_insn_refs_p): New function.
(curr_insn_transform): Use it.
2025-01-31 Richard Biener <rguenther@suse.de>
PR debug/100530
* dwarf2out.cc (modified_type_die): Do not claim we handle
address-space qualification with dwarf_qual_info[].
2025-01-31 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/118689
PR modula2/115032
* tree-ssa-loop-niter.cc (build_cltz_expr): Return NULL_TREE if fn is
NULL and use_ifn is false.
2025-01-31 Richard Biener <rguenther@suse.de>
* tree-vect-loop.cc (vect_analyze_loop_operations): Only
call vectorizable_lc_phi when not PURE_SLP.
(vectorizable_reduction): Do not claim having handled
the inner loop LC PHI for outer loop vectorization.
2025-01-30 Georg-Johann Lay <avr@gjlay.de>
* config/avr/builtins.def (STRLEN_FLASH, STRLEN_FLASHX)
(STRLEN_MEMX): New DEF_BUILTIN's.
* config/avr/avr.cc (avr_ftype_strlen): New static function.
(avr_builtin_supported_p): New built-ins are not for AVR_TINY.
(avr_init_builtins) <strlen_flash_node, strlen_flashx_node,
strlen_memx_node>: Provide new fntypes.
(avr_fold_builtin) [AVR_BUILTIN_STRLEN_FLASH]
[AVR_BUILTIN_STRLEN_FLASHX, AVR_BUILTIN_STRLEN_MEMX]: Fold if
possible.
* doc/extend.texi (AVR Built-in Functions): Document
__builtin_avr_strlen_flash, __builtin_avr_strlen_flashx,
__builtin_avr_strlen_memx.
2025-01-30 Georg-Johann Lay <avr@gjlay.de>
* config/avr/builtins.def (AVR_FIRST_C_ONLY_BUILTIN_ID): New macro.
* config/avr/avr-protos.h (avr_builtin_supported_p): New.
* config/avr/avr.cc (avr_builtin_supported_p): New function.
(avr_init_builtins): Only provide a built-in when it is supported.
* config/avr/avr-c.cc (avr_cpu_cpp_builtins): Only define the
__BUILTIN_AVR_<NAME> build-in defines when the associated built-in
function is supported.
* doc/extend.texi (AVR Built-in Functions): Add a note that
following built-ins are supported for only for GNU-C.
2025-01-30 Jakub Jelinek <jakub@redhat.com>
Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
PR target/118696
* config/s390/vector.md (*vec_cmpgt<mode><mode>_nocc_emu,
*vec_cmpgtu<mode><mode>_nocc_emu): Duplicate the first rather than
second V2DImode element.
2025-01-30 Richard Biener <rguenther@suse.de>
PR middle-end/118695
* expr.cc (expand_expr_real_1): When expanding a MEM_REF
to a non-MEM by committing it to a stack temporary make
sure to handle misaligned accesses correctly.
2025-01-30 Tobias Burnus <tburnus@baylibre.com>
* gimplify.cc (gimplify_call_expr): For OpenMP's append_args clause
processed by 'omp dispatch', update for internal-representation
changes; fix handling of hidden arguments, add some comments and
handle Fortran's value dummy and optional/pointer/allocatable actual
args.
2025-01-30 Richard Biener <rguenther@suse.de>
PR middle-end/118692
* expr.cc (expand_expr_real_1): When expanding a MEM_REF
as BIT_FIELD_REF avoid large offsets for accesses not
overlapping the base object.
2025-01-30 Richard Biener <rguenther@suse.de>
PR tree-optimization/114052
* tree-ssa-loop-niter.cc (maybe_lower_iteration_bound): Check
for infinite subloops we might not exit.
2025-01-30 Richard Sandiford <richard.sandiford@arm.com>
PR rtl-optimization/118320
* pair-fusion.cc (pair_fusion_bb_info::fuse_pair): Commonize
the merge of input_uses and return early if it fails.
2025-01-29 Gaius Mulley <gaiusmod2@gmail.com>
PR modula2/118010
PR modula2/118183
PR modula2/116073
* doc/gm2.texi (-fm2-file-offset-bits=): Change the default size
description to CSSIZE_T.
Add COFF_T to the list of data types exported by SYSTEM.def.
2025-01-29 Richard Sandiford <richard.sandiford@arm.com>
PR rtl-optimization/118429
* pair-fusion.cc (latest_hazard_before): Add an extra parameter
to say whether the instruction is a load or a store. If the
instruction is not a load or store and has memory side effects,
prevent it from being moved earlier.
(pair_fusion::find_trailing_add): Update call accordingly.
(pair_fusion_bb_info::fuse_pair): If the trailng addition had
a memory side-effect, use a tombstone to preserve it.
2025-01-29 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr.md (*negsi2.libgcc): New insn.
2025-01-29 Yoshinori Sato <ysato@users.sourceforge.jp>
* config/rx/constraints.md (Q): Also check that the address
passes rx_is_restricted_memory-address.
2025-01-29 Andrew Pinski <quic_apinski@quicinc.com>
PR tree-optimization/118505
* gimple-ssa-split-paths.cc (poor_ifcvt_pred): Return
true for trapping statements.
2025-01-29 Andrew Pinski <quic_apinski@quicinc.com>
* gimple-ssa-split-paths.cc (poor_ifcvt_candidate_code): Remove CALL_EXPR handling.
2025-01-29 Martin Jambor <mjambor@suse.cz>
Michal Jireš <mjires@suse.cz>
PR tree-optimization/117892
* tree-ssa-dse.cc (dse_optimize_call): Leave control-altering
noreturn calls alone.
2025-01-29 Pan Li <pan2.li@intel.com>
PR target/117688
* config/riscv/riscv.cc (riscv_expand_sstrunc): Leverage the helper
riscv_extend_to_xmode_reg with SIGN_EXTEND.
2025-01-29 Pan Li <pan2.li@intel.com>
PR target/117688
* config/riscv/riscv.cc (riscv_expand_sssub): Leverage the helper
riscv_extend_to_xmode_reg with SIGN_EXTEND.
2025-01-29 Pan Li <pan2.li@intel.com>
PR target/117688
* config/riscv/riscv.cc (riscv_expand_ssadd): Leverage the helper
riscv_extend_to_xmode_reg with SIGN_EXTEND.
2025-01-29 Pan Li <pan2.li@intel.com>
* config/riscv/riscv.cc (riscv_gen_zero_extend_rtx): Rename from ...
(riscv_extend_to_xmode_reg): Rename to and add rtx_code for
zero/sign extend if non-Xmode.
(riscv_expand_usadd): Leverage the renamed function with ZERO_EXTEND.
(riscv_expand_ussub): Ditto.
2025-01-29 Richard Biener <rguenther@suse.de>
PR middle-end/118684
* expr.cc (expand_expr_real_1): When creating a stack local
during expansion of a handled component, when the base is
a SSA_NAME use its type alignment and avoid calling
get_object_alignment.
2025-01-28 Richard Biener <rguenther@suse.de>
PR middle-end/118684
* expr.cc (expand_expr_real_1): When expanding a reference
based on a register and we end up needing a MEM make sure
that's aligned as the original reference required.
2025-01-28 David Malcolm <dmalcolm@redhat.com>
* input.cc (file_cache_slot::dump): Show indices within
m_line_record when dumping entries.
2025-01-28 David Malcolm <dmalcolm@redhat.com>
PR other/118675
* diagnostic-format-sarif.cc: Define INCLUDE_STRING.
(escape_braces): New.
(set_string_property_escaping_braces): New.
(sarif_builder::make_message_object): Escape braces in the "text"
property.
(sarif_builder::make_message_object_for_diagram): Likewise, and
for the "markdown" property.
(sarif_builder::make_multiformat_message_string): Likewise for the
"text" property.
(xelftest::test_message_with_braces): New.
(selftest::diagnostic_format_sarif_cc_tests): Call it.
2025-01-28 Richard Sandiford <richard.sandiford@arm.com>
PR tree-optimization/117270
* tree-vect-slp.cc (vectorizable_slp_permutation_1): Make nperms
account for the number of times that each permutation will be used
during transformation.
2025-01-28 Richard Biener <rguenther@suse.de>
PR tree-optimization/112859
* tree-loop-distribution.cc
(loop_distribution::pg_add_dependence_edges): Add comment.
2025-01-28 Vladimir N. Makarov <vmakarov@redhat.com>
PR target/118663
* lra-constraints.cc (invalid_mode_reg_p): Check empty
reg_class_contents.
2025-01-28 Richard Biener <rguenther@suse.de>
PR tree-optimization/117424
* tree-eh.cc (tree_could_trap_p): Verify the base is
fully contained within a decl.
2025-01-28 Thomas Schwinge <tschwinge@baylibre.com>
* tree-pretty-print.cc (dump_omp_clause): Clarify
'OMP_CLAUSE_MAP_RUNTIME_IMPLICIT_P'.
2025-01-28 Jakub Jelinek <jakub@redhat.com>
PR rtl-optimization/118638
* combine.cc (make_extraction): Only optimize (mult x 2^n) if len is
larger than 1.
2025-01-28 Richard Sandiford <richard.sandiford@arm.com>
* tree-vect-slp.cc (vectorizable_slp_permutation_1): Remove
extra newline from dump message.
2025-01-28 Jeff Law <jlaw@ventanamicro.com>
PR target/114085
* config/h8300/constraints.md (U): No longer accept REGs.
* config/h8300/logical.md (andqi3_2): Use "rU" rather than "U".
(andqi3_2_clobber_flags, andqi3_1, <code>qi3_1): Likewise.
* config/h8300/testcompare.md (tst_extzv_1_n): Likewise.
2025-01-27 Robin Dapp <rdapp@ventanamicro.com>
PR target/117173
* config/riscv/riscv-v.cc (shuffle_generic_patterns): Only
support single-source permutes by default.
* config/riscv/riscv.opt: New param "riscv-two-source-permutes".
2025-01-27 John David Anglin <danglin@gcc.gnu.org>
PR c++/116524
* configure.ac: Check for munmap and msync.
* configure: Regenerate.
* config.in: Regenerate.
2025-01-27 Richard Biener <rguenther@suse.de>
PR tree-optimization/118653
* tree-vect-loop.cc (vectorizable_live_operation): Also allow
out-of-loop debug uses.
2025-01-27 Richard Biener <rguenther@suse.de>
PR rtl-optimization/118662
* combine.cc (try_combine): When re-materializing a load
from an extended reg by a lowpart subreg make sure we're
not dealing with vector or complex modes.
2025-01-27 Richard Biener <rguenther@suse.de>
PR middle-end/118643
* expr.cc (expand_expr_real_1): Avoid falling back to BIT_FIELD_REF
expansion for negative offset.
2025-01-27 Richard Biener <rguenther@suse.de>
PR tree-optimization/112859
PR tree-optimization/115347
* tree-loop-distribution.cc
(loop_distribution::pg_add_dependence_edges): For a zero
distance vector still make sure to not have an inner
loop with zero distance.
2025-01-27 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/118637
* match.pd: Canonicalize unsigned division by power of two to
right shift.
2025-01-27 Soumya AR <soumyaa@nvidia.com>
PR target/118490
* match.pd: Added ! to verify that log/exp (CST) can be constant folded.
2025-01-26 Ilya Leoshkevich <iii@linux.ibm.com>
* asan.cc (asan_emit_stack_protection): Always zero the flag
unless it is cleared by the __asan_stack_free_N() libcall.
2025-01-26 Pan Li <pan2.li@intel.com>
PR target/118103
* config/riscv/riscv.cc (riscv_conditional_register_usage): Add
the FRM as the global_regs.
2025-01-25 Andi Kleen <ak@gcc.gnu.org>
PR preprocessor/118168
* input.cc (file_cache_slot::m_error): New field.
(file_cache_slot::create): Clear m_error.
(file_cache_slot::file_cache_slot): Clear m_error.
(file_cache_slot::read_data): Set m_error on error.
(file_cache_slot::get_next_line): Use m_error instead of ferror.
2025-01-25 Jeff Law <jlaw@ventanamicro.com>
PR target/116256
* config/riscv/riscv.md (mvconst_internal): Reject single bit
constants.
* config/riscv/riscv.cc (riscv_gen_zero_extend_rtx): Improve
handling constants.
2025-01-24 Andrew Carlotti <andrew.carlotti@arm.com>
* config/aarch64/aarch64-arches.def (V9_5A): Add CPA.
* config/aarch64/aarch64-option-extensions.def (CPA): New.
* doc/invoke.texi: Document +cpa.
2025-01-24 Andrew Carlotti <andrew.carlotti@arm.com>
* doc/invoke.texi: Add +wfxt and +xs to armv9.2-a
2025-01-24 Andrew Carlotti <andrew.carlotti@arm.com>
* config/aarch64/aarch64-arches.def (V9_5A): New.
* doc/invoke.texi: Document armv9.5-a option.
2025-01-24 Andrew Carlotti <andrew.carlotti@arm.com>
* common/config/aarch64/aarch64-common.cc: Assert that CRYPTO
bit is not set.
* config/aarch64/aarch64-feature-deps.h
(info<FEAT>.explicit_on): Unset CRYPTO bit.
(cpu_##CORE_IDENT): Ditto.
2025-01-24 Andrew Carlotti <andrew.carlotti@arm.com>
* common/config/aarch64/aarch64-common.cc
(aarch64_rewrite_selected_cpu): Refactor and inline into...
(aarch64_rewrite_mcpu): this.
* config/aarch64/aarch64-protos.h
(aarch64_rewrite_selected_cpu): Delete.
2025-01-24 Andrew Carlotti <andrew.carlotti@arm.com>
* common/config/aarch64/aarch64-common.cc
(aarch64_get_arch_string_for_assembler): New.
(aarch64_rewrite_march): New.
(aarch64_rewrite_selected_cpu): Call new function.
* config/aarch64/aarch64-elf.h (ASM_SPEC): Remove identity mapping.
* config/aarch64/aarch64-protos.h
(aarch64_get_arch_string_for_assembler): New.
* config/aarch64/aarch64.cc
(aarch64_declare_function_name): Call new function.
(aarch64_start_file): Ditto.
* config/aarch64/aarch64.h
(EXTRA_SPEC_FUNCTIONS): Use new macro name.
(MCPU_TO_MARCH_SPEC): Rename to...
(MARCH_REWRITE_SPEC): ...this, and extend the spec rule.
(aarch64_rewrite_march): New declaration.
(MCPU_TO_MARCH_SPEC_FUNCTIONS): Rename to...
(AARCH64_BASE_SPEC_FUNCTIONS): ...this, and add new function.
(ASM_CPU_SPEC): Use new macro name.
2025-01-24 Andrew Carlotti <andrew.carlotti@arm.com>
* common/config/aarch64/aarch64-common.cc
(aarch64_get_all_extension_candidates): Inline into...
(aarch64_print_hint_for_extensions): ...this.
2025-01-24 Andrew Carlotti <andrew.carlotti@arm.com>
* common/config/aarch64/aarch64-common.cc
(aarch64_get_all_extension_candidates): Move within file.
(aarch64_print_hint_candidates): Move from aarch64.cc.
(aarch64_print_hint_for_extensions): Ditto.
(aarch64_print_hint_for_arch): Ditto.
(aarch64_print_hint_for_core): Ditto.
(enum aarch_parse_opt_result): Ditto.
(aarch64_parse_arch): Ditto.
(aarch64_parse_cpu): Ditto.
(aarch64_parse_tune): Ditto.
(aarch64_validate_march): Ditto.
(aarch64_validate_mcpu): Ditto.
(aarch64_validate_mtune): Ditto.
* config/aarch64/aarch64-protos.h
(aarch64_rewrite_selected_cpu): Move within file.
(aarch64_print_hint_for_extensions): Share function prototype.
(aarch64_print_hint_for_arch): Ditto.
(aarch64_print_hint_for_core): Ditto.
(enum aarch_parse_opt_result): Ditto.
(aarch64_validate_march): Ditto.
(aarch64_validate_mcpu): Ditto.
(aarch64_validate_mtune): Ditto.
(aarch64_get_all_extension_candidates): Unshare prototype.
* config/aarch64/aarch64.cc
(aarch64_parse_arch): Move to aarch64-common.cc.
(aarch64_parse_cpu): Ditto.
(aarch64_parse_tune): Ditto.
(aarch64_print_hint_candidates): Ditto.
(aarch64_print_hint_for_core): Ditto.
(aarch64_print_hint_for_arch): Ditto.
(aarch64_print_hint_for_extensions): Ditto.
(aarch64_validate_mcpu): Ditto.
(aarch64_validate_march): Ditto.
(aarch64_validate_mtune): Ditto.
2025-01-24 Andrew Carlotti <andrew.carlotti@arm.com>
* config/aarch64/aarch64.cc
(aarch64_print_hint_candidates): New helper function.
(aarch64_print_hint_for_core_or_arch): Inline into callers.
(aarch64_print_hint_for_core): Inline callee and use new helper.
(aarch64_print_hint_for_arch): Ditto.
(aarch64_print_hint_for_extensions): Use new helper.
2025-01-24 Andrew Carlotti <andrew.carlotti@arm.com>
* config/aarch64/aarch64.cc
(aarch64_print_hint_for_extensions): Receive string as a char *.
(aarch64_parse_arch): Don't return a const struct processor *.
(aarch64_parse_cpu): Ditto.
(aarch64_parse_tune): Ditto.
(aarch64_validate_mtune): Ditto.
(aarch64_validate_mcpu): Ditto, and use temporary variables for
march/mcpu cross-check.
(aarch64_validate_march): Ditto.
(aarch64_override_options): Adjust for changed parameter types.
(aarch64_handle_attr_arch): Ditto.
(aarch64_handle_attr_cpu): Ditto.
(aarch64_handle_attr_tune): Ditto.
2025-01-24 Andrew Carlotti <andrew.carlotti@arm.com>
* common/config/aarch64/aarch64-common.cc
(struct aarch64_option_extension): Rename to..
(struct aarch64_extension_info): ...this.
(all_extensions): Update type name.
(struct arch_to_arch_name): Rename to...
(struct aarch64_arch_info): ...this, and rename name field.
(all_architectures): Update type names, and move before...
(struct processor_name_to_arch): ...this. Rename to...
(struct aarch64_processor_info): ...this, rename name field and
add cpu field.
(all_cores): Update type name, and set new field.
(aarch64_parse_extension): Update names.
(aarch64_get_all_extension_candidates): Ditto.
(aarch64_rewrite_selected_cpu): Ditto.
2025-01-24 Andrew Carlotti <andrew.carlotti@arm.com>
* common/config/aarch64/aarch64-common.cc
(all_cores): Remove explicit generic entry.
2025-01-24 Andrew Carlotti <andrew.carlotti@arm.com>
* config/aarch64/aarch64-opts.h
(enum aarch64_processor): Rename to...
(enum aarch64_cpu): ...this, and rename the entries.
* config/aarch64/aarch64.cc
(aarch64_type): Rename type and initial value.
(struct processor): Rename member types.
(all_architectures): Rename enum members.
(all_cores): Ditto.
(aarch64_get_tune_cpu): Rename type and enum member.
* config/aarch64/aarch64.h (enum target_cpus): Remove.
(TARGET_CPU_DEFAULT): Rename default value.
(aarch64_tune): Rename type.
* config/aarch64/aarch64.opt:
(selected_tune): Rename type and default value.
2025-01-24 Andrew Carlotti <andrew.carlotti@arm.com>
* config/aarch64/aarch64.cc (aarch64_override_options): Compare
returned feature masks directly.
2025-01-24 Vladimir N. Makarov <vmakarov@redhat.com>
PR target/118497
* ira-int.h (target_ira_int): Add x_ira_hard_regno_nrefs.
(ira_hard_regno_nrefs): New macro.
* ira.cc (setup_hard_regno_aclass): Remove unused code. Modify
the comment.
(setup_hard_regno_nrefs): New function.
(ira): Call it.
* ira-color.cc (calculate_saved_nregs): Check
ira_hard_regno_nrefs.
2025-01-24 yxj-github-437 <2457369732@qq.com>
* config/aarch64/aarch64.cc (aarch64_build_builtin_va_list): Mark
__builtin_va_list as TREE_PUBLIC.
* config/arm/arm.cc (arm_build_builtin_va_list): Likewise.
2025-01-24 David Malcolm <dmalcolm@redhat.com>
PR sarif-replay/117670
* Makefile.in (SARIF_REPLAY_INSTALL_NAME): New.
(install-libgdiagnostics): Use it,and exeext, rather than just
sarif-replay.
2025-01-24 Richard Biener <rguenther@suse.de>
PR tree-optimization/116010
* tree-data-ref.cc (contains_ssa_ref_p_1): New function.
(contains_ssa_ref_p): Likewise.
(dr_may_alias_p): Avoid treating unanalyzed base parts without
SSA reference conservatively.
2025-01-24 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* config/s390/s390.h (S390_TDC_POSITIVE_ZERO): Remove.
(S390_TDC_NEGATIVE_ZERO): Remove.
(S390_TDC_POSITIVE_NORMALIZED_BFP_NUMBER): Remove.
(S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER): Remove.
(S390_TDC_POSITIVE_DENORMALIZED_BFP_NUMBER): Remove.
(S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER): Remove.
(S390_TDC_POSITIVE_INFINITY): Remove.
(S390_TDC_NEGATIVE_INFINITY): Remove.
(S390_TDC_POSITIVE_QUIET_NAN): Remove.
(S390_TDC_NEGATIVE_QUIET_NAN): Remove.
(S390_TDC_POSITIVE_SIGNALING_NAN): Remove.
(S390_TDC_NEGATIVE_SIGNALING_NAN): Remove.
(S390_TDC_POSITIVE_DENORMALIZED_DFP_NUMBER): Remove.
(S390_TDC_NEGATIVE_DENORMALIZED_DFP_NUMBER): Remove.
(S390_TDC_POSITIVE_NORMALIZED_DFP_NUMBER): Remove.
(S390_TDC_NEGATIVE_NORMALIZED_DFP_NUMBER): Remove.
(S390_TDC_SIGNBIT_SET): Remove.
(S390_TDC_INFINITY): Remove.
* config/s390/s390.md (signbit<mode>2<tf_fpr>): Merge this one
(isinf<mode>2<tf_fpr>): and this one into
(<TDC_CLASS:tdc_insn><mode>2<tf_fpr>): new expander.
(isnormal<mode>2<tf_fpr>): New BFP expander.
(isnormal<mode>2): New DFP expander.
* config/s390/vector.md (signbittf2_vr): Merge this one
(isinftf2_vr): and this one into
(<tdc_insn>tf2_vr): new expander.
(signbittf2): Merge this one
(isinftf2): and this one into
(<tdc_insn>tf2): new expander.
2025-01-24 Richard Biener <rguenther@suse.de>
PR tree-optimization/118634
* tree-ssa-loop-ivcanon.cc (try_unroll_loop_completely):
Dump the number of estimated eliminated insns.
2025-01-24 Saurabh Jha <saurabh.jha@arm.com>
* config/aarch64/aarch64-sve2.md:
(*aarch64_pred_faminmax_fused): Fix to use the correct flags.
* config/aarch64/aarch64.h
(TARGET_SVE_FAMINMAX): Remove.
* config/aarch64/iterators.md: Fix iterators so that famax and
famin use correct flags.
2025-01-24 Alexandre Oliva <oliva@adacore.com>
PR tree-optimization/118572
* gimple-fold.cc (fold_truth_andor_for_ifcombine): Compare as
unsigned the variables whose extension bits are masked out.
2025-01-24 Alexandre Oliva <oliva@adacore.com>
* gimple-fold.cc (fold_truth_andor_for_ifcombine): Document
reversep's absence of effects on range tests. Don't reject
reversep mismatches before trying compare swapping.
2025-01-24 Alexandre Oliva <oliva@adacore.com>
PR tree-optimization/118514
* tree-eh.cc (bit_field_ref_in_bounds_p): New.
(tree_could_trap_p) <BIT_FIELD_REF>: Call it.
* gimple-fold.cc (make_bit_field_load): Check trapping status
of replacement load against original load.
2025-01-23 John David Anglin <danglin@gcc.gnu.org>
* config/pa/pa32-regs.h (ADDITIONAL_REGISTER_NAMES): Change
register 86 name to "%fr31L".
2025-01-23 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/118628
* tree-vect-stmts.cc (vectorizable_store, vectorizable_load):
Initialize offvar to NULL_TREE.
2025-01-23 Georg-Johann Lay <avr@gjlay.de>
PR tree-optimization/118012
PR tree-optimization/118360
* config/avr/avr.opt (-mpr118012): New undocumented option.
* config/avr/avr-protos.h (avr_out_sextr)
(avr_emit_skip_pixop, avr_emit_skip_clear): New protos.
* config/avr/avr.cc (avr_adjust_insn_length)
[case ADJUST_LEN_SEXTR]: Handle case.
(avr_rtx_costs_1) [NEG]: Costs for NEG (ZERO_EXTEND (ZERO_EXTRACT)).
[MULT && avropt_pr118012]: Costs for MULT (x AND 1).
(avr_out_sextr, avr_emit_skip_pixop, avr_emit_skip_clear): New
functions.
* config/avr/avr.md [avropt_pr118012]: Add combine patterns with
that condition that try to work around PR118012.
(adjust_len) <sextr>: Add insn attr value.
(pixop): New code iterator.
(mulsi3) [avropt_pr118012 && !AVR_TINY]: Allow these in insn condition.
2025-01-23 Richard Sandiford <richard.sandiford@arm.com>
PR rtl-optimization/118562
* rtl-ssa/blocks.cc (function_info::replace_phi): When converting
to a degenerate phi, make sure to remove all uses of the previous
inputs.
2025-01-23 Richard Sandiford <richard.sandiford@arm.com>
* config/aarch64/aarch64-tuning-flags.def
(AARCH64_EXTRA_TUNE_CHEAP_FPMR_WRITE): New tuning flag.
* config/aarch64/aarch64.h (TARGET_CHEAP_FPMR_WRITE): New macro.
* config/aarch64/aarch64.md: Split moves into FPMR into a test
and branch around.
(aarch64_write_fpmr): New pattern.
2025-01-23 Richard Sandiford <richard.sandiford@arm.com>
* config/aarch64/aarch64.cc (aarch64_memory_move_cost): Account
for the cost of moving in and out of GENERAL_SYSREGS.
2025-01-23 Richard Sandiford <richard.sandiford@arm.com>
* config/aarch64/aarch64.md (*mov<SHORT:mode>_aarch64)
(*movsi_aarch64, *movdi_aarch64): Allow the source of an MSR
to be zero.
2025-01-23 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/118605
* tree-assume.cc (assume_query::m_parm_list): Change type
from bitmap & to bitmap.
2025-01-23 Tejas Belagod <tejas.belagod@arm.com>
* omp-low.cc (use_pointer_for_field): Use pointer if the OMP data
structure's field type is a poly-int.
2025-01-23 Jakub Jelinek <jakub@redhat.com>
PR middle-end/114877
* builtins.cc (fold_builtin_frexp): Handle rvc_nan and rvc_inf cases
like rvc_zero, return passed in arg and set *exp = 0.
2025-01-23 Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
* doc/sourcebuild.texi (Effective-Target Keywords): Document
'alarm'.
2025-01-23 Georg-Johann Lay <avr@gjlay.de>
PR target/117726
* config/avr/avr.cc (avr_ld_regno_p): New function.
(ashlsi3_out) [case 25,26,27,28,29,30]: Handle and tweak.
(lshrsi3_out): Same.
(avr_rtx_costs_1) [SImode, ASHIFT, LSHIFTRT]: Adjust costs.
* config/avr/avr.md (ashlsi3, *ashlsi3, *ashlsi3_const):
Add "r,r,C4L" alternative.
(lshrsi3, *lshrsi3, *lshrsi3_const): Add "r,r,C4R" alternative.
* config/avr/constraints.md (C4R, C4L): New,
2025-01-23 Richard Biener <rguenther@suse.de>
PR tree-optimization/118558
* tree-vectorizer.h (vect_known_alignment_in_bytes): Pass
through offset to dr_misalignment.
* tree-vect-stmts.cc (get_group_load_store_type): Compute
offset applied for negative stride and use it when querying
alignment of accesses.
(vectorizable_load): Likewise.
2025-01-23 Nathaniel Shead <nathanieloshead@gmail.com>
PR c++/107741
* common.opt: Add -fabi-version=20.
* doc/invoke.texi: Likewise.
2025-01-23 Xi Ruoyao <xry111@xry111.site>
PR target/118501
* config/loongarch/loongarch.md (@xorsign<mode>3): Use
force_lowpart_subreg.
2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
* config/i386/avx10_2-512convertintrin.h:
Omit "p" for packed for FP8.
* config/i386/avx10_2convertintrin.h: Ditto.
2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
PR target/118270
* config/i386/avx10_2-512satcvtintrin.h: Change intrin and
builtin name according to new mnemonics.
* config/i386/avx10_2satcvtintrin.h: Ditto.
* config/i386/i386-builtin.def (BDESC): Ditto.
* config/i386/sse.md
(UNSPEC_VCVTBF162IBS): Rename from UNSPEC_VCVTNEBF162IBS.
(UNSPEC_VCVTBF162IUBS): Rename from UNSPEC_VCVTNEBF162IUBS.
(UNSPEC_VCVTTBF162IBS): Rename from UNSPEC_VCVTTNEBF162IBS.
(UNSPEC_VCVTTBF162IUBS): Rename from UNSPEC_VCVTTNEBF162IUBS.
(UNSPEC_CVTNE_BF16_IBS_ITER): Rename to...
(UNSPEC_CVT_BF16_IBS_ITER): ...this. Adjust UNSPEC name.
(sat_cvt_sign_prefix): Adjust UNSPEC name.
(sat_cvt_trunc_prefix): Ditto.
(avx10_2_cvt<sat_cvt_trunc_prefix>nebf162i<sat_cvt_sign_prefix>bs<mode><mask_name>):
Rename to...
(avx10_2_cvt<sat_cvt_trunc_prefix>bf162i<sat_cvt_sign_prefix>bs<mode><mask_name>):
...this. Change instruction name output.
2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
PR target/118270
* config/i386/avx10_2-512convertintrin.h: Change intrin and
builtin name according to new mnemonics.
* config/i386/avx10_2convertintrin.h: Ditto.
* config/i386/i386-builtin.def (BDESC): Ditto.
* config/i386/sse.md
(UNSPEC_VCVTPH2BF8): Rename from UNSPEC_VCVTNEPH2BF8.
(UNSPEC_VCVTPH2BF8S): Rename from UNSPEC_VCVTNEPH2BF8S.
(UNSPEC_VCVTPH2HF8): Rename from UNSPEC_VCVTNEPH2HF8.
(UNSPEC_VCVTPH2HF8S): Rename from UNSPEC_VCVTNEPH2HF8S.
(UNSPEC_CONVERTPH2FP8): Rename from UNSPEC_NECONVERTPH2FP8.
Adjust UNSPEC name.
(convertph2fp8): Rename from neconvertph2fp8. Adjust
iterator map.
(vcvt<neconvertph2fp8>v8hf): Rename to...
(vcvt<neconvertph2fp8>v8hf): ...this.
(*vcvt<neconvertph2fp8>v8hf): Rename to...
(*vcvt<neconvertph2fp8>v8hf): ...this.
(vcvt<neconvertph2fp8>v8hf_mask): Rename to...
(vcvt<neconvertph2fp8>v8hf_mask): ...this.
(*vcvt<neconvertph2fp8>v8hf_mask): Rename to...
(*vcvt<neconvertph2fp8>v8hf_mask): ...this.
(vcvt<neconvertph2fp8><mode><mask_name>): Rename to...
(vcvt<convertph2fp8><mode><mask_name>): ...this.
2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
PR target/118270
* config/i386/avx10_2-512convertintrin.h: Change intrin and
builtin name according to new mnemonics.
* config/i386/avx10_2convertintrin.h: Ditto.
* config/i386/i386-builtin.def (BDESC): Ditto.
* config/i386/sse.md
(UNSPEC_VCVT2PH2BF8): Rename from UNSPEC_VCVTNE2PH2BF8.
(UNSPEC_VCVT2PH2BF8S): Rename from UNSPEC_VCVTNE2PH2BF8S.
(UNSPEC_VCVT2PH2HF8): Rename from UNSPEC_VCVTNE2PH2HF8.
(UNSPEC_VCVT2PH2HF8S): Rename from UNSPEC_VCVTNE2PH2HF8S.
(UNSPEC_CONVERTFP8_PACK): Rename from UNSPEC_NECONVERTFP8_PACK.
Adjust UNSPEC name.
(convertfp8_pack): Rename from neconvertfp8_pack. Adjust
iterator map.
(vcvt<neconvertfp8_pack><mode><mask_name>): Rename to...
(vcvt<convertfp8_pack><mode><mask_name>): ...this.
2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
PR target/118270
* config/i386/avx10_2bf16intrin.h: Change intrin and builtin
name according to new mnemonics.
* config/i386/i386-builtin.def (BDESC): Ditto.
* config/i386/i386-expand.cc
(ix86_expand_fp_compare): Adjust comments.
(ix86_expand_builtin): Adjust switch case.
* config/i386/i386.md (cmpibf): Change instruction name output.
* config/i386/sse.md (UNSPEC_VCOMSBF16): Removed.
(avx10_2_comisbf16_v8bf): New.
(avx10_2_comsbf16_v8bf): Removed.
2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
PR target/118270
* config/i386/avx10_2-512bf16intrin.h: Change intrin and builtin
name according to new mnemonics.
* config/i386/avx10_2bf16intrin.h: Ditto.
* config/i386/i386-builtin.def (BDESC): Ditto.
* config/i386/sse.md
(UNSPEC_VFPCLASSBF16); Rename from UNSPEC_VFPCLASSPBF16.
(avx10_2_getexppbf16_<mode><mask_name>): Rename to...
(avx10_2_getexpbf16_<mode><mask_name>): ...this.
Change instruction name output.
(avx10_2_fpclasspbf16_<mode><mask_scalar_merge_name>):
Rename to...
(avx10_2_fpclassbf16_<mode><mask_scalar_merge_name>): ...this.
Change instruction name output.
2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
PR target/118270
* config/i386/avx10_2-512bf16intrin.h: Change intrin and builtin
name according to new mnemonics.
* config/i386/avx10_2bf16intrin.h: Ditto.
* config/i386/i386-builtin.def (BDESC): Ditto.
* config/i386/sse.md
(UNSPEC_VSCALEFBF16): Rename from UNSPEC_VSCALEFPBF16.
(avx10_2_scalefpbf16_<mode><mask_name>): Rename to...
(avx10_2_scalefbf16_<mode><mask_name>): ...this.
Change instruction name output.
(avx10_2_rsqrtpbf16_<mode><mask_name>): Rename to...
(avx10_2_rsqrtbf16_<mode><mask_name>): ...this.
Change instruction name output.
(avx10_2_sqrtnepbf16_<mode><mask_name>): Rename to...
(avx10_2_sqrtbf16_<mode><mask_name>): ...this.
Change instruction name output.
2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
PR target/118270
* config/i386/avx10_2-512bf16intrin.h: Change intrin and builtin
name according to new mnemonics.
* config/i386/avx10_2bf16intrin.h: Ditto.
* config/i386/i386-builtin.def (BDESC): Ditto.
* config/i386/sse.md
(UNSPEC_VRNDSCALEBF16): Rename from UNSPEC_VRNDSCALENEPBF16.
(UNSPEC_VREDUCEBF16): Rename from UNSPEC_VREDUCENEPBF16.
(UNSPEC_VGETMANTBF16): Rename from UNSPEC_VGETMANTPBF16.
(BF16IMMOP): Adjust iterator due to UNSPEC name change.
(bf16immop): Ditto.
(avx10_2_<bf16immop>pbf16_<mode><mask_name>): Rename to...
(avx10_2_<bf16immop>bf16_<mode><mask_name>): ...this. Change
instruction name output.
2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
PR target/118270
* config/i386/avx10_2-512minmaxintrin.h: Change intrin and
builtin name according to new mnemonics.
* config/i386/avx10_2minmaxintrin.h: Ditto.
* config/i386/i386-builtin.def (BDESC): Ditto.
* config/i386/sse.md
(UNSPEC_MINMAXBF16): Rename from UNSPEC_MINMAXNEPBF16.
(avx10_2_minmaxnepbf16_<mode><mask_name>): Rename to...
(avx10_2_minmaxbf16_<mode><mask_name>): ...this. Change
instruction name output.
2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
PR target/118270
* config/i386/avx10_2-512bf16intrin.h: Change intrin and builtin
name according to new mnemonics.
* config/i386/avx10_2bf16intrin.h: Ditto.
* config/i386/i386-builtin.def (BDESC): Ditto.
* config/i386/sse.md
(avx10_2_<code>pbf16_<mode><mask_name>): Rename to...
(avx10_2_<code>bf16_<mode><mask_name>): ...this.
Change instruction name output.
(avx10_2_cmppbf16_<mode><mask_scalar_merge_name>): Rename to...
(avx10_2_cmpbf16_<mode><mask_scalar_merge_name>): ...this.
Change instruction name output.
2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
PR target/118270
* config/i386/avx10_2-512bf16intrin.h: Change intrin and builtin
names according to new mnemonics.
* config/i386/avx10_2bf16intrin.h: Ditto.
* config/i386/i386-builtin.def (BDESC): Ditto.
* config/i386/sse.md
(avx10_2_fmaddnepbf16_<mode>_maskz): Rename to...
(avx10_2_fmaddbf16_<mode>_maskz): ...this. Adjust emit_insn.
(avx10_2_fmaddnepbf16_<mode><sd_maskz_name>): Rename to...
(avx10_2_fmaddbf16_<mode><sd_maskz_name>): ...this.
Change instruction name output.
(avx10_2_fmaddnepbf16_<mode>_mask): Rename to...
(avx10_2_fmaddbf16_<mode>_mask): ...this.
Change instruction name output.
(avx10_2_fmaddnepbf16_<mode>_mask3): Rename to...
(avx10_2_fmaddbf16_<mode>_mask3): ...this.
Change instruction name output.
(avx10_2_fnmaddnepbf16_<mode>_maskz): Rename to...
(avx10_2_fnmaddbf16_<mode>_maskz): ...this. Adjust emit_insn.
(avx10_2_fnmaddnepbf16_<mode><sd_maskz_name>): Rename to...
(avx10_2_fnmaddbf16_<mode><sd_maskz_name>): ...this.
Change instruction name output.
(avx10_2_fnmaddnepbf16_<mode>_mask): Rename to...
(avx10_2_fnmaddbf16_<mode>_mask): ...this.
Change instruction name output.
(avx10_2_fnmaddnepbf16_<mode>_mask3): Rename to...
(avx10_2_fnmaddbf16_<mode>_mask3): ...this.
Change instruction name output.
(avx10_2_fmsubnepbf16_<mode>_maskz): Rename to...
(avx10_2_fmsubbf16_<mode>_maskz): ...this. Adjust emit_insn.
(avx10_2_fmsubnepbf16_<mode><sd_maskz_name>): Rename to...
(avx10_2_fmsubbf16_<mode><sd_maskz_name>): ...this.
Change instruction name output.
(avx10_2_fmsubnepbf16_<mode>_mask): Rename to...
(avx10_2_fmsubbf16_<mode>_mask): ...this.
Change instruction name output.
(avx10_2_fmsubnepbf16_<mode>_mask3): Rename to...
(avx10_2_fmsubbf16_<mode>_mask3): ...this.
Change instruction name output.
(avx10_2_fnmsubnepbf16_<mode>_maskz): Rename to...
(avx10_2_fnmsubbf16_<mode>_maskz): ...this. Adjust emit_insn.
(avx10_2_fnmsubnepbf16_<mode><sd_maskz_name>): Rename to...
(avx10_2_fnmsubbf16_<mode><sd_maskz_name>): ...this.
Change instruction name output.
(avx10_2_fnmsubnepbf16_<mode>_mask): Rename to...
(avx10_2_fnmsubbf16_<mode>_mask): ...this.
Change instruction name output.
(avx10_2_fnmsubnepbf16_<mode>_mask3): Rename to...
(avx10_2_fnmsubbf16_<mode>_mask3): ...this.
Change instruction name output.
2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
PR target/118270
* config/i386/avx10_2-512bf16intrin.h: Change intrin and builtin
name according to new mnemonics.
* config/i386/avx10_2bf16intrin.h: Ditto.
* config/i386/i386-builtin.def (BDESC): Ditto.
* config/i386/sse.md (div<mode>3): Adjust emit_insn.
(avx10_2_<insn>nepbf16_<mode><mask_name>): Rename to...
(avx10_2_<insn>bf16_<mode><mask_name>): ...this. Change
instruction name output.
(avx10_2_rcppbf16_<mode><mask_name>): Rename to...
(avx10_2_rcpbf16_<mode><mask_name>):...this. Change
instruction name output.
2025-01-22 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* config/s390/s390.cc: Fix arch15 machine string which must not
be empty.
2025-01-22 Richard Sandiford <richard.sandiford@arm.com>
* config/aarch64/aarch64.md (aarch64_read_sysregti): Change
the source predicate to aarch64_reg_or_zero.
2025-01-22 Xi Ruoyao <xry111@xry111.site>
* config/loongarch/loongarch.md
(<optab>_alsl_reversesi_extended): Add '&' to the destination
register constraint and append '0' to the first source register
constraint to indicate the destination register cannot be same
as the second source register, and change the split condition to
reload_completed so that the insn will be split only after RA in
order to obtain allocated registers that satisfy the above
constraints.
2025-01-21 Jeff Law <jlaw@ventanamicro.com>
Revert:
2024-10-29 yulong <shiyulong@iscas.ac.cn>
* config.gcc: Add riscv_cmo.h.
* config/riscv/riscv_cmo.h: New file.
2025-01-21 Andrew Pinski <quic_apinski@quicinc.com>
PR tree-optimization/118483
* match.pd (`x ==/!= ~x`): Allow for an optional convert
and use itwise_inverted_equal_p/maybe_bit_not instead of
directly matching bit_not.
2025-01-21 Robin Dapp <rdapp@ventanamicro.com>
* config/riscv/riscv.cc (riscv_file_end): Fix format string.
(riscv_lshift_subword): Mark MODE as unused.
2025-01-21 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr-passes.cc (avr_emit_shift) [ASHIFT,HImode]:
Allow offsets 5 and 6 as 3op provided have MUL and a scratch.
* config/avr/avr.cc (avr_optimize_size_max_p): New function.
(avr_out_ashlhi3_mul): New function.
(ashlhi3_out) [case 4, 5, 6]: Better speed for -Os.
* config/avr/avr.md (isa) <mul, no_mul>: New attr values.
(*ashlhi3_const): Add alternative for offsets 5 and 6.
2025-01-21 Jin Ma <jinma@linux.alibaba.com>
PR target/116593
* config/riscv/constraints.md (vl): New.
* config/riscv/thead-vector.md: Replacing rK with rvl.
* config/riscv/vector.md: Likewise.
2025-01-21 Denis Chertykov <chertykov@gmail.com>
* lra-spills.cc (assign_stack_slot_num_and_sort_pseudos): Use known_ge
to compare sizes.
2025-01-21 Jeff Law <jlaw@ventanamicro.com>
PR target/116256
* config/riscv/predicates.md (consecutive_bits_operand): Properly
handle (const_int 0).
2025-01-21 Alfie Richards <alfie.richards@arm.com>
* config/aarch64/aarch64.opt.urls: Regenerate
2025-01-21 Richard Biener <rguenther@suse.de>
PR tree-optimization/118569
* cfgloopmanip.cc (fix_loop_placement): When the loops
nesting parents changed, mark all blocks to be scanned
for LC PHI uses.
(fix_bb_placements): Remove code moved into fix_loop_placement.
2025-01-21 Vladimir Miloserdov <vladimir.miloserdov@arm.com>
* config/aarch64/aarch64-c.cc
(aarch64_update_cpp_builtins): Add new flag TARGET_LUT.
* config/aarch64/aarch64-sve-builtins-shapes.cc
(struct luti_base): Shape for lut intrinsics.
(SHAPE): Specializations for lut shapes for luti2 and luti4..
* config/aarch64/aarch64-sve-builtins-shapes.h: Declare lut
intrinsics.
* config/aarch64/aarch64-sve-builtins-sve2.cc
(class svluti_lane_impl): Define expand for lut intrinsics.
(FUNCTION): Define expand for lut intrinsics.
* config/aarch64/aarch64-sve-builtins-sve2.def
(REQUIRED_EXTENSIONS): Declare lut intrinsics behind lut flag.
(svluti2_lane): Define intrinsic behind flag.
(svluti4_lane): Define intrinsic behind flag.
* config/aarch64/aarch64-sve-builtins-sve2.h: Declare lut
intrinsics.
* config/aarch64/aarch64-sve-builtins.cc
(TYPES_bh_data): New type for byte and halfword.
(bh_data): Type array for byte and halfword.
(h_data): Type array for halfword.
* config/aarch64/aarch64-sve2.md
(@aarch64_sve_luti<LUTI_BITS><mode>): Instruction patterns for
lut intrinsics.
* config/aarch64/iterators.md: Iterators and attributes for lut
intrinsics.
2025-01-21 Tamar Christina <tamar.christina@arm.com>
PR middle-end/118273
* tree-vect-stmts.cc (vectorizable_simd_clone_call): Use nvectors when
doing mask registrations.
2025-01-21 Tamar Christina <tamar.christina@arm.com>
* config.gcc (aarch64-*-elf): Drop ILP32 from default multilibs.
2025-01-21 Lulu Cheng <chenglulu@loongson.cn>
* config/loongarch/loongarch-protos.h
(loongarch_reset_previous_fndecl): Add function declaration.
(loongarch_save_restore_target_globals): Likewise.
(loongarch_register_pragmas): Likewise.
* config/loongarch/loongarch-target-attr.cc
(loongarch_option_valid_attribute_p): Optimize the processing
of attributes.
(loongarch_pragma_target_parse): New functions.
(loongarch_register_pragmas): Likewise.
* config/loongarch/loongarch.cc
(loongarch_reset_previous_fndecl): New functions.
(loongarch_set_current_function): When the old_tree is the same
as the new_tree, the rules for using registers, etc.,
are set according to the option values to ensure that the
pragma can be processed correctly.
* config/loongarch/loongarch.h (REGISTER_TARGET_PRAGMAS):
Define macro.
* doc/extend.texi: Supplemental Documentation.
2025-01-21 Lulu Cheng <chenglulu@loongson.cn>
* attr-urls.def: Regenerate.
* config.gcc: Add loongarch-target-attr.o to extra_objs.
* config/loongarch/loongarch-protos.h
(loongarch_option_valid_attribute_p): Function declaration.
(loongarch_option_override_internal): Likewise.
* config/loongarch/loongarch.cc
(loongarch_option_override_internal): Delete the modifications
to target_option_default_node and target_option_current_node.
(loongarch_set_current_function): Add annotation information.
(loongarch_option_override): add assignment operations to
target_option_default_node and target_option_current_node.
(TARGET_OPTION_VALID_ATTRIBUTE_P): Define.
* config/loongarch/t-loongarch: Add compilation of target file
loongarch-target-attr.o.
* doc/extend.texi: Add description information of LoongArch
Function Attributes.
* config/loongarch/loongarch-target-attr.cc: New file.
2025-01-21 Alfie Richards <alfie.richards@arm.com>
* config/aarch64/aarch64.cc
(aarch64_process_target_version_attr): Add experimental warning.
* config/aarch64/aarch64.opt: Add command line option to disable
warning.
* doc/invoke.texi: Add documentation for -W[no-]experimental-fmv-target.
2025-01-20 Vladimir N. Makarov <vmakarov@redhat.com>
PR target/118560
* lra-constraints.cc (invalid_mode_reg_p): Exchange args in
hard_reg_set_subset_p call.
2025-01-20 Jeff Law <jlaw@ventanamicro.com>
PR target/114442
* config/riscv/xiangshan.md: Add missing insn types to a
new dummy insn reservation.
2025-01-20 Jeff Law <jlaw@ventanamicro.com>
PR target/116256
* config/riscv/riscv.md (reassocating constant addition): Adjust
condition to avoid creating an unrecognizable insn.
2025-01-20 Denis Chertykov <chertykov@gmail.com>
PR rtl-optimization/117868
* lra-spills.cc (assign_stack_slot_num_and_sort_pseudos): Reuse slots
only without allocated memory or only with equal or smaller registers
with equal or smaller alignment.
(lra_spill): Print slot size as width.
2025-01-20 Richard Sandiford <richard.sandiford@arm.com>
PR tree-optimization/118348
* tree-vectorizer.cc (vec_info::move_dr): Copy
STMT_VINFO_SIMD_LANE_ACCESS_P.
2025-01-20 Richard Sandiford <richard.sandiford@arm.com>
Revert:
2025-01-20 Richard Sandiford <richard.sandiford@arm.com>
PR tree-optimization/118384
* tree-vectorizer.cc (vec_info::move_dr): Copy
STMT_VINFO_SIMD_LANE_ACCESS_P.
2025-01-20 Richard Sandiford <richard.sandiford@arm.com>
PR tree-optimization/118384
* tree-vectorizer.cc (vec_info::move_dr): Copy
STMT_VINFO_SIMD_LANE_ACCESS_P.
2025-01-20 Richard Sandiford <richard.sandiford@arm.com>
PR target/118501
* config/aarch64/aarch64.md (@xorsign<mode>3): Use
force_lowpart_subreg.
2025-01-20 Richard Sandiford <richard.sandiford@arm.com>
PR target/118531
* config/aarch64/aarch64.md (*insv_reg<mode>_<SUBDI_BITS>)
(*aarch64_bfi<GPI:mode><ALLX:mode>_<SUBDI_BITS>)
(*aarch64_bfidi<ALLX:mode>_subreg_<SUBDI_BITS>): Add missing
simd requirements.
2025-01-20 Jin Ma <jinma@linux.alibaba.com>
* config/riscv/thead.md (*th_cond_mov<GPR:mode><GPR2:mode>):
Change GPR2 to X.
(*th_cond_mov<GPR:mode>): Likewise.
2025-01-20 Andrew Pinski <quic_apinski@quicinc.com>
PR tree-optimization/118077
PR tree-optimization/117668
* tree-inline.cc (fold_marked_statements): Purge abnormal edges
as needed.
2025-01-20 Richard Biener <rguenther@suse.de>
PR tree-optimization/117875
* tree-vect-slp.cc (vect_build_slp_tree_1): Handle SSA copies.
2025-01-20 Xi Ruoyao <xry111@xry111.site>
PR target/115921
* config/loongarch/loongarch-protos.h
(loongarch_reassoc_shift_bitwise): New function prototype.
* config/loongarch/loongarch.cc
(loongarch_reassoc_shift_bitwise): Implement.
* config/loongarch/loongarch.md
(*alslsi3_extend_subreg): New define_insn_and_split.
(<any_bitwise:optab>_shift_reverse<X:mode>): New
define_insn_and_split.
(<any_bitwise:optab>_alsl_reversesi_extended): New
define_insn_and_split.
(zero_extend_ashift): Remove as it's just a special case of
and_shift_reversedi, and it does not make too much sense to
write "alsl.d rd,rs,r0,shamt" instead of "slli.d rd,rs,shamt".
(bstrpick_alsl_paired): Remove as it is already done by
splitting and_shift_reversedi into and + ashift first, then
late combining the ashift and a further add.
2025-01-20 Xi Ruoyao <xry111@xry111.site>
* config/loongarch/constraints.md (Yy): New define_constriant.
* config/loongarch/loongarch.cc (loongarch_print_operand):
For "%M", output the index of bits to be used with
bstrins/bstrpick.
* config/loongarch/predicates.md (ins_zero_bitmask_operand):
Exclude low_bitmask_operand as for low_bitmask_operand it's
always better to use bstrpick instead of bstrins.
(and_operand): New define_predicate.
* config/loongarch/loongarch.md (any_or): New
define_code_iterator.
(bitwise_operand): New define_code_attr.
(*<optab:any_or><mode:GPR>3): New define_insn.
(*and<mode:GPR>3): New define_insn.
(<optab:any_bitwise><mode:X>3): New define_expand.
(and<mode>3_extended): Remove, replaced by the 3rd alternative
of *and<mode:GPR>3.
(bstrins_<mode>_for_mask): Remove, replaced by the 4th
alternative of *and<mode:GPR>3.
(*<optab:any_bitwise>si3_internal): Remove, already covered by
the *<optab:any_or><mode:GPR>3 and *and<mode:GPR>3 templates.
2025-01-20 Richard Biener <rguenther@suse.de>
PR tree-optimization/118552
* cfgloopmanip.cc (fix_loop_placement): Properly mark
exit source blocks as to be scanned for LC SSA update when
the loops nesting relationship changed.
(fix_loop_placements): Adjust.
(fix_bb_placements): Likewise.
2025-01-20 Thomas Schwinge <tschwinge@baylibre.com>
* config/nvptx/t-nvptx (MULTILIB_OPTIONS): Don't add 'mptx=3.1' if
neither sm_30 nor sm_35 multilib variant is built.
2025-01-20 Jakub Jelinek <jakub@redhat.com>
PR c++/118509
* tree.cc (tree_invariant_p_1): Return true for TARGET_EXPR too.
2025-01-20 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/118224
* tree-ssa-dce.cc (is_removable_allocation_p): Multiply a1 by a2
instead of adding it.
2025-01-20 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* config/s390/s390-builtins.def (s390_vec_load_len): Deprecate
some overloads.
(s390_vec_store_len): Deprecate some overloads.
(s390_vec_load_len_r): Add.
(s390_vec_store_len_r): Add.
* config/s390/s390-c.cc (s390_vec_load_len_r): Add.
(s390_vec_store_len_r): Add.
* config/s390/vecintrin.h (vec_load_len_r): Redefine.
(vec_store_len_r): Redefine.
2025-01-20 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* config/s390/s390-builtins.def: Add 128-bit variants.
* config/s390/s390-builtin-types.def: Update accordingly.
* config/s390/vector.md (<vec_shifts_name><mode>3): Add 128-bit
variants.
* config/s390/vx-builtins.md: Ditto.
2025-01-20 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* config/s390/s390-builtins.def: Add 128-bit variants and remove
bool variants.
* config/s390/s390-builtin-types.def: Update accordinly.
* config/s390/s390.md: Emulate min/max for GPR.
* config/s390/vector.md: Add min/max patterns and emulate in
case of no VXE3.
2025-01-20 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* config/s390/s390-builtins.def (s390_vec_abs_s128): Add.
(s390_vlpq): Add.
* config/s390/s390-builtin-types.def: Update accordingly.
* config/s390/vector.md (abs<mode>2): Emulate w/o VXE3.
(*abs<mode>2): Add 128-bit variant.
(*vec_sel0<mode>): Make it a ...
(vec_sel0<mode>): named pattern.
2025-01-20 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* config/s390/s390-builtins.def: Add 128-bit variants.
* config/s390/s390-builtin-types.def: Update accordingly.
* config/s390/s390.cc (s390_expand_vec_compare_cc): Also
consider TI modes for vectors.
* config/s390/vector.md: Enable *vec_cmp et al. for VXE3.
* config/s390/vx-builtins.md: Ditto.
2025-01-20 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* config/s390/vector.md (div<mode>3): Add.
(udiv<mode>3): Add.
(mod<mode>3): Add.
(umod<mode>3): Add.
2025-01-20 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* config/s390/s390-builtins.def (s390_vec_cntlz): Add 128-bit
integer overloads.
(s390_vclzq): Add.
(s390_vec_cnttz): Add 128-bit integer overloads.
(s390_vctzq): Add.
* config/s390/s390-builtin-types.def: Update accordingly.
* config/s390/s390.h (CTZ_DEFINED_VALUE_AT_ZERO): Define.
* config/s390/s390.md (*clzg): New insn.
(clztidi2): Exploit new insn for target arch15.
(ctzdi2): New insn.
* config/s390/vector.md (clz<mode>2): Extend modes including
128-bit integer.
(ctz<mode>2): Likewise.
2025-01-20 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* config/s390/s390-builtins.def (s390_vec_gen_element_masks_128): Add.
(s390_vgemb): Add.
(s390_vgemh): Add.
(s390_vgemf): Add.
(s390_vgemg): Add.
(s390_vgemq): Add.
* config/s390/s390-builtin-types.def: Update accordingly.
* config/s390/s390.md (UNSPEC_VEC_VGEM): Add.
* config/s390/vecintrin.h (vec_gen_element_masks_8): Define.
(vec_gen_element_masks_16): Define.
(vec_gen_element_masks_32): Define.
(vec_gen_element_masks_64): Define.
(vec_gen_element_masks_128): Define.
* config/s390/vx-builtins.md (vgemv16qi): Add.
(vgem<mode>): Add.
2025-01-20 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* config/s390/s390-builtins.def (s390_vec_evaluate): Add.
(s390_veval): Add.
* config/s390/s390-builtin-types.def: Update accordingly.
* config/s390/s390.md (UNSPEC_VEC_VEVAL): Add.
* config/s390/vecintrin.h (vec_evaluate): Define.
* config/s390/vector.md
(*veval<mode>_<logic_op1:logic_op_stringify><logic_op2:logic_op_stringify>):
Add.
(veval<mode>): Add.
2025-01-20 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* config/s390/s390-builtins.def (s390_vec_blend): Add.
(s390_vblendb): Add.
(s390_vblendh): Add.
(s390_vblendf): Add.
(s390_vblendg): Add.
(s390_vblendq): Add.
* config/s390/s390-builtin-types.def: Update accordingly.
* config/s390/s390.md (UNSPEC_VEC_VBLEND): Add.
* config/s390/vecintrin.h (vec_blend): Define.
* config/s390/vx-builtins.md (vblend<mode>): Add.
2025-01-20 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* config/s390/s390-builtins.def (s390_bdepg): Add.
(s390_bextg): Add.
* config/s390/s390-builtin-types.def: Update accordingly.
* config/s390/s390.md (UNSPEC_BDEPG): Add.
(UNSPEC_BEXTG): Add.
(bdepg): Add.
(bextg): Add.
2025-01-20 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* config/s390/s390.md (*lxa<LXAMODE>_index): Add.
(*lxa<LXAMODE>_displacement_index): Add.
(*lxa<LXAMODE>_index_base): Add.
(*lxa<LXAMODE>_displacement_index_base): Add.
(*lxab_displacement_index_base): Add.
(*llxa<LXAMODE>_displacement_index): Add.
(*llxa<LXAMODE>_index_base): Add.
(*llxa<LXAMODE>_displacement_index_base): Add.
(*llxab_displacement_index_base): Add.
2025-01-20 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* config/s390/s390-builtins.def: Add new instruction variants.
* config/s390/s390-builtin-types.def: Update accordingly.
* config/s390/vecintrin.h: Add new defines.
* config/s390/vector.md: Adapt insns for new instruction
variants.
* config/s390/vx-builtins.md: Ditto.
2025-01-20 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
* config/s390/s390-builtins.def (B_VXE3): Define.
(B_ARCH15): Define.
* config/s390/s390-c.cc (s390_resolve_overloaded_builtin):
Consistency checks for VXE3.
* config/s390/s390.cc (s390_expand_builtin): Consistency checks
for VXE3.
2025-01-20 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
* config/s390/s390-c.cc (rid_int128): New helper function.
(s390_macro_to_expand): Deal with `vector __int128`.
(s390_cpu_cpp_builtins_internal): Bump __VEC__.
* config/s390/s390.cc (s390_handle_vectorbool_attribute): Add
128-bit bool zvector.
2025-01-20 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
* common/config/s390/s390-common.cc: Add arch15 processor flags.
* config.gcc: Add arch15 for options --with-{arch,mtune}.
* config/s390/driver-native.cc (s390_host_detect_local_cpu):
Default to arch15.
* config/s390/s390-opts.h (enum processor_type): Add
PROCESSOR_ARCH15.
* config/s390/s390.cc (processor_table,s390_issue_rate,
s390_get_sched_attrmask,s390_get_unit_mask): Add arch15.
* config/s390/s390.h (enum processor_flags): Add processor flags
for VXE3 and ARCH15.
(TARGET_CPU_VXE3): Define.
(TARGET_CPU_VXE3_P): Define.
(TARGET_CPU_ARCH15): Define.
(TARGET_CPU_ARCH15_P): Define.
(TARGET_VXE3): Define.
(TARGET_VXE3_P): Define.
(TARGET_ARCH15): Define.
(TARGET_ARCH15_P): Define.
* config/s390/s390.md: Add VXE3 and ARCH15 to cpu_facility, and
let attribute "enabled" deal with them.
* config/s390/s390.opt: Add arch15.
2025-01-20 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
* config/s390/vecintrin.h: Sort definitions.
2025-01-20 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* config/s390/vector.md: Stay scalar for TOINTVEC/tointvec.
2025-01-20 Kito Cheng <kito.cheng@sifive.com>
* config.gcc (riscv*): Install sifive_vector.h.
* config/riscv/sifive_vector.h: New.
2025-01-20 Hongyu Wang <hongyu.wang@intel.com>
PR target/118510
* config/i386/i386.md (*x86_64_shld_ndd_2): Use register_operand
for operand[0] and adjust the output template to directly
generate ndd form shld pattern.
(*x86_shld_ndd_2): Likewise.
(*x86_64_shrd_ndd_2): Likewise.
(*x86_shrd_ndd_2): Likewise.
2025-01-19 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (*movdi_internal): Reorder ISA attribute
by ascending alternative index.
2025-01-19 Mark Wielaard <mark@klomp.org>
* config/sparc/sparc.opt.urls: Regenerated.
2025-01-19 Gerald Pfeifer <gerald@pfeifer.com>
* doc/gm2.texi (Type compatibility): Move modula2.org link
to https.
2025-01-19 Gerald Pfeifer <gerald@pfeifer.com>
* doc/extend.texi (OpenMP): Adjust link to specifications.
2025-01-18 Jeff Law <jlaw@ventanamicro.com>
PR target/116308
* config/riscv/riscv.cc (riscv_lshift_subword): Use gen_lowpart
rather than simplify_gen_subreg.
2025-01-18 Michal Jires <mjires@suse.cz>
* cgraph.cc (symbol_table::create_empty):
Move uid to symtab_node.
(test_symbol_table_test): Change expected dump id.
* cgraph.h (struct cgraph_node):
Move uid to symtab_node.
(symbol_table::register_symbol): Likewise.
* dumpfile.cc (test_capture_of_dump_calls):
Change expected dump id.
* ipa-inline.cc (update_caller_keys):
Use summary id instead of uid.
(update_callee_keys): Likewise.
* symtab.cc (symtab_node::get_dump_name):
Use uid instead of order.
2025-01-18 Eric Botcazou <ebotcazou@adacore.com>
PR target/118512
* config/sparc/sparc-c.cc (sparc_target_macros): Deal with VIS 3B.
* config/sparc/sparc.cc (dump_target_flag_bits): Likewise.
(sparc_option_override): Likewise.
(sparc_vis_init_builtins): Likewise.
* config/sparc/sparc.md (fpcmp_vis): Replace TARGET_VIS3 with
TARGET_VIS3B.
(vec_cmp): Likewise.
(fpcmpu_vis): Likewise.
(vec_cmpu): Likewise.
(vcond_mask_): Likewise.
* config/sparc/sparc.opt (VIS3B): New target mask.
* doc/invoke.texi (SPARC options): Document -mvis3b.
2025-01-18 Jin Ma <jinma@linux.alibaba.com>
PR target/118357
* config/riscv/riscv-vsetvl.cc: Function change_vtype_only_p always
returns false for XTheadVector.
2025-01-18 Richard Biener <rguenther@suse.de>
PR tree-optimization/118529
* tree-vect-stmts.cc (vectorizable_condition): Check the
shape of the vector and condition vector type are compatible.
2025-01-18 Georg-Johann Lay <avr@gjlay.de>
* doc/invoke.texi (AVR Options): Fix plenk at -msplit-ldst.
2025-01-18 Akram Ahmad <Akram.Ahmad@arm.com>
Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64-builtins.cc: Expand iterators.
* config/aarch64/aarch64-simd-builtins.def: Use standard names
* config/aarch64/aarch64-simd.md: Use standard names, split insn
definitions on signedness of operator and type of operands.
* config/aarch64/arm_neon.h: Use standard builtin names.
* config/aarch64/iterators.md: Add VSDQ_I_QI_HI iterator to
simplify splitting of insn for unsigned scalar arithmetic.
2025-01-18 Akram Ahmad <Akram.Ahmad@arm.com>
* config/aarch64/aarch64-sve.md: Rename insns
2025-01-18 Tamar Christina <tamar.christina@arm.com>
Revert:
2025-01-17 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64-builtins.cc: Expand iterators.
* config/aarch64/aarch64-simd-builtins.def: Use standard names
* config/aarch64/aarch64-simd.md: Use standard names, split insn
definitions on signedness of operator and type of operands.
* config/aarch64/arm_neon.h: Use standard builtin names.
* config/aarch64/iterators.md: Add VSDQ_I_QI_HI iterator to
simplify splitting of insn for unsigned scalar arithmetic.
2025-01-18 Tamar Christina <tamar.christina@arm.com>
Revert:
2025-01-17 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64-sve.md: Rename insns
2025-01-18 Monk Chiang <monk.chiang@sifive.com>
* config/riscv/riscv.cc: Remove unused variable.
2025-01-18 Xi Ruoyao <xry111@xry111.site>
* config/loongarch/loongarch.cc (loongarch_rtx_costs): Fix the
cost for (a + b * imm) and (a + (b << imm)) which can be
implemented with a single alsl instruction.
2025-01-18 Xi Ruoyao <xry111@xry111.site>
* config/loongarch/loongarch.md (alslsi3_extend): Add alsl.wu.
2025-01-17 Vladimir N. Makarov <vmakarov@redhat.com>
PR rtl-optimization/118067
* lra-constraints.cc (invalid_mode_reg_p): New function.
(curr_insn_transform): Use it to check mode returned by target
secondary_memory_needed_mode.
2025-01-17 Jakub Jelinek <jakub@redhat.com>
PR target/118511
* config/s390/s390.cc (print_operand) <case 'p'>: Use
output_operand_lossage instead of gcc_checking_assert.
(print_operand) <case 'q'>: Likewise.
(print_operand) <case 'r'>: Likewise.
2025-01-17 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64-sve.md: Rename insns
2025-01-17 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64-builtins.cc: Expand iterators.
* config/aarch64/aarch64-simd-builtins.def: Use standard names
* config/aarch64/aarch64-simd.md: Use standard names, split insn
definitions on signedness of operator and type of operands.
* config/aarch64/arm_neon.h: Use standard builtin names.
* config/aarch64/iterators.md: Add VSDQ_I_QI_HI iterator to
simplify splitting of insn for unsigned scalar arithmetic.
2025-01-17 Carl Love <cel@linux.ibm.com>
* config/rs6000/rs6000-builtins.def (__builtin_vsx_xvcvuxwdp):
Remove built-in definition.
2025-01-17 Carl Love <cel@linux.ibm.com>
* config/rs6000/rs6000-builtins.def (__builtin_vsx_vperm_8hi,
__builtin_vsx_vperm_8hi_uns): Remove built-in definitions.
2025-01-17 Carl Love <cel@linux.ibm.com>
* doc/extend.texi: Fix spelling mistake in description of the
vec_sel built-in. Add documentation of the 128-bit vec_perm
instance.
2025-01-17 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr-c.cc (DEF_BUILTIN): Add ATTRS argument to macro
definition.
* config/avr/avr.cc: Same.
(avr_init_builtins) <attr_const>: New variable that can be used
as ATTRS argument in DEF_BUILTIN.
* config/avr/builtins.def (DEF_BUILTIN): Add ATTRS parameter
to all definitions.
2025-01-17 Georg-Johann Lay <avr@gjlay.de>
PR target/118329
* config/avr/avr-modes.def: Add INT_N (PSI, 24).
* config/avr/avr.cc (avr_init_builtin_int24)
<__int24>: Remove definition.
<__uint24>: Adjust definition to INT_N interface.
2025-01-17 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/118522
* match.pd ((FTYPE) N CMP (FTYPE) M): Add convert, as in GENERIC
integral types with the same precision and sign might actually not
be compatible types.
2025-01-17 Richard Biener <rguenther@suse.de>
PR tree-optimization/92539
* tree-ssa-loop-ivcanon.cc (tree_unroll_loops_completely_1):
Also try force-evaluation if ivcanon did not yet run.
(canonicalize_loop_induction_variables):
When niter was computed constant by force evaluation add a
canonical IV if we didn't unroll.
* tree-ssa-loop-niter.cc (loop_niter_by_eval): When we
don't find a proper PHI try if the exit condition scans
over a STRING_CST and simulate that.
2025-01-17 Monk Chiang <monk.chiang@sifive.com>
* config/riscv/riscv.cc
(is_zicfilp_p): New function.
(is_zicfiss_p): New function.
* config/riscv/riscv-zicfilp.cc: Update.
* config/riscv/riscv.h: Update.
* config/riscv/riscv.md: Update.
* config/riscv/riscv-c.cc: Add CFI predefine marco.
2025-01-17 Monk Chiang <monk.chiang@sifive.com>
* config/riscv/riscv.cc
(riscv_file_end): Add .note.gnu.property.
2025-01-17 Monk Chiang <monk.chiang@sifive.com>
* common/config/riscv/riscv-common.cc: Add ZICFILP ISA
string.
* config.gcc: Add riscv-zicfilp.o
* config/riscv/riscv-passes.def (INSERT_PASS_BEFORE):
Insert landing pad instructions.
* config/riscv/riscv-protos.h (make_pass_insert_landing_pad):
Declare.
* config/riscv/riscv-zicfilp.cc: New file.
* config/riscv/riscv.cc
(riscv_trampoline_init): Add landing pad instructions.
(riscv_legitimize_call_address): Likewise.
(riscv_output_mi_thunk): Likewise.
* config/riscv/riscv.h: Update.
* config/riscv/riscv.md: Add landing pad patterns.
* config/riscv/riscv.opt (TARGET_ZICFILP): Define.
* config/riscv/t-riscv: Add build rule for
riscv-zicfilp.o
2025-01-17 Monk Chiang <monk.chiang@sifive.com>
* common/config/riscv/riscv-common.cc: Add ZICFISS ISA string.
* config/riscv/predicates.md: New predicate x1x5_operand.
* config/riscv/riscv.cc
(riscv_expand_prologue): Insert shadow stack instructions.
(riscv_expand_epilogue): Likewise.
(riscv_for_each_saved_reg): Assign t0 or ra register for
sspopchk instruction.
(need_shadow_stack_push_pop_p): New function. Omit shadow
stack operation on leaf function.
* config/riscv/riscv.h
(need_shadow_stack_push_pop_p): Define.
* config/riscv/riscv.md: Add shadow stack patterns.
(save_stack_nonlocal): Add shadow stack instructions for setjump.
(restore_stack_nonlocal): Add shadow stack instructions for longjump.
* config/riscv/riscv.opt (TARGET_ZICFISS): Define.
2025-01-16 Tamar Christina <tamar.christina@arm.com>
Richard Sandiford <richard.sandiford@arm.com>
PR target/113257
* config/aarch64/driver-aarch64.cc (get_cpu_from_id, DEFAULT_CPU): New.
(host_detect_local_cpu): Use it.
2025-01-16 Tamar Christina <tamar.christina@arm.com>
PR target/110901
* config/aarch64/aarch64.h (MCPU_TO_MARCH_SPEC): Don't override if
march is set.
2025-01-16 Vladimir N. Makarov <vmakarov@redhat.com>
PR rtl-optimization/1180167
* lra-constraints.cc (process_alt_operands): Use operand mode not
subreg reg mode. Add and improve debugging prints for updating
losers.
2025-01-16 Sandra Loosemore <sloosemore@baylibre.com>
* omp-general.cc (omp_complete_construct_context): Check
"omp declare target" attribute, not "omp declare target block".
2025-01-16 Peter Bergner <bergner@linux.ibm.com>
* config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin): Return
const0_rtx when there is an error.
2025-01-16 Peter Bergner <bergner@linux.ibm.com>
* config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin): Use correct
array size for the loop limit.
* config/rs6000/rs6000-builtins.def: Fix field size for PMASK operand.
2025-01-16 Liao Shihua <shihua@iscas.ac.cn>
* config/riscv/vector.md: New attr set.
2025-01-16 Jiawei <jiawei@iscas.ac.cn>
* config/riscv/genrvv-type-indexer.cc (expand_floattype): New func.
(main): New type.
* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_XFQF_OPS): New def.
(vint8mf8_t): Ditto.
(vint8mf4_t): Ditto.
(vint8mf2_t): Ditto.
(vint8m1_t): Ditto.
(vint8m2_t): Ditto.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_XFQF_OPS): Ditto.
(rvv_arg_type_info::get_xfqf_float_type): Ditto.
* config/riscv/riscv-vector-builtins.def (xfqf_vector): Ditto.
(xfqf_float): Ditto.
* config/riscv/riscv-vector-builtins.h
(struct rvv_arg_type_info): New function prototype.
* config/riscv/sifive-vector.md: Update iterator.
* config/riscv/vector-iterators.md: Ditto.
2025-01-16 Christoph Müllner <christoph.muellner@vrull.eu>
PR tree-optimization/118487
* tree-ssa-forwprop.cc (recognise_vec_perm_simplify_seq):
Ensure that shuffle masks are VECTOR_CSTs.
2025-01-16 Christoph Müllner <christoph.muellner@vrull.eu>
* tree-ssa-forwprop.cc (recognise_vec_perm_simplify_seq):
Eliminate redundant calls to to_constant().
2025-01-16 Richard Biener <rguenther@suse.de>
Mikael Morin <mikael@gcc.gnu.org>
PR tree-optimization/115494
* tree-ssa-pre.cc (phi_translate_1): Always generate a
representative for translated dependent expressions.
2025-01-16 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/118430
* tree-ssa-propagate.cc (may_propagate_copy): Return false if dest
is lhs of an [[gnu::musttail]] call.
(substitute_and_fold_dom_walker::before_dom_children): Formatting fix.
2025-01-16 Jakub Jelinek <jakub@redhat.com>
Andrew Pinski <quic_apinski@quicinc.com>
PR tree-optimization/118430
* tree-tailcall.cc: Include gimple-range.h, alloc-pool.h, sreal.h,
symbol-summary.h, ipa-cp.h and ipa-prop.h.
(find_tail_calls): If ass_var is NULL and ret_var is not, check if
IPA-VRP has not found singleton return range for it. In that case,
don't punt if ret_var is the only value in that range. Adjust the
maybe_error_musttail message otherwise to diagnose different value
being returned from the caller and callee rather than using return
slot. Formatting fixes.
2025-01-16 Jakub Jelinek <jakub@redhat.com>
* doc/extend.texi (Using Assembly Language with C): Add Asm constexprs
to @menu.
(Basic Asm): Move @node asm constexprs before Asm Labels, rename to
Asm constexprs, change wording so that it is clearer that the constant
expression actually must not return a string literal, just some specific
container and other wording tweaks. Only talk about top-level for basic
asms in this @node, move restrictions on top-level extended asms to ...
(Extended Asm): ... here.
2025-01-16 Jakub Jelinek <jakub@redhat.com>
PR ipa/118400
* vec.h (vec<T, va_heap, vl_ptr>::release): Call m_vec->truncate (0)
instead of clearing m_vec->m_vecpfx.m_num.
2025-01-16 liuhongt <hongtao.liu@intel.com>
PR target/118489
* config/i386/sse.md (VF1_AVX512BW): Fix typo.
2025-01-16 Richard Biener <rguenther@suse.de>
PR tree-optimization/115895
* tree-vect-stmts.cc (get_group_load_store_type): When we
might overrun because the group size is not a multiple of the
vector size we cannot use loop masking since that does not
implement the required load shortening.
2025-01-16 Keith Packard <keithp@keithp.com>
* config/lm32/lm32.cc: Add several #includes.
(va_list_type): New.
(lm32_build_va_list): New function.
(lm32_builtin_va_start): Likewise.
(lm32_sd_gimplify_va_arg_expr): Likewise.
(lm32_gimplify_va_arg_expr): Likewise.
2025-01-16 Keith Packard <keithp@keithp.com>
* config/lm32/lm32.cc (setup_incoming_varargs): Adjust the
conditionals so that pretend_size is always computed, even
if no_rtl is set.
2025-01-16 Keith Packard <keithp@keithp.com>
* config/lm32/lm32.cc (lm32_setup_incoming_varargs): Skip last
named parameter when preparing to flush registers with unnamed
arguments to th stack.
2025-01-16 Keith Packard <keithp@keithp.com>
* config/lm32/lm32.cc (lm32_function_arg): Pass unnamed
arguments in registers too, just like named arguments.
2025-01-16 Andi Kleen <ak@gcc.gnu.org>
* config/i386/x86-tune-sched-core.cc: Fix incorrect comment.
2025-01-16 Eugene Rozenfeld <erozen@microsoft.com>
PR gcov-profile/116743
* auto-profile.cc (afdo_annotate_cfg): Fix mismatch between the call graph node count
and the entry block count.
2025-01-15 Andrew Pinski <quic_apinski@quicinc.com>
PR tree-optimization/102705
* match.pd (`(1 >> X) != 0`): Remove pattern.
(`1 >> x`): New pattern.
2025-01-15 Sam James <sam@gentoo.org>
* doc/extend.texi: Cleanup trailing whitespace.
2025-01-15 Sam James <sam@gentoo.org>
* doc/extend.texi: Add 'a' for grammar fix.
2025-01-15 Wilco Dijkstra <wilco.dijkstra@arm.com>
* config/aarch64/tuning_models/neoverse512tvb.h (tune_flags): Update.
2025-01-15 Wilco Dijkstra <wilco.dijkstra@arm.com>
* config/aarch64/aarch64-tuning-flags.def (AARCH64_EXTRA_TUNE_BASE):
Add AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA.
* config/aarch64/tuning_models/ampere1b.h: Remove redundant
AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA.
* config/aarch64/tuning_models/neoversev2.h: Likewise.
2025-01-15 Wilco Dijkstra <wilco.dijkstra@arm.com>
* config/aarch64/aarch64.cc (aarch64_override_options): Add warning.
* doc/invoke.texi: Document -mabi=ilp32 as deprecated.
2025-01-15 Cupertino Miranda <cupertino.miranda@oracle.com>
* config/bpf/core-builtins.cc (compute_field_expr): Change
VAR_DECL outcome in switch case.
2025-01-15 Cupertino Miranda <cupertino.miranda@oracle.com>
* config/bpf/core-builtins.cc
(make_gimple_core_safe_access_index): Fix in condition.
2025-01-15 Cupertino Miranda <cupertino.miranda@oracle.com>
* btfout.cc (get_btf_kind): Remove static from function definition.
* config/bpf/btfext-out.cc (bpf_code_reloc_add): Check if CO-RE type
is not a const or volatile.
* ctfc.h (btf_dtd_kind): Add prototype for function.
2025-01-15 Tamar Christina <tamar.christina@arm.com>
PR middle-end/118472
* fold-const.cc (operand_compare::operand_equal_p): Fix incorrect
replacement.
2025-01-15 Richard Biener <rguenther@suse.de>
* genmatch.cc (define_dump_logs): Make reverse lookup in
dbg_line_numbers easier by adding comments with start index
and cutting number of elements per line to 10.
2025-01-15 Jakub Jelinek <jakub@redhat.com>
PR ipa/116068
* cgraphunit.cc (symbol_table::process_new_functions): Call
bitmap_obstack_initialize (NULL); and bitmap_obstack_release (NULL)
around processing the functions.
2025-01-15 Kito Cheng <kito.cheng@sifive.com>
PR target/118182
* config/riscv/autovec-opt.md (*widen_reduc_plus_scal_<mode>): Adjust
argument for expand_reduction.
(*widen_reduc_plus_scal_<mode>): Ditto.
(*fold_left_widen_plus_<mode>): Ditto.
(*mask_len_fold_left_widen_plus_<mode>): Ditto.
(*cond_widen_reduc_plus_scal_<mode>): Ditto.
(*cond_len_widen_reduc_plus_scal_<mode>): Ditto.
(*cond_widen_reduc_plus_scal_<mode>): Ditto.
* config/riscv/autovec.md (reduc_plus_scal_<mode>): Adjust argument for
expand_reduction.
(reduc_smax_scal_<mode>): Ditto.
(reduc_umax_scal_<mode>): Ditto.
(reduc_smin_scal_<mode>): Ditto.
(reduc_umin_scal_<mode>): Ditto.
(reduc_and_scal_<mode>): Ditto.
(reduc_ior_scal_<mode>): Ditto.
(reduc_xor_scal_<mode>): Ditto.
(reduc_plus_scal_<mode>): Ditto.
(reduc_smax_scal_<mode>): Ditto.
(reduc_smin_scal_<mode>): Ditto.
(reduc_fmax_scal_<mode>): Ditto.
(reduc_fmin_scal_<mode>): Ditto.
(fold_left_plus_<mode>): Ditto.
(mask_len_fold_left_plus_<mode>): Ditto.
* config/riscv/riscv-v.cc (expand_reduction): Add one more
argument for reduction code for vl0-safe.
* config/riscv/riscv-protos.h (expand_reduction): Ditto.
* config/riscv/vector-iterators.md (unspec): Add _VL0_SAFE variant of
reduction.
(ANY_REDUC_VL0_SAFE): New.
(ANY_WREDUC_VL0_SAFE): Ditto.
(ANY_FREDUC_VL0_SAFE): Ditto.
(ANY_FREDUC_SUM_VL0_SAFE): Ditto.
(ANY_FWREDUC_SUM_VL0_SAFE): Ditto.
(reduc_op): Add _VL0_SAFE variant of reduction.
(order) Ditto.
* config/riscv/vector.md (@pred_<reduc_op><mode>): New.
2025-01-15 Richard Biener <rguenther@suse.de>
PR tree-optimization/115777
* tree-vect-slp.cc (vect_bb_slp_scalar_cost): Do not
cost a scalar stmt that needs to be preserved.
2025-01-15 Michal Jires <mjires@suse.cz>
PR lto/118238
* lto-wrapper.cc (run_gcc): Remove link() copying.
2025-01-15 Anton Blanchard <antonb@tenstorrent.com>
Jeff Law <jlaw@ventanamicro.com>
PR target/118170
* config/riscv/generic-ooo.md (generic_ooo_float_div_half): New
reservation.
2025-01-15 Richard Sandiford <richard.sandiford@arm.com>
Jeff Law <jlaw@ventanamicro.com>
PR rtl-optimization/109592
* simplify-rtx.cc (simplify_context::simplify_binary_operation_1):
Simplify nested shifts with subregs.
2025-01-14 anetczuk <anetczuk@o2.pl>
* tree-dump.cc (dequeue_and_dump): Handle OBJ_TYPE_REF.
2025-01-14 Alexandre Oliva <oliva@adacore.com>
* gimple-fold.cc (decode_field_reference): Rebustify to set
out parms only when returning non-NULL.
(fold_truth_andor_for_ifcombine): Bail if
decode_field_reference returns NULL. Add complementary assert
on r_const's not being set when l_const isn't.
2025-01-14 Sandra Loosemore <sloosemore@baylibre.com>
* cgraph.cc (symbol_table::create_edge): Don't set
calls_declare_variant_alt in the caller.
* cgraph.h (struct cgraph_node): Remove declare_variant_alt
and calls_declare_variant_alt flags.
* cgraphclones.cc (cgraph_node::create_clone): Don't copy
calls_declare_variant_alt bit.
* gimplify.cc: Remove previously #ifdef-ed out code.
* ipa-free-lang-data.cc (free_lang_data_in_decl): Adjust code
referencing declare_variant_alt bit.
* ipa.cc (symbol_table::remove_unreachable_nodes): Likewise.
* lto-cgraph.cc (lto_output_node): Remove references to deleted
bits.
(output_refs): Adjust code referencing declare_variant_alt bit.
(input_overwrite_node): Remove references to deleted bits.
(input_refs): Adjust code referencing declare_variant_alt bit.
* lto-streamer-out.cc (lto_output): Likewise.
* lto-streamer.h (omp_lto_output_declare_variant_alt): Delete.
(omp_lto_input_declare_variant_alt): Delete.
* omp-expand.cc (expand_omp_target): Use has_omp_variant_constructs
bit to trigger pass_omp_device_lower instead of
calls_declare_variant_alt.
* omp-general.cc (struct omp_declare_variant_entry): Delete.
(struct omp_declare_variant_base_entry): Delete.
(struct omp_declare_variant_hasher): Delete.
(omp_declare_variant_hasher::hash): Delete.
(omp_declare_variant_hasher::equal): Delete.
(omp_declare_variants): Delete.
(omp_declare_variant_alt_hasher): Delete.
(omp_declare_variant_alt_hasher::hash): Delete.
(omp_declare_variant_alt_hasher::equal): Delete.
(omp_declare_variant_alt): Delete.
(omp_lto_output_declare_variant_alt): Delete.
(omp_lto_input_declare_variant_alt): Delete.
(includes): Delete unnecessary include of gt-omp-general.h.
* omp-offload.cc (execute_omp_device_lower): Remove references
to deleted bit.
(pass_omp_device_lower::gate): Likewise.
* omp-simd-clone.cc (simd_clone_create): Likewise.
* passes.cc (ipa_write_summaries): Likeise.
* symtab.cc (symtab_node::get_partitioning_class): Likewise.
* tree-inline.cc (expand_call_inline): Likewise.
(tree_function_versioning): Likewise.
2025-01-14 Sandra Loosemore <sloosemore@baylibre.com>
Kwok Cheung Yeung <kcy@codesourcery.com>
Sandra Loosemore <sandra@codesourcery.com>
Marcel Vollweiler <marcel@codesourcery.com>
PR middle-end/114596
PR middle-end/112779
PR middle-end/113904
* Makefile.in (GTFILES): Move omp-general.h earlier; required
because of moving score_wide_int declaration to that file.
* cgraph.h (struct cgraph_node): Add has_omp_variant_constructs flag.
* cgraphclones.cc (cgraph_node::create_clone): Propagate
has_omp_variant_constructs flag.
* gimplify.cc (omp_resolved_variant_calls): New.
(expand_late_variant_directive): New.
(find_supercontext): New.
(gimplify_variant_call_expr): New.
(gimplify_call_expr): Adjust parameters to make fallback available.
Update processing for "declare variant" substitution.
(is_gimple_stmt): Add OMP_METADIRECTIVE.
(omp_construct_selector_matches): Ifdef out unused function.
(omp_get_construct_context): New.
(gimplify_omp_dispatch): Replace call to deleted function
omp_resolve_declare_variant with equivalent logic.
(expand_omp_metadirective): New.
(expand_late_variant_directive): New.
(gimplify_omp_metadirective): New.
(gimplify_expr): Adjust arguments to gimplify_call_expr. Add
cases for OMP_METADIRECTIVE, OMP_NEXT_VARIANT, and
OMP_TARGET_DEVICE_MATCHES.
(gimplify_function_tree): Initialize/clean up
omp_resolved_variant_calls.
* gimplify.h (omp_construct_selector_matches): Delete declaration.
(omp_get_construct_context): Declare.
* lto-cgraph.cc (lto_output_node): Write has_omp_variant_constructs.
(input_overwrite_node): Read has_omp_variant_constructs.
* omp-builtins.def (BUILT_IN_OMP_GET_NUM_DEVICES): New.
* omp-expand.cc (expand_omp_taskreg): Propagate
has_omp_variant_constructs.
(expand_omp_target): Likewise.
* omp-general.cc (omp_maybe_offloaded): Add construct_context
parameter; use it instead of querying gimplifier state. Add
comments.
(omp_context_name_list_prop): Do not test lang_GNU_Fortran in
offload compiler, just use the string as-is.
(expr_uses_parm_decl): New.
(omp_check_context_selector): Add metadirective_p parameter.
Remove sorry for target_device selector. Add additional checks
specific to metadirective or declare variant.
(make_omp_metadirective_variant): New.
(omp_construct_traits_match): New.
(omp_context_selector_matches): Temporarily ifdef out the previous
code, and add a new implementation based on the old one with
different parameters, some unnecessary loops removed, and code
re-indented.
(omp_target_device_matches_on_host): New.
(resolve_omp_target_device_matches): New.
(omp_construct_simd_compare): Support matching of "simdlen" and
"aligned" clauses.
(omp_context_selector_set_compare): Make static. Adjust call to
omp_construct_simd_compare.
(score_wide_int): Move declaration to omp-general.h.
(omp_selector_is_dynamic): New.
(omp_device_num_check): New.
(omp_dynamic_cond): New.
(omp_context_compute_score): Ifdef out the old version and
re-implement with different parameters.
(omp_complete_construct_context): New.
(omp_resolve_late_declare_variant): Ifdef out.
(omp_declare_variant_remove_hook): Likewise.
(omp_resolve_declare_variant): Likewise.
(sort_variant): New.
(omp_get_dynamic_candidates): New.
(omp_declare_variant_candidates): New.
(omp_metadirective_candidates): New.
(omp_early_resolve_metadirective): New.
(omp_resolve_variant_construct): New.
* omp-general.h (score_wide_int): Moved here from omp-general.cc.
(struct omp_variant): New.
(make_omp_metadirective_variant): Declare.
(omp_construct_traits_to_codes): Delete declaration.
(omp_check_context_selector): Adjust parameters.
(omp_context_selector_matches): Likewise.
(omp_context_selector_set_compare): Delete declaration.
(omp_resolve_declare_variant): Likewise.
(omp_declare_variant_candidates): Declare.
(omp_metadirective_candidates): Declare.
(omp_get_dynamic_candidates): Declare.
(omp_early_resolve_metadirective): Declare.
(omp_resolve_variant_construct): Declare.
(omp_dynamic_cond): Declare.
* omp-offload.cc (resolve_omp_variant_cookies): New.
(execute_omp_device_lower): Call the above function to resolve
variant directives. Remove call to omp_resolve_declare_variant.
(pass_omp_device_lower::gate): Check has_omp_variant_construct bit.
* omp-simd-clone.cc (simd_clone_create): Propagate
has_omp_variant_constructs bit.
* tree-inline.cc (expand_call_inline): Likewise.
(tree_function_versioning): Likewise.
2025-01-14 Sandra Loosemore <sloosemore@baylibre.com>
Kwok Cheung Yeung <kcy@codesourcery.com>
Sandra Loosemore <sandra@codesourcery.com>
* doc/generic.texi (OpenMP): Document OMP_METADIRECTIVE,
OMP_NEXT_VARIANT, and OMP_TARGET_DEVICE_MATCHES.
* fold-const.cc (operand_compare::hash_operand): Ignore
the new nodes.
* gimple-expr.cc (is_gimple_val): Allow OMP_NEXT_VARIANT
and OMP_TARGET_DEVICE_MATCHES.
* gimple.cc (get_gimple_rhs_num_ops): OMP_NEXT_VARIANT and
OMP_TARGET_DEVICE_MATCHES are both GIMPLE_SINGLE_RHS.
* tree-cfg.cc (tree_node_can_be_shared): Allow sharing of
OMP_NEXT_VARIANT.
* tree-inline.cc (remap_gimple_op_r): Ignore subtrees of
OMP_NEXT_VARIANT.
* tree-pretty-print.cc (dump_generic_node): Handle OMP_METADIRECTIVE,
OMP_NEXT_VARIANT, and OMP_TARGET_DEVICE_MATCHES.
* tree-ssa-operands.cc (operands_scanner::get_expr_operands):
Ignore operands of OMP_NEXT_VARIANT and OMP_TARGET_DEVICE_MATCHES.
* tree.def (OMP_METADIRECTIVE): New.
(OMP_NEXT_VARIANT): New.
(OMP_TARGET_DEVICE_MATCHES): New.
* tree.h (OMP_METADIRECTIVE_VARIANTS): New.
(OMP_METADIRECTIVE_VARIANT_SELECTOR): New.
(OMP_METADIRECTIVE_VARIANT_DIRECTIVE): New.
(OMP_METADIRECTIVE_VARIANT_BODY): New.
(OMP_NEXT_VARIANT_INDEX): New.
(OMP_NEXT_VARIANT_STATE): New.
(OMP_TARGET_DEVICE_MATCHES_SELECTOR): New.
(OMP_TARGET_DEVICE_MATCHES_PROPERTIES): New.
2025-01-14 Alexandre Oliva <oliva@adacore.com>
PR tree-optimization/118456
* gimple-fold.cc (decode_field_reference): Punt if shifting
after changing signedness.
(fold_truth_andor_for_ifcombine): Check extension bits in
constants before clipping.
2025-01-14 Robin Dapp <rdapp@ventanamicro.com>
PR target/118154
* config/riscv/riscv-vsetvl.cc (MAX_LMUL): New define.
(pre_vsetvl::earliest_fuse_vsetvl_info): Use.
(pre_vsetvl::pre_global_vsetvl_info): New predicate with equal
ratio.
* config/riscv/riscv-vsetvl.def: Use.
2025-01-14 Robin Dapp <rdapp@ventanamicro.com>
PR middle-end/118140
* gimple-match-exports.cc (maybe_resimplify_conditional_op): Add
COND_EXPR when we simplified to a scalar gimple value but still
have an else value.
2025-01-14 Richard Biener <rguenther@suse.de>
PR tree-optimization/118405
* tree-vect-stmts.cc (vectorizable_load): When we fall back
to scalar loads make sure we properly convert to vector(1) T
when there was only a single vector element.
2025-01-14 Robin Dapp <rdapp.gcc@gmail.com>
* config/riscv/riscv-v.cc (expand_const_vector): Shift in Xmode.
2025-01-14 Jiufu Guo <guojiufu@linux.ibm.com>
PR target/116030
* config/rs6000/vsx.md (vsx_stxvd2x4_le_const_<mode>): Add clobber
and guard with !altivec_indexed_or_indirect_operand.
2025-01-14 Robin Dapp <rdapp.gcc@gmail.com>
PR target/117682
* config/riscv/riscv-v.cc (expand_const_vector): Fall back to
merging if either step is negative.
2025-01-13 Xi Ruoyao <xry111@xry111.site>
PR target/115921
* config/riscv/riscv.md (<optab>_shift_reverse): Remove
check for TARGET_ZBA.
2025-01-13 Richard Sandiford <richard.sandiford@arm.com>
PR target/118418
* simplify-rtx.cc (simplify_context::simplify_relational_operation_1):
Take STORE_FLAG_VALUE into account when handling signed comparisons
of comparison results.
2025-01-13 Xi Ruoyao <xry111@xry111.site>
PR target/115921
* config/riscv/riscv.md (<optab>_shift_reverse): Only check
popcount_hwi if !TARGET_ZBS.
2025-01-13 Jin Ma <jinma@linux.alibaba.com>
* config/riscv/riscv-vsetvl.cc (demand_system::use_max_sew): Also
set the ratio for PREV.
2025-01-13 Vineet Gupta <vineetg@rivosinc.com>
* config/riscv/riscv.cc (riscv_register_move_cost): Remove buggy
check.
2025-01-13 Jin Ma <jinma@linux.alibaba.com>
* config/riscv/riscv.cc (riscv_build_integer_1): Change
1UL/1ULL to HOST_WIDE_INT_1U.
2025-01-13 Jeff Law <jlaw@ventanamicro.com>
PR rtl-optimization/107455
* postreload.cc (reload_cse_regs_1): Take advantage of conditional
equivalences.
2025-01-13 Alexandre Oliva <oliva@adacore.com>
PR tree-optimization/118409
* gimple-fold.cc (fold_truth_andor_for_ifcombine): Apply the
signbit mask to the right-hand XOR operand too.
2025-01-13 Jakub Jelinek <jakub@redhat.com>
PR target/115910
* expr.cc (expand_expr_divmod): Prefix the TDF_DETAILS note with
";; " and add a space before (needed tie breaker). Formatting fixes.
2025-01-13 Richard Biener <rguenther@suse.de>
Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
PR tree-optimization/117119
* tree-data-ref.cc (initialize_matrix_A): Check whether
an INTEGER_CST fits in HWI, otherwise return chrec_dont_know.
2025-01-13 Michal Jires <mjires@suse.cz>
PR lto/118181
* lto-ltrans-cache.cc (ltrans_file_cache::create_item):
Pass checksum by reference.
* lto-ltrans-cache.h: Likewise.
2025-01-13 Michal Jires <mjires@suse.cz>
* lockfile.cc (LOCKFILE_USE_FCNTL): New.
(lockfile::lock_write): Use LOCKFILE_USE_FCNTL.
(lockfile::try_lock_write): Use LOCKFILE_USE_FCNTL.
(lockfile::lock_read): Use LOCKFILE_USE_FCNTL.
(lockfile::unlock): Use LOCKFILE_USE_FCNTL.
(lockfile::lockfile_supported): Use LOCKFILE_USE_FCNTL.
2025-01-13 liuhongt <hongtao.liu@intel.com>
* config/i386/i386-expand.cc (ix86_expand_vecop_qihi2):
Refactor to avoid redundant TARGET_AVX512BW in many places.
2025-01-13 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/117997
PR middle-end/118415
* expr.cc (assemble_crc_table): Make static, remove id argument,
use output_constant_def. Emit note if -fdump-rtl-expand-details
about which table has been emitted.
(generate_crc_table): Make static, adjust assemble_crc_table
caller, call it always.
(calculate_table_based_CRC): Make static.
* internal-fn.cc (expand_crc_optab_fn): Emit note if
-fdump-rtl-expand-details about using optab for crc. Formatting fix.
2025-01-12 Maciej W. Rozycki <macro@orcam.me.uk>
* config/alpha/alpha.cc (alpha_expand_block_move): Use a HImode
subreg of a DImode register to hold data from an aligned HImode
load.
2025-01-12 Maciej W. Rozycki <macro@orcam.me.uk>
* config/alpha/alpha.cc (alpha_expand_block_move): Merge loaded
data from pairs of SImode registers into single DImode registers
if to be used with unaligned stores.
2025-01-12 Maciej W. Rozycki <macro@orcam.me.uk>
* config/alpha/alpha.cc (alpha_option_override): Ignore CPU
flags corresponding to features the enabling or disabling of
which has been requested with an individual feature option.
2025-01-12 Maciej W. Rozycki <macro@orcam.me.uk>
PR middle-end/64242
* config/alpha/alpha.md (`builtin_longjmp'): Restore frame
pointer last. Add frame clobber and schedule blockage.
2025-01-12 Maciej W. Rozycki <macro@orcam.me.uk>
* config/alpha/alpha.md (builtin_longjmp): Add memory clobbers.
2025-01-12 Richard Biener <rguenther@suse.de>
* tree-vect-slp.cc (vect_analyze_slp): Release saved_stmts
vector.
(vect_build_slp_tree_2): Release new_oprnds_info when not
used.
(vect_analyze_slp): Release root_stmts when gcond SLP
build fails.
2025-01-12 Andrew Pinski <quic_apinski@quicinc.com>
PR middle-end/118411
* final.cc (get_attr_length_1): Handle asm for CALL_INSN
and JUMP_INSNs.
2025-01-11 mengqinggang <mengqinggang@loongson.cn>
* config/loongarch/lasx.md: Use new loongarch_output_move.
* config/loongarch/loongarch-protos.h (loongarch_output_move):
Change parameters from (rtx, rtx) to (rtx *).
* config/loongarch/loongarch.cc (loongarch_output_move):
Generate final immediate for lu12i.w and lu52i.d.
* config/loongarch/loongarch.md:
Generate final immediate for lu32i.d and lu52i.d.
* config/loongarch/lsx.md: Use new loongarch_output_move.
2025-01-11 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/88575
* vr-values.cc (simplify_using_ranges::fold_cond_with_ops): Query
relation between op0 and op1 and utilize it.
(simplify_using_ranges::simplify): Do not eliminate float checks.
2025-01-10 Alex Coplan <alex.coplan@arm.com>
PR tree-optimization/118211
PR tree-optimization/116126
* tree-vect-loop.cc (vect_compute_single_scalar_iteration_cost):
Don't skip over gconds.
2025-01-10 Alex Coplan <alex.coplan@arm.com>
PR tree-optimization/118211
PR tree-optimization/116126
* tree-vect-loop-manip.cc (vect_do_peeling): Adjust skip_vector
condition to only omit the edge if we're versioning for
alignment.
2025-01-10 Tamar Christina <Tamar.Christina@arm.com>
Alex Coplan <alex.coplan@arm.com>
PR tree-optimization/118211
PR tree-optimization/116126
* tree-vect-loop-manip.cc (vect_do_peeling): Update immediate
dominators of nodes that were dominated by the prolog skip block
after inserting vector skip edge. Initialize prolog variable to
NULL to avoid bogus -Wmaybe-uninitialized during bootstrap.
2025-01-10 Alex Coplan <alex.coplan@arm.com>
PR tree-optimization/118211
PR tree-optimization/116126
* tree-vect-loop-manip.cc (vect_do_peeling): Avoid emitting an
epilogue guard for inverted early-exit loops.
2025-01-10 Alex Coplan <alex.coplan@arm.com>
Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/118211
PR tree-optimization/116126
* tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
Set need_peeling_for_alignment flag on read DRs instead of
failing vectorization. Punt on gathers.
(dr_misalignment): Handle non-constant target alignments.
(vect_compute_data_ref_alignment): If need_peeling_for_alignment
flag is set on the DR, then override the target alignment chosen
by the preferred_vector_alignment hook to choose a safe
alignment.
(vect_supportable_dr_alignment): Override
support_vector_misalignment hook if need_peeling_for_alignment
is set on the DR: in this case we must return
dr_unaligned_unsupported in order to force peeling.
* tree-vect-loop-manip.cc (vect_do_peeling): Allow prolog
peeling by a compile-time non-constant amount.
* tree-vectorizer.h (dr_vec_info): Add new flag
need_peeling_for_alignment.
2025-01-10 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64-cores.def (AARCH64_CORE): Fix cortex-x4 parts
num.
2025-01-10 Richard Biener <rguenther@suse.de>
* df-core.cc (rest_of_handle_df_finish): Release dflow for
problems without free function (like LR).
* gimple-crc-optimization.cc (crc_optimization::loop_may_calculate_crc):
Release loop_bbs on all exits.
* tree-vectorizer.h (supportable_indirect_convert_operation): Change.
* tree-vect-generic.cc (expand_vector_conversion): Adjust.
* tree-vect-stmts.cc (vectorizable_conversion): Use auto_vec for
converts.
(supportable_indirect_convert_operation): Get a reference to
the output vector of converts.
2025-01-10 Christophe Lyon <christophe.lyon@linaro.org>
PR target/118332
* config/arm/arm-mve-builtins.cc (wrap_type_in_struct): Delete.
(register_type_decl): Delete.
(register_builtin_tuple_types): Use
lang_hooks.types.simulate_record_decl.
2025-01-10 Richard Biener <rguenther@suse.de>
* gcse.cc (pass_hardreg_pre::gate): Wrap possibly unused
fun argument.
2025-01-10 Richard Biener <rguenther@suse.de>
PR rtl-optimization/117467
PR rtl-optimization/117934
* ext-dce.cc (ext_dce_execute): Do nothing if a memory
allocation estimate exceeds what is allowed by
--param max-gcse-memory.
2025-01-10 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* config/s390/s390-protos.h (s390_emit_compare): Add mode
parameter for the resulting RTX.
* config/s390/s390.cc (s390_emit_compare): Dito.
(s390_emit_compare_and_swap): Change.
(s390_expand_vec_strlen): Change.
(s390_expand_cs_hqi): Change.
(s390_expand_split_stack_prologue): Change.
* config/s390/s390.md (*add<mode>3_carry1_cc): Renamed to ...
(add<mode>3_carry1_cc): this and in order to use the
corresponding gen function, encode CC mode into pattern.
(*sub<mode>3_borrow_cc): Renamed to ...
(sub<mode>3_borrow_cc): this and in order to use the
corresponding gen function, encode CC mode into pattern.
(*add<mode>3_alc_carry1_cc): Renamed to ...
(add<mode>3_alc_carry1_cc): this and in order to use the
corresponding gen function, encode CC mode into pattern.
(sub<mode>3_slb_borrow1_cc): New.
(uaddc<mode>5): New.
(usubc<mode>5): New.
2025-01-10 Andrew Carlotti <andrew.carlotti@arm.com>
* doc/passes.texi: Document hardreg PRE pass.
2025-01-10 Andrew Carlotti <andrew.carlotti@arm.com>
* config/aarch64/aarch64.h (HARDREG_PRE_REGNOS): New macro.
* gcse.cc (doing_hardreg_pre_p): New global variable.
(do_load_motion): New boolean check.
(current_hardreg_regno): New global variable.
(compute_local_properties): Unset transp for hardreg clobbers.
(prune_hardreg_uses): New function.
(want_to_gcse_p): Use different checks for hardreg PRE.
(oprs_unchanged_p): Disable load motion for hardreg PRE pass.
(hash_scan_set): For hardreg PRE, skip non-hardreg sets and
check for hardreg clobbers.
(record_last_mem_set_info): Skip for hardreg PRE.
(compute_pre_data): Prune hardreg uses from transp bitmap.
(pre_expr_reaches_here_p_work): Add sentence to comment.
(insert_insn_start_basic_block): New functions.
(pre_edge_insert): Don't add hardreg sets to predecessor block.
(pre_delete): Use hardreg for the reaching reg.
(reset_hardreg_debug_uses): New function.
(pre_gcse): For hardreg PRE, reset debug uses and don't insert
copies.
(one_pre_gcse_pass): Disable load motion for hardreg PRE.
(execute_hardreg_pre): New.
(class pass_hardreg_pre): New.
(pass_hardreg_pre::gate): New.
(make_pass_hardreg_pre): New.
* passes.def (pass_hardreg_pre): New pass.
* tree-pass.h (make_pass_hardreg_pre): New.
2025-01-10 Andrew Carlotti <andrew.carlotti@arm.com>
* multiple_target.cc
(redirect_to_specific_clone): Assert that "target" attribute is
used for FMV before checking it.
(ipa_target_clone): Skip redirect_to_specific_clone on some
targets.
2025-01-10 Andrew Carlotti <andrew.carlotti@arm.com>
* doc/invoke.texi: Add new AArch64 flags.
2025-01-10 Andrew Carlotti <andrew.carlotti@arm.com>
* config/aarch64/aarch64-arches.def (V8_7A): Add XS.
* config/aarch64/aarch64-option-extensions.def (XS): New flag.
2025-01-10 Andrew Carlotti <andrew.carlotti@arm.com>
* config/aarch64/aarch64-arches.def (V8_7A): Add WFXT.
* config/aarch64/aarch64-option-extensions.def (WFXT): New flag.
2025-01-10 Andrew Carlotti <andrew.carlotti@arm.com>
* config/aarch64/aarch64-arches.def (V8_4A): Add RCPC2.
* config/aarch64/aarch64-option-extensions.def
(RCPC2): New flag.
(RCPC3): Add RCPC2 dependency.
* config/aarch64/aarch64.h (TARGET_RCPC2): Use new flag.
2025-01-10 Andrew Carlotti <andrew.carlotti@arm.com>
* config/aarch64/aarch64-arches.def (V8_5A): Add FLAGM2.
* config/aarch64/aarch64-option-extensions.def (FLAGM2): New flag.
2025-01-10 Andrew Carlotti <andrew.carlotti@arm.com>
* config/aarch64/aarch64-arches.def (V8_5A): Add FRINTTS
* config/aarch64/aarch64-option-extensions.def (FRINTTS): New flag.
* config/aarch64/aarch64.h (TARGET_FRINT): Use new flag.
* config/aarch64/arm_acle.h: Use new flag for frintts intrinsics.
* config/aarch64/arm_neon.h: Ditto.
2025-01-10 Andrew Carlotti <andrew.carlotti@arm.com>
* config/aarch64/aarch64-arches.def (V8_3A): Add JSCVT.
* config/aarch64/aarch64-option-extensions.def (JSCVT): New flag.
* config/aarch64/aarch64.h (TARGET_JSCVT): Use new flag.
* config/aarch64/arm_acle.h: Use new flag for jscvt intrinsics.
2025-01-10 Andrew Carlotti <andrew.carlotti@arm.com>
* config/aarch64/aarch64-arches.def (V8_3A): Add FCMA.
* config/aarch64/aarch64-option-extensions.def (FCMA): New flag.
(SVE): Add FCMA dependency.
* config/aarch64/aarch64.h (TARGET_COMPLEX): Use new flag.
* config/aarch64/arm_neon.h: Use new flag for fcma intrinsics.
2025-01-10 Andrew Carlotti <andrew.carlotti@arm.com>
* config/aarch64/aarch64.cc
(aarch64_expand_epilogue): Use TARGET_PAUTH.
* config/aarch64/aarch64.md: Update comment.
2025-01-10 Richard Sandiford <richard.sandiford@arm.com>
PR rtl-optimization/117186
* rtl.h (simplify_context::simplify_logical_relational_operation): Add
an invert0_p parameter.
* simplify-rtx.cc (unsigned_comparison_to_mask): New function.
(mask_to_unsigned_comparison): Likewise.
(comparison_code_valid_for_mode): Delete.
(simplify_context::simplify_logical_relational_operation): Add
an invert0_p parameter. Handle AND and XOR. Handle unsigned
comparisons. Handle always-false results. Ignore the low bit
of the mask if the operands are always ordered and remove the
then-redundant check of comparison_code_valid_for_mode. Check
for side-effects in the operands before simplifying them away.
(simplify_context::simplify_binary_operation_1): Remove
simplification of (compare (gt ...) (lt ...)) and instead...
(simplify_context::simplify_relational_operation_1): ...handle
comparisons of comparisons here.
(test_comparisons): New function.
(test_scalar_ops): Call it.
2025-01-10 Alexandre Oliva <oliva@adacore.com>
* gimple-fold.cc (decode_field_reference): Drop misuses of
uniform_integer_cst_p.
(fold_truth_andor_for_ifcombine): Likewise.
2025-01-10 Alexandre Oliva <oliva@adacore.com>
PR tree-optimization/118344
* gimple-fold.cc (fold_truth_andor_for_ifcombine): Fix typo in
rr_and_mask's type adjustment test.
2025-01-10 Alexandre Oliva <oliva@adacore.com>
* gimple-fold.cc (decode_field_reference): Add xor_pand_mask.
Propagate pand_mask to the right-hand xor operand. Don't
require the right-hand xor operand to be a constant.
(fold_truth_andor_for_ifcombine): Pass right-hand mask when
appropriate.
2025-01-10 Alexandre Oliva <oliva@adacore.com>
PR tree-optimization/118206
* gimple-fold.cc (decode_field_reference): Account for upper
bits dropped by narrowing conversions whether before or after
a right shift.
(fold_truth_andor_for_ifcombine): Fold masks, compares, and
combined results.
2025-01-10 Alexandre Oliva <oliva@adacore.com>
* gimple-fold.cc (fold_truth_andor_for_ifcombine): Limit
boundary choice by word size as well. Try aligned double-word
loads as a last resort.
2025-01-10 Martin Jambor <mjambor@suse.cz>
PR ipa/118138
* ipa-cp.cc (ipacp_value_safe_for_type): Return the appropriate
type instead of a bool, accept NULL_TREE VALUEs.
(propagate_vals_across_arith_jfunc): Use the new returned value of
ipacp_value_safe_for_type.
(propagate_vals_across_ancestor): Likewise.
(propagate_scalar_across_jump_function): Likewise.
2025-01-10 chenxiaolong <chenxiaolong@loongson.cn>
Deng Jianbo <dengjianbo@loongson.cn>.
* config/loongarch/loongarch.cc
(loongarch_builtin_vectorization_cost): Modify the
construction cost of the vec_construct vector.
2025-01-09 Tamar Christina <tamar.christina@arm.com>
PR target/118188
* config/aarch64/aarch64.cc (aarch64_vector_costs::count_ops): Adjust
throughput of emulated gather and scatters.
2025-01-09 Vladimir N. Makarov <vmakarov@redhat.com>
PR target/118017
* lra-constraints.cc (inherit_reload_reg): Check reg class on uniformity.
2025-01-09 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
PR target/118362
* config/s390/s390.cc (s390_constant_via_vgbm_p): Allow at most
16-byte vectors.
2025-01-09 Christophe Lyon <christophe.lyon@linaro.org>
PR target/118131
* config/arm/arm.h (VALID_MVE_STRUCT_MODE): Accept TI, OI and XI
modes again.
2025-01-09 Thomas Schwinge <tschwinge@baylibre.com>
PR target/65181
* config/nvptx/nvptx.cc (nvptx_get_drap_rtx): Handle
'!TARGET_SOFT_STACK'.
* config/nvptx/nvptx.md (define_c_enum "unspec"): Add
'UNSPEC_STACKSAVE', 'UNSPEC_STACKRESTORE'.
(define_expand "allocate_stack", define_expand "save_stack_block")
(define_expand "save_stack_block"): Handle '!TARGET_SOFT_STACK',
PTX 'alloca'.
(define_insn "@nvptx_alloca_<mode>")
(define_insn "@nvptx_stacksave_<mode>")
(define_insn "@nvptx_stackrestore_<mode>"): New.
* doc/invoke.texi (Nvidia PTX Options): Update '-msoft-stack',
'-mno-soft-stack'.
* doc/sourcebuild.texi (nvptx-specific attributes): Document
'nvptx_runtime_alloca_ptx'.
(Add Options): Document 'nvptx_alloca_ptx'.
2025-01-09 Richard Biener <rguenther@suse.de>
* cfgloopmanip.cc (duplicate_loop_body_to_header_edge): When
copying to the header edge first redirect the entry to the
new loop and then the exit to the old to avoid PHI node
re-allocation.
2025-01-09 H.J. Lu <hjl.tools@gmail.com>
PR rtl-optimization/118266
* ree.cc (add_removable_extension): Skip extension on fixed
register.
2025-01-09 Jakub Jelinek <jakub@redhat.com>
Andrew Pinski <quic_apinski@quicinc.com>
PR tree-optimization/117927
* tree-pass.h (PROP_last_full_fold): Define.
* passes.def: Add last= parameters to pass_forwprop.
* tree-ssa-forwprop.cc (pass_forwprop): Add last_p non-static
data member and initialize it in the ctor.
(pass_forwprop::set_pass_param): New method.
(pass_forwprop::execute): Set PROP_last_full_fold in curr_properties
at the start if last_p.
* match.pd (a rrotate (32-b) -> a lrotate b): Only optimize either
if @2 is known not to be equal to prec or if during/after last
forwprop the subtraction has single use and prec is power of two; in
that case transform it into orotate by masked count.
2025-01-09 Haochen Jiang <haochen.jiang@intel.com>
* common/config/i386/cpuinfo.h (get_intel_cpu): Remove 0x00.
2025-01-09 xuli <xuli1@eswincomputing.com>
* config/riscv/riscv-vector-builtins.cc (function_builder::add_unique_function):
Only register overloaded intrinsic for g++.
Only insert non_overloaded_function_table for gcc.
(function_builder::add_overloaded_function): Only register overloaded intrinsic for gcc.
(handle_pragma_vector): Only initialize non_overloaded_function_table for gcc.
2025-01-09 Tobias Burnus <tburnus@baylibre.com>
* builtin-types.def (BT_FN_PTRMODE_PTR_INT_PTR): Add.
* gimplify.cc (gimplify_call_expr): Add error for multiple
list items to the OpenMP interop clause if no device clause;
continue instead of restarting after append_args handling.
(gimplify_omp_dispatch): Extract device number from the
single interop-clause list item.
* omp-builtins.def (BUILT_IN_OMP_GET_INTEROP_INT): Add.
2025-01-08 Thomas Schwinge <tschwinge@baylibre.com>
PR target/65181
* config/nvptx/nvptx.cc (default_ptx_version_option): For
'-march=sm_52' and higher, default at least to '-mptx=7.3'.
* doc/invoke.texi (Nvidia PTX Options): Update '-mptx=[...]'.
2025-01-08 Thomas Schwinge <tschwinge@baylibre.com>
* config/nvptx/nvptx-opts.h (enum ptx_version): Add
'PTX_VERSION_7_3'.
* config/nvptx/nvptx.cc (ptx_version_to_string)
(ptx_version_to_number): Adjust.
* config/nvptx/nvptx.h (TARGET_PTX_7_3): New.
* config/nvptx/nvptx.opt (Enum(ptx_version)): Add 'EnumValue'
'7.3' for 'PTX_VERSION_7_3'.
* doc/invoke.texi (Nvidia PTX Options): Document '-mptx=7.3'.
2025-01-08 Thomas Schwinge <tschwinge@baylibre.com>
* doc/sourcebuild.texi (Effective-Target Keywords): Document
'nvptx_softstack'.
2025-01-08 Thomas Schwinge <tschwinge@baylibre.com>
PR target/65181
* config/nvptx/nvptx.h (STACK_SAVEAREA_MODE): '#define'.
* config/nvptx/nvptx.md [!TARGET_SOFT_STACK]
(save_stack_function): 'define_expand'.
(restore_stack_function): Handle '!TARGET_SOFT_STACK'.
2025-01-08 Thomas Schwinge <tschwinge@baylibre.com>
PR target/65181
* config/nvptx/nvptx.md [!TARGET_SOFT_STACK] (save_stack_block):
'define_expand'.
2025-01-08 Thiago Jung Bauermann <thiago.bauermann@linaro.org>
* configure.ac: Fix check for HAVE_GAS_SHF_MERGE on Arm targets.
* configure: Regenerate.
2025-01-08 Richard Sandiford <richard.sandiford@arm.com>
PR target/107102
* config/aarch64/aarch64.cc (aarch64_function_ok_for_sibcall): Only
reject calls with different PCSes if the callee clobbers register
state that the caller must preserve.
2025-01-08 Tobias Burnus <tburnus@baylibre.com>
* gimplify.cc (gimplify_call_expr): Disable variant function's
append_args in 'omp dispatch' when invoking the variant directly
and not through the base function.
2025-01-08 Thomas Schwinge <tschwinge@baylibre.com>
* doc/invoke.texi (Nvidia PTX Options): Update '-march-map=sm_50'.
2025-01-08 Richard Biener <rguenther@suse.de>
PR tree-optimization/117979
* tree-ssa-dce.cc (make_forwarders_with_degenerate_phis):
Properly update the irreducible region state.
2025-01-08 Jakub Jelinek <jakub@redhat.com>
* dwarf2out.cc (break_out_comdat_types): Copy over
DW_AT_language_{name,version} if present.
(output_skeleton_debug_sections): Remove also
DW_AT_language_{name,version}.
(gen_compile_unit_die): For C17, C23, C2Y, C++17, C++20, C++23
and C++26 emit for -gdwarf-5 -gno-strict-dwarf also
DW_AT_language_{name,version} attributes.
2025-01-08 Richard Biener <rguenther@suse.de>
PR middle-end/118325
* tree-nested.cc (convert_nl_goto_reference): Assign proper
context to generated artificial label.
2025-01-08 Richard Biener <rguenther@suse.de>
PR tree-optimization/118269
* tree-vect-loop.cc (vect_create_epilog_for_reduction):
Use the correct stmt for the REDUC_GROUP_FIRST_ELEMENT lookup.
2025-01-08 Christophe Lyon <christophe.lyon@linaro.org>
PR target/118332
* config/arm/arm-mve-builtins.cc (wrap_type_in_struct): Use 'val'
instead of '__val'.
2025-01-08 Haochen Jiang <haochen.jiang@intel.com>
* config/i386/amxavx512intrin.h
(_tile_cvtrowps2pbf16h_internal): Rename to...
(_tile_cvtrowps2bf16h_internal): ...this.
(_tile_cvtrowps2pbf16hi_internal): Rename to...
(_tile_cvtrowps2bf16hi_internal): ...this.
(_tile_cvtrowps2pbf16l_internal): Rename to...
(_tile_cvtrowps2bf16l_internal): ...this.
(_tile_cvtrowps2pbf16li_internal): Rename to...
(_tile_cvtrowps2bf16li_internal): ...this.
(_tile_cvtrowps2pbf16h): Rename to...
(_tile_cvtrowps2bf16h): ...this.
(_tile_cvtrowps2pbf16hi): Rename to...
(_tile_cvtrowps2bf16hi): ...this.
(_tile_cvtrowps2pbf16l): Rename to...
(_tile_cvtrowps2bf16l): ...this.
(_tile_cvtrowps2pbf16li): Rename to...
(_tile_cvtrowps2bf16li): ...this.
2025-01-08 Hongyu Wang <hongyu.wang@intel.com>
* config/i386/i386.cc (ix86_noce_max_ifcvt_seq_cost): Adjust
cost with ix86_tune_cost->br_mispredict_scale.
* config/i386/i386.h (processor_costs): Add br_mispredict_scale.
* config/i386/x86-tune-costs.h: Add new br_mispredict_scale to
all processor_costs, in which icelake_cost/alderlake_cost
with value COSTS_N_INSNS (2) + 3 and other processor with value
COSTS_N_INSNS (2).
2025-01-07 Pan Li <pan2.li@intel.com>
* match.pd: Update comments for sat_* pattern.
2025-01-07 Pan Li <pan2.li@intel.com>
* match.pd: Extract saturated value match for signed SAT_*.
2025-01-07 Pan Li <pan2.li@intel.com>
* match.pd: Refactor sorts of signed SAT_TRUNC match patterns
2025-01-07 Pan Li <pan2.li@intel.com>
* match.pd: Refactor sorts of signed SAT_SUB match patterns.
2025-01-07 Vineet Gupta <vineetg@rivosinc.com>
Pan Li <pan2.li@intel.com>
PR target/117722
* config/riscv/autovec.md: Add uabd expander.
2025-01-07 Tsung Chun Lin <tclin914@gmail.com>
* expr.cc (widest_fixed_size_mode_for_size): Prefer scalar modes
over vector modes in more cases.
2025-01-07 Andreas Schwab <schwab@suse.de>
PR target/118137
* config/riscv/sync.md ("lrsc_atomic_exchange<mode>"): Apply mask
to shifted value.
2025-01-07 Jeff Law <jlaw@ventanamicro.com>
* config/ft32/ft32.md (casesi expander): Force operands[2] into
a register if it's not a suitable rimm operand.
2025-01-07 Wilco Dijkstra <wilco.dijkstra@arm.com>
* common/config/aarch64/aarch64-common.cc: Switch off fschedule_insns.
2025-01-07 Wilco Dijkstra <wilco.dijkstra@arm.com>
* config/aarch64/aarch64.md (movhf_aarch64): Use aarch64_valid_fp_move.
(movsf_aarch64): Likewise.
(movdf_aarch64): Likewise.
* config/aarch64/aarch64.cc (aarch64_valid_fp_move): New function.
* config/aarch64/aarch64-protos.h (aarch64_valid_fp_move): Likewise.
2025-01-07 Paul-Antoine Arras <parras@baylibre.com>
* gimplify.cc (gimplify_call_expr): Create variable
variant_substituted_p to control whether adjust_args applies.
2025-01-07 Tamar Christina <tamar.christina@arm.com>
PR tree-optimization/114932
* tree-ssa-loop-ivopts.cc (alloc_iv): Perform affine unsigned fold.
2025-01-07 Andrew Pinski <quic_apinski@quicinc.com>
PR tree-optimization/105769
* cfgexpand.cc (vars_ssa_cache::operator()): For constructors
walk over the elements.
2025-01-07 Andrew Pinski <quic_apinski@quicinc.com>
PR middle-end/117426
PR middle-end/111422
* cfgexpand.cc (struct vars_ssa_cache): New class.
(vars_ssa_cache::vars_ssa_cache): New constructor.
(vars_ssa_cache::~vars_ssa_cache): New deconstructor.
(vars_ssa_cache::create): New method.
(vars_ssa_cache::exists): New method.
(vars_ssa_cache::add_one): New method.
(vars_ssa_cache::update): New method.
(vars_ssa_cache::dump): New method.
(add_scope_conflicts_2): Factor mostly out to
vars_ssa_cache::operator(). New cache argument.
Walk the bitmap cache for the stack variables addresses.
(vars_ssa_cache::operator()): New method factored out from
add_scope_conflicts_2. Rewrite to be a full walk of all operands
and use a worklist.
(add_scope_conflicts_1): Add cache new argument for the addr cache.
Just call add_scope_conflicts_2 for the phi result instead of calling
for the uses and don't call walk_stmt_load_store_addr_ops for phis.
Update call to add_scope_conflicts_2 to add cache argument.
(add_scope_conflicts): Add cache argument and update calls to
add_scope_conflicts_1.
2025-01-07 Andrew Pinski <quic_apinski@quicinc.com>
* cfgexpand.cc (INVALID_STACK_INDEX): New defined.
(decl_stack_index): New function.
(visit_op): Use decl_stack_index.
(visit_conflict): Likewise.
(add_scope_conflicts_1): Likewise.
2025-01-07 Richard Biener <rguenther@suse.de>
PR rtl-optimization/118298
* loop-unroll.cc (decide_unroll_constant_iterations): Honor
loop->unroll even if the loop is too big for heuristics.
2025-01-07 Deng Jianbo <dengjianbo@loongson.cn>
* config/loongarch/loongarch.cc (loongarch_output_move):
Optimize instructions for initializing fp regsiter to zero.
2025-01-07 Gaius Mulley <gaiusmod2@gmail.com>
PR modula2/118010
* doc/gm2.texi (Compiler options): New option
-fm2-file-offset-bits=.
2025-01-07 Jennifer Schmitz <jschmitz@nvidia.com>
* tree-vect-stmts.cc (vectorizable_store): Extend the use of
n_adjacent_stores to also cover vec_to_scalar operations.
* config/aarch64/aarch64-tuning-flags.def: Remove
use_new_vector_costs as tuning option.
* config/aarch64/aarch64.cc (aarch64_use_new_vector_costs_p):
Remove.
(aarch64_vector_costs::add_stmt_cost): Remove use of
aarch64_use_new_vector_costs_p.
(aarch64_vector_costs::finish_cost): Remove use of
aarch64_use_new_vector_costs_p.
* config/aarch64/tuning_models/cortexx925.h: Remove
AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COSTS.
* config/aarch64/tuning_models/fujitsu_monaka.h: Likewise.
* config/aarch64/tuning_models/generic_armv8_a.h: Likewise.
* config/aarch64/tuning_models/generic_armv9_a.h: Likewise.
* config/aarch64/tuning_models/neoverse512tvb.h: Likewise.
* config/aarch64/tuning_models/neoversen2.h: Likewise.
* config/aarch64/tuning_models/neoversen3.h: Likewise.
* config/aarch64/tuning_models/neoversev1.h: Likewise.
* config/aarch64/tuning_models/neoversev2.h: Likewise.
* config/aarch64/tuning_models/neoversev3.h: Likewise.
* config/aarch64/tuning_models/neoversev3ae.h: Likewise.
2025-01-06 Alexandre Oliva <oliva@adacore.com>
PR middle-end/118006
* cfgexpand.cc (expand_gimple_basic_block): Do not emit
pending stack adjustments after a barrier.
2025-01-06 Akram Ahmad <Akram.Ahmad@arm.com>
* config/aarch64/aarch64-simd.md: (*aarch64_trunc_concat)
new insn definition.
2025-01-06 Fangrui Song <maskray@gcc.gnu.org>
PR gcov-profile/96092
* coverage.cc (coverage_init): Remap getpwd().
2025-01-06 Jennifer Schmitz <jschmitz@nvidia.com>
* config/aarch64/aarch64-sve-builtins-base.cc
(svmul_impl::fold): Wrap code for folding to svneg in lambda
function and pass to gimple_folder::convert_and_fold to enable
the transform for unsigned types.
* config/aarch64/aarch64-sve-builtins.cc
(gimple_folder::convert_and_fold): New function that converts
operands to target type before calling callback function, adding the
necessary conversion statements.
(gimple_folder::redirect_call): Set fntype of redirected call.
(get_vector_type): Move from here to aarch64-sve-builtins.h.
* config/aarch64/aarch64-sve-builtins.h
(gimple_folder::convert_and_fold): Declare function.
(get_vector_type): Move here as inline function.
2025-01-06 Martin Jambor <mjambor@suse.cz>
* ipa-cp.cc (ipcp_print_widest_int): New function.
(ipcp_store_vr_results): Use it.
(ipcp_bits_lattice::print): Likewise. Fix formatting.
2025-01-06 Mark Wielaard <mark@klomp.org>
PR tree-optimization/118032
* tree-switch-conversion.cc (jump_table_cluster::find_jump_tables):
Remove param_switch_lower_slow_alg_max_cases check.
2025-01-06 Tamar Christina <tamar.christina@arm.com>
PR target/96342
PR target/118272
* config/aarch64/aarch64-sve.md (vec_init<mode><Vquad>,
vec_initvnx16qivnx2qi): New.
* config/aarch64/aarch64.cc (aarch64_sve_expand_vector_init_subvector):
Rewrite to support any arbitrary combinations.
* config/aarch64/iterators.md (SVE_NO2E): Update to use SVE_NO4E
(SVE_NO2E, Vquad): New.
2025-01-06 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/118224
* tree-ssa-dce.cc (is_removable_allocation_p): Don't return true
for allocations with constant size argument larger than PTRDIFF_MAX
or for calloc with one of the arguments constant larger than
PTRDIFF_MAX or their product known constant above PTRDIFF_MAX.
Fix comment typos, furhter -> further and then -> than.
* lto-section-in.cc (lto_free_function_in_decl_state_for_node):
Fix comment typo, furhter -> further.
2025-01-04 Hans-Peter Nilsson <hp@axis.com>
* config/mmix/mmix.cc (mmix_asm_output_labelref): Replace '.'
with '::'.
* config/mmix/mmix.h (ASM_PN_FORMAT): Define to actual default.
2025-01-03 Richard Sandiford <richard.sandiford@arm.com>
PR rtl-optimization/117938
* rtlanal.cc (rtx_properties::try_to_add_dest): Treat writes
to the stack pointer as also writing to memory.
2025-01-03 Jakub Jelinek <jakub@redhat.com>
PR c++/118275
* varasm.cc (array_size_for_constructor): Use build_int_cst
with TREE_TYPE (index) as first argument, instead of bitsize_int.
2025-01-03 Jakub Jelinek <jakub@redhat.com>
* tree-ssa-forwprop.cc (check_ctz_array): Use tree_fits_shwi_p instead
of just TREE_CODE tests for INTEGER_CST.
2025-01-03 Jose E. Marchesi <jose.marchesi@oracle.com>
* config.gcc: install a wrapping stdint.h in bpf targets.
2025-01-02 Paul-Antoine Arras <parras@baylibre.com>
* gimplify.cc (gimplify_call_expr): Fix handling of need_device_ptr for
type(c_ptr). Fix handling of nested function calls in a dispatch region.
(find_ifn_gomp_dispatch): Return the IFN without stripping it.
(gimplify_omp_dispatch): Keep IFN_GOMP_DISPATCH until
gimplify_call_expr.
2025-01-02 Tobias Burnus <tburnus@baylibre.com>
* doc/install.texi (amdgcn-x-amdhsa): Refer to Newlib 4.5.0 for
the I/O locking fixes.
2025-01-02 Richard Biener <rguenther@suse.de>
PR tree-optimization/118171
* tree-ssa-pre.cc (create_component_ref_by_pieces_1): Do not
fold any component ref parts.
2025-01-02 Richard Sandiford <richard.sandiford@arm.com>
PR target/118184
* config/aarch64/aarch64-early-ra.cc (allocno_assignment_is_rmw):
New function.
(early_ra::record_insn_defs): Mark the live range information as
untrustworthy if an assignment would change part of an allocno
but preserve the rest.
2025-01-02 Jakub Jelinek <jakub@redhat.com>
* tree-ssa-forwprop.cc (check_ctz_array): Handle also RAW_DATA_CST
in the CONSTRUCTOR_ELTS.
2025-01-02 Jakub Jelinek <jakub@redhat.com>
* doc/libgdiagnostics/conf.py: Use u'' instead of '' in
project and copyright initialization.
2025-01-02 Jakub Jelinek <jakub@redhat.com>
* gcc.cc (process_command): Update copyright notice dates.
* gcov-dump.cc (print_version): Ditto.
* gcov.cc (print_version): Ditto.
* gcov-tool.cc (print_version): Ditto.
* gengtype.cc (create_file): Ditto.
* doc/cpp.texi: Bump @copying's copyright year.
* doc/cppinternals.texi: Ditto.
* doc/gcc.texi: Ditto.
* doc/gccint.texi: Ditto.
* doc/gcov.texi: Ditto.
* doc/install.texi: Ditto.
* doc/invoke.texi: Ditto.
2025-01-02 Guo Jie <guojie@loongson.cn>
* config/loongarch/loongarch.cc
(loongarch_expand_conditional_move): Add some optimization
implementations based on noce_try_cmove_arith.
2025-01-02 Guo Jie <guojie@loongson.cn>
* config/loongarch/lasx.md (lasx_xvabsd_s_<lasxfmt>): Remove.
(<su>abd<mode>3): New insn pattern.
(lasx_xvabsd_u_<lasxfmt_u>): Remove.
* config/loongarch/loongarch-builtins.cc (CODE_FOR_lsx_vabsd_b):
Rename.
(CODE_FOR_lsx_vabsd_h): Ditto.
(CODE_FOR_lsx_vabsd_w): Ditto.
(CODE_FOR_lsx_vabsd_d): Ditto.
(CODE_FOR_lsx_vabsd_bu): Ditto.
(CODE_FOR_lsx_vabsd_hu): Ditto.
(CODE_FOR_lsx_vabsd_wu): Ditto.
(CODE_FOR_lsx_vabsd_du): Ditto.
(CODE_FOR_lasx_xvabsd_b): Ditto.
(CODE_FOR_lasx_xvabsd_h): Ditto.
(CODE_FOR_lasx_xvabsd_w): Ditto.
(CODE_FOR_lasx_xvabsd_d): Ditto.
(CODE_FOR_lasx_xvabsd_bu): Ditto.
(CODE_FOR_lasx_xvabsd_hu): Ditto.
(CODE_FOR_lasx_xvabsd_wu): Ditto.
(CODE_FOR_lasx_xvabsd_du): Ditto.
* config/loongarch/loongarch.md (u): Add smax/umax.
* config/loongarch/lsx.md (SU_MAX): New iterator.
(su_min): New attr.
(lsx_vabsd_s_<lsxfmt>): Remove.
(<su>abd<mode>3): New insn pattern.
(lsx_vabsd_u_<lsxfmt_u>): Remove.
2025-01-02 Guo Jie <guojie@loongson.cn>
* config/loongarch/lasx.md (vec_unpacks_lo_<mode>): Redefine.
(vec_unpacku_lo_<mode>): Ditto.
(lasx_vext2xv_h<u>_b<u>): Replaced by vec_unpack<su>_lo_v32qi.
(vec_unpack<su>_lo_v32qi): New insn.
(lasx_vext2xv_w<u>_h<u>): Replaced by vec_unpack<su>_lo_v16hi.
(vec_unpack<su>_lo_v16qi_internal): New insn, for 128 bits.
(vec_unpack<su>_lo_v16hi): New insn.
(lasx_vext2xv_d<u>_w<u>): Replaced by vec_unpack<su>_lo_v8si.
(vec_unpack<su>_lo_v8hi_internal): New insn, for 128 bits.
(vec_unpack<su>_lo_v8si): New insn.
(vec_unpack<su>_lo_v4si_internal): New insn, for 128 bits.
(vec_packs_float_v4di): New expander.
(vec_pack_sfix_trunc_v4df): Ditto.
(vec_unpacks_float_hi_v8si): Ditto.
(vec_unpacks_float_lo_v8si): Ditto.
(vec_unpack_sfix_trunc_hi_v8sf): Ditto.
(vec_unpack_sfix_trunc_lo_v8sf): Ditto.
* config/loongarch/loongarch-builtins.cc
(CODE_FOR_lsx_vftintrz_w_d): Rename.
(CODE_FOR_lsx_vftintrzh_l_s): Ditto.
(CODE_FOR_lsx_vftintrzl_l_s): Ditto.
(CODE_FOR_lsx_vffint_s_l): Ditto.
(CODE_FOR_lsx_vffinth_d_w): Ditto.
(CODE_FOR_lsx_vffintl_d_w): Ditto.
(CODE_FOR_lsx_vexth_h_b): Ditto.
(CODE_FOR_lsx_vexth_w_h): Ditto.
(CODE_FOR_lsx_vexth_d_w): Ditto.
(CODE_FOR_lsx_vexth_hu_bu): Ditto.
(CODE_FOR_lsx_vexth_wu_hu): Ditto.
(CODE_FOR_lsx_vexth_du_wu): Ditto.
(CODE_FOR_lsx_vfcvth_d_s): Ditto.
(CODE_FOR_lsx_vfcvtl_d_s): Ditto.
(CODE_FOR_lasx_vext2xv_h_b): Ditto.
(CODE_FOR_lasx_vext2xv_w_h): Ditto.
(CODE_FOR_lasx_vext2xv_d_w): Ditto.
(CODE_FOR_lasx_vext2xv_hu_bu): Ditto.
(CODE_FOR_lasx_vext2xv_wu_hu): Ditto.
(CODE_FOR_lasx_vext2xv_du_wu): Ditto.
(loongarch_expand_builtin_insn): Swap source operands in
CODE_FOR_lsx_vftintrz_w_d and CODE_FOR_lsx_vffint_s_l.
* config/loongarch/loongarch-protos.h
(loongarch_expand_vec_unpack): Remove useless parameter high_p.
* config/loongarch/loongarch.cc (loongarch_expand_vec_unpack):
Rewrite.
* config/loongarch/lsx.md (vec_unpacks_hi_v4sf): Redefine.
(vec_unpacks_lo_v4sf): Ditto.
(vec_unpacks_hi_<mode>): Ditto.
(vec_unpacku_hi_<mode>): Ditto.
(lsx_vfcvth_d_s): Replaced by vec_unpacks_hi_v4sf.
(lsx_vfcvtl_d_s): Replaced by vec_unpacks_lo_v4sf.
(lsx_vffint_s_l): Replaced by vec_packs_float_v2di.
(vec_packs_float_v2di): New insn.
(lsx_vftintrz_w_d): Replaced by vec_pack_sfix_trunc_v2df.
(vec_pack_sfix_trunc_v2df): New insn.
(lsx_vffinth_d_w): Replaced by vec_unpacks_float_hi_v4si.
(vec_unpacks_float_hi_v4si): New insn.
(lsx_vffintl_d_w): Replaced by vec_unpacks_float_lo_v4si.
(vec_unpacks_float_lo_v4si): New insn.
(lsx_vftintrzh_l_s): Replaced by vec_unpack_sfix_trunc_hi_v4sf.
(vec_unpack_sfix_trunc_hi_v4sf): New insn.
(lsx_vftintrzl_l_s): Replaced by vec_unpack_sfix_trunc_lo_v4sf.
(vec_unpack_sfix_trunc_lo_v4sf): New insn.
(lsx_vexth_h<u>_b<u>): Replaced by vec_unpack<su>_hi_v16qi.
(vec_unpack<su>_hi_v16qi): New insn.
(lsx_vexth_w<u>_h<u>): Replaced by vec_unpack<su>_hi_v8hi.
(vec_unpack<su>_hi_v8hi): New insn.
(lsx_vexth_d<u>_w<u>): Replaced by vec_unpack<su>_hi_v4si.
(vec_unpack<su>_hi_v4si): New insn.
2025-01-02 Guo Jie <guojie@loongson.cn>
* config/loongarch/loongarch.md
(bytepick_d_<bytepick_imm>_rev): New combiner.
(bstrpick_alsl_paired): Reorder input operands.
2025-01-02 Guo Jie <guojie@loongson.cn>
* config/loongarch/lasx.md: Remove useless vec_select.
* config/loongarch/predicates.md: Correct error predicate.
2025-01-02 Guo Jie <guojie@loongson.cn>
* config/loongarch/lasx.md: Fix selector index.
2025-01-02 Guo Jie <guojie@loongson.cn>
* config/loongarch/lasx.md: Remove useless code.
* config/loongarch/lsx.md: Ditto.
2025-01-01 Sam James <sam@gentoo.org>
* doc/cpp.texi (Common Predefined Macros): Fix syntax.
2025-01-01 Richard Biener <rguenther@suse.de>
PR middle-end/118174
* tree-outof-ssa.cc (ssa_is_replaceable_p): Exclude tailcalls.
2025-01-01 Sandra Loosemore <sloosemore@baylibre.com>
* doc/invoke.texi (Option Summary): Put "M32C Options" and
"Cygwin and MinGW Options" in alphabetical order. Add
cross-references.
(Cygwin and MinGW Options): Likewise move the section to its
correct alphabetical location.
* config/lynx.opt.urls: Regenerated.
* config/mingw/cygming.opt.urls: Regenerated.
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