blob: 8244f37bf03dce3b70fe513a2a6e194d7d8304ff [file] [log] [blame]
/* Subroutines used for code generation on the Synopsys DesignWare ARC cpu.
Copyright (C) 1994-2021 Free Software Foundation, Inc.
Sources derived from work done by Sankhya Technologies (www.sankhya.com) on
behalf of Synopsys Inc.
Position Independent Code support added,Code cleaned up,
Comments and Support For ARC700 instructions added by
Saurabh Verma (saurabh.verma@codito.com)
Ramana Radhakrishnan(ramana.radhakrishnan@codito.com)
Fixing ABI inconsistencies, optimizations for ARC600 / ARC700 pipelines,
profiling support added by Joern Rennecke <joern.rennecke@embecosm.com>
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#define IN_TARGET_CODE 1
#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "memmodel.h"
#include "backend.h"
#include "target.h"
#include "rtl.h"
#include "tree.h"
#include "cfghooks.h"
#include "df.h"
#include "tm_p.h"
#include "stringpool.h"
#include "attribs.h"
#include "optabs.h"
#include "regs.h"
#include "emit-rtl.h"
#include "recog.h"
#include "diagnostic.h"
#include "fold-const.h"
#include "varasm.h"
#include "stor-layout.h"
#include "calls.h"
#include "output.h"
#include "insn-attr.h"
#include "flags.h"
#include "explow.h"
#include "expr.h"
#include "langhooks.h"
#include "tm-constrs.h"
#include "reload.h" /* For operands_match_p */
#include "cfgrtl.h"
#include "tree-pass.h"
#include "context.h"
#include "builtins.h"
#include "rtl-iter.h"
#include "alias.h"
#include "opts.h"
#include "hw-doloop.h"
/* Which cpu we're compiling for (ARC600, ARC601, ARC700). */
static char arc_cpu_name[10] = "";
static const char *arc_cpu_string = arc_cpu_name;
typedef struct GTY (()) _arc_jli_section
{
const char *name;
struct _arc_jli_section *next;
} arc_jli_section;
static arc_jli_section *arc_jli_sections = NULL;
/* Track which regs are set fixed/call saved/call used from commnad line. */
HARD_REG_SET overrideregs;
/* Maximum size of a loop. */
#define ARC_MAX_LOOP_LENGTH 4095
/* Check if an rtx fits in the store instruction format. Loads can
handle any constant. */
#define RTX_OK_FOR_OFFSET_P(MODE, X) \
(GET_CODE (X) == CONST_INT \
&& SMALL_INT_RANGE (INTVAL (X), (GET_MODE_SIZE (MODE) - 1) & (~0x03), \
(INTVAL (X) & (GET_MODE_SIZE (MODE) - 1) & 3 \
? 0 \
: -(-GET_MODE_SIZE (MODE) | (~0x03)) >> 1)))
/* Array of valid operand punctuation characters. */
char arc_punct_chars[256];
/* State used by arc_ccfsm_advance to implement conditional execution. */
struct GTY (()) arc_ccfsm
{
int state;
int cc;
rtx cond;
rtx_insn *target_insn;
int target_label;
};
/* Status of the IRQ_CTRL_AUX register. */
typedef struct irq_ctrl_saved_t
{
/* Last register number used by IRQ_CTRL_SAVED aux_reg. */
short irq_save_last_reg;
/* True if BLINK is automatically saved. */
bool irq_save_blink;
/* True if LPCOUNT is automatically saved. */
bool irq_save_lpcount;
} irq_ctrl_saved_t;
static irq_ctrl_saved_t irq_ctrl_saved;
#define ARC_AUTOBLINK_IRQ_P(FNTYPE) \
((ARC_INTERRUPT_P (FNTYPE) \
&& irq_ctrl_saved.irq_save_blink) \
|| (ARC_FAST_INTERRUPT_P (FNTYPE) \
&& rgf_banked_register_count > 8))
#define ARC_AUTOFP_IRQ_P(FNTYPE) \
((ARC_INTERRUPT_P (FNTYPE) \
&& (irq_ctrl_saved.irq_save_last_reg > 26)) \
|| (ARC_FAST_INTERRUPT_P (FNTYPE) \
&& rgf_banked_register_count > 8))
#define ARC_AUTO_IRQ_P(FNTYPE) \
(ARC_INTERRUPT_P (FNTYPE) && !ARC_FAST_INTERRUPT_P (FNTYPE) \
&& (irq_ctrl_saved.irq_save_blink \
|| (irq_ctrl_saved.irq_save_last_reg >= 0)))
/* Number of registers in second bank for FIRQ support. */
static int rgf_banked_register_count;
#define arc_ccfsm_current cfun->machine->ccfsm_current
#define ARC_CCFSM_BRANCH_DELETED_P(STATE) \
((STATE)->state == 1 || (STATE)->state == 2)
/* Indicate we're conditionalizing insns now. */
#define ARC_CCFSM_RECORD_BRANCH_DELETED(STATE) \
((STATE)->state += 2)
#define ARC_CCFSM_COND_EXEC_P(STATE) \
((STATE)->state == 3 || (STATE)->state == 4 || (STATE)->state == 5 \
|| current_insn_predicate)
/* Check if INSN has a 16 bit opcode considering struct arc_ccfsm *STATE. */
#define CCFSM_ISCOMPACT(INSN,STATE) \
(ARC_CCFSM_COND_EXEC_P (STATE) \
? (get_attr_iscompact (INSN) == ISCOMPACT_TRUE \
|| get_attr_iscompact (INSN) == ISCOMPACT_TRUE_LIMM) \
: get_attr_iscompact (INSN) != ISCOMPACT_FALSE)
/* Likewise, but also consider that INSN might be in a delay slot of JUMP. */
#define CCFSM_DBR_ISCOMPACT(INSN,JUMP,STATE) \
((ARC_CCFSM_COND_EXEC_P (STATE) \
|| (JUMP_P (JUMP) \
&& INSN_ANNULLED_BRANCH_P (JUMP) \
&& (TARGET_AT_DBR_CONDEXEC || INSN_FROM_TARGET_P (INSN)))) \
? (get_attr_iscompact (INSN) == ISCOMPACT_TRUE \
|| get_attr_iscompact (INSN) == ISCOMPACT_TRUE_LIMM) \
: get_attr_iscompact (INSN) != ISCOMPACT_FALSE)
/* Start enter/leave register range. */
#define ENTER_LEAVE_START_REG 13
/* End enter/leave register range. */
#define ENTER_LEAVE_END_REG 26
/* The maximum number of insns skipped which will be conditionalised if
possible. */
/* When optimizing for speed:
Let p be the probability that the potentially skipped insns need to
be executed, pn the cost of a correctly predicted non-taken branch,
mt the cost of a mis/non-predicted taken branch,
mn mispredicted non-taken, pt correctly predicted taken ;
costs expressed in numbers of instructions like the ones considered
skipping.
Unfortunately we don't have a measure of predictability - this
is linked to probability only in that in the no-eviction-scenario
there is a lower bound 1 - 2 * min (p, 1-p), and a somewhat larger
value that can be assumed *if* the distribution is perfectly random.
A predictability of 1 is perfectly plausible not matter what p is,
because the decision could be dependent on an invocation parameter
of the program.
For large p, we want MAX_INSNS_SKIPPED == pn/(1-p) + mt - pn
For small p, we want MAX_INSNS_SKIPPED == pt
When optimizing for size:
We want to skip insn unless we could use 16 opcodes for the
non-conditionalized insn to balance the branch length or more.
Performance can be tie-breaker. */
/* If the potentially-skipped insns are likely to be executed, we'll
generally save one non-taken branch
o
this to be no less than the 1/p */
#define MAX_INSNS_SKIPPED 3
/* ZOL control registers. */
#define AUX_LP_START 0x02
#define AUX_LP_END 0x03
/* FPX AUX registers. */
#define AUX_DPFP_START 0x301
/* ARC600 MULHI register. */
#define AUX_MULHI 0x12
/* A nop is needed between a 4 byte insn that sets the condition codes and
a branch that uses them (the same isn't true for an 8 byte insn that sets
the condition codes). Set by arc_ccfsm_advance. Used by
arc_print_operand. */
static int get_arc_condition_code (rtx);
static tree arc_handle_interrupt_attribute (tree *, tree, tree, int, bool *);
static tree arc_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
static tree arc_handle_jli_attribute (tree *, tree, tree, int, bool *);
static tree arc_handle_secure_attribute (tree *, tree, tree, int, bool *);
static tree arc_handle_uncached_attribute (tree *, tree, tree, int, bool *);
static tree arc_handle_aux_attribute (tree *, tree, tree, int, bool *);
/* Initialized arc_attribute_table to NULL since arc doesnot have any
machine specific supported attributes. */
const struct attribute_spec arc_attribute_table[] =
{
/* { name, min_len, max_len, decl_req, type_req, fn_type_req,
affects_type_identity, handler, exclude } */
{ "interrupt", 1, 1, true, false, false, true,
arc_handle_interrupt_attribute, NULL },
/* Function calls made to this symbol must be done indirectly, because
it may lie outside of the 21/25 bit addressing range of a normal function
call. */
{ "long_call", 0, 0, false, true, true, false, NULL, NULL },
/* Whereas these functions are always known to reside within the 25 bit
addressing range of unconditionalized bl. */
{ "medium_call", 0, 0, false, true, true, false, NULL, NULL },
/* And these functions are always known to reside within the 21 bit
addressing range of blcc. */
{ "short_call", 0, 0, false, true, true, false, NULL, NULL },
/* Function which are not having the prologue and epilogue generated
by the compiler. */
{ "naked", 0, 0, true, false, false, false, arc_handle_fndecl_attribute,
NULL },
/* Functions calls made using jli instruction. The pointer in JLI
table is found latter. */
{ "jli_always", 0, 0, false, true, true, false, NULL, NULL },
/* Functions calls made using jli instruction. The pointer in JLI
table is given as input parameter. */
{ "jli_fixed", 1, 1, false, true, true, false, arc_handle_jli_attribute,
NULL },
/* Call a function using secure-mode. */
{ "secure_call", 1, 1, false, true, true, false, arc_handle_secure_attribute,
NULL },
/* Bypass caches using .di flag. */
{ "uncached", 0, 0, false, true, false, false, arc_handle_uncached_attribute,
NULL },
{ "aux", 0, 1, true, false, false, false, arc_handle_aux_attribute, NULL },
{ NULL, 0, 0, false, false, false, false, NULL, NULL }
};
static int arc_comp_type_attributes (const_tree, const_tree);
static void arc_file_start (void);
static void arc_internal_label (FILE *, const char *, unsigned long);
static void arc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
tree);
static int arc_address_cost (rtx, machine_mode, addr_space_t, bool);
static void arc_encode_section_info (tree decl, rtx rtl, int first);
static void arc_init_builtins (void);
static rtx arc_expand_builtin (tree, rtx, rtx, machine_mode, int);
static int branch_dest (rtx);
static void arc_output_pic_addr_const (FILE *, rtx, int);
static bool arc_function_ok_for_sibcall (tree, tree);
static rtx arc_function_value (const_tree, const_tree, bool);
const char * output_shift (rtx *);
static void arc_reorg (void);
static bool arc_in_small_data_p (const_tree);
static void arc_init_reg_tables (void);
static bool arc_return_in_memory (const_tree, const_tree);
static bool arc_vector_mode_supported_p (machine_mode);
static bool arc_can_use_doloop_p (const widest_int &, const widest_int &,
unsigned int, bool);
static const char *arc_invalid_within_doloop (const rtx_insn *);
static void output_short_suffix (FILE *file);
static bool arc_frame_pointer_required (void);
static bool arc_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT,
unsigned int,
enum by_pieces_operation op,
bool);
/* Globally visible information about currently selected cpu. */
const arc_cpu_t *arc_selected_cpu;
/* Traditionally, we push saved registers first in the prologue,
then we allocate the rest of the frame - and reverse in the epilogue.
This has still its merits for ease of debugging, or saving code size
or even execution time if the stack frame is so large that some accesses
can't be encoded anymore with offsets in the instruction code when using
a different scheme.
Also, it would be a good starting point if we got instructions to help
with register save/restore.
However, often stack frames are small, and the pushing / popping has
some costs:
- the stack modification prevents a lot of scheduling.
- frame allocation / deallocation may need extra instructions.
- we need to place a memory barrier after frame allocation to avoid
the delay slot scheduler to reschedule a frame related info and
messing up with dwarf unwinding. The barrier before deallocation
is for flushing all pending sp operations.
Thus, for small frames, we'd like to use a different scheme:
- The frame is allocated in full with the first prologue instruction,
and deallocated in full with the last epilogue instruction.
Thus, the instructions in-between can be freely scheduled.
- If the function has no outgoing arguments on the stack, we can allocate
one register save slot at the top of the stack. This register can then
be saved simultaneously with frame allocation, and restored with
frame deallocation.
This register can be picked depending on scheduling considerations,
although same though should go into having some set of registers
to be potentially lingering after a call, and others to be available
immediately - i.e. in the absence of interprocedual optimization, we
can use an ABI-like convention for register allocation to reduce
stalls after function return. */
/* ARCompact stack frames look like:
Before call After call
high +-----------------------+ +-----------------------+
mem | reg parm save area | | reg parm save area |
| only created for | | only created for |
| variable arg fns | | variable arg fns |
AP +-----------------------+ +-----------------------+
| return addr register | | return addr register |
| (if required) | | (if required) |
+-----------------------+ +-----------------------+
| | | |
| reg save area | | reg save area |
| | | |
+-----------------------+ +-----------------------+
| frame pointer | | frame pointer |
| (if required) | | (if required) |
FP +-----------------------+ +-----------------------+
| | | |
| local/temp variables | | local/temp variables |
| | | |
+-----------------------+ +-----------------------+
| | | |
| arguments on stack | | arguments on stack |
| | | |
SP +-----------------------+ +-----------------------+
| reg parm save area |
| only created for |
| variable arg fns |
AP +-----------------------+
| return addr register |
| (if required) |
+-----------------------+
| |
| reg save area |
| |
+-----------------------+
| frame pointer |
| (if required) |
FP +-----------------------+
| |
| local/temp variables |
| |
+-----------------------+
| |
| arguments on stack |
low | |
mem SP +-----------------------+
Notes:
1) The "reg parm save area" does not exist for non variable argument fns.
The "reg parm save area" can be eliminated completely if we created our
own va-arc.h, but that has tradeoffs as well (so it's not done). */
/* Structure to be filled in by arc_compute_frame_size with register
save masks, and offsets for the current function. */
struct GTY (()) arc_frame_info
{
unsigned int total_size; /* # bytes that the entire frame takes up. */
unsigned int extra_size; /* # bytes of extra stuff. */
unsigned int pretend_size; /* # bytes we push and pretend caller did. */
unsigned int args_size; /* # bytes that outgoing arguments take up. */
unsigned int reg_size; /* # bytes needed to store regs. */
unsigned int var_size; /* # bytes that variables take up. */
uint64_t gmask; /* Mask of saved gp registers. */
bool initialized; /* FALSE if frame size already calculated. */
short millicode_start_reg;
short millicode_end_reg;
bool save_return_addr;
};
/* GMASK bit length -1. */
#define GMASK_LEN 63
/* Defining data structures for per-function information. */
typedef struct GTY (()) machine_function
{
unsigned int fn_type;
struct arc_frame_info frame_info;
/* To keep track of unalignment caused by short insns. */
int unalign;
struct arc_ccfsm ccfsm_current;
/* Map from uid to ccfsm state during branch shortening. */
rtx ccfsm_current_insn;
char arc_reorg_started;
char prescan_initialized;
} machine_function;
/* Given a symbol RTX (const (symb <+ const_int>), returns its
alignment. */
static int
get_symbol_alignment (rtx x)
{
tree decl = NULL_TREE;
int align = 0;
switch (GET_CODE (x))
{
case SYMBOL_REF:
decl = SYMBOL_REF_DECL (x);
break;
case CONST:
return get_symbol_alignment (XEXP (x, 0));
case PLUS:
gcc_assert (CONST_INT_P (XEXP (x, 1)));
return get_symbol_alignment (XEXP (x, 0));
default:
return 0;
}
if (decl)
align = DECL_ALIGN (decl);
align = align / BITS_PER_UNIT;
return align;
}
/* Return true if x is ok to be used as a small data address. */
static bool
legitimate_small_data_address_p (rtx x, machine_mode mode)
{
switch (GET_CODE (x))
{
case CONST:
return legitimate_small_data_address_p (XEXP (x, 0), mode);
case SYMBOL_REF:
return SYMBOL_REF_SMALL_P (x);
case PLUS:
{
bool p0 = (GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
&& SYMBOL_REF_SMALL_P (XEXP (x, 0));
/* If no constant then we cannot do small data. */
if (!CONST_INT_P (XEXP (x, 1)))
return false;
/* Small data relocs works with scalled addresses, check if
the immediate fits the requirements. */
switch (GET_MODE_SIZE (mode))
{
case 1:
return p0;
case 2:
return p0 && ((INTVAL (XEXP (x, 1)) & 0x1) == 0);
case 4:
case 8:
return p0 && ((INTVAL (XEXP (x, 1)) & 0x3) == 0);
default:
return false;
}
}
default:
return false;
}
}
/* TRUE if op is an scaled address. */
static bool
legitimate_scaled_address_p (machine_mode mode, rtx op, bool strict)
{
if (GET_CODE (op) != PLUS)
return false;
if (GET_CODE (XEXP (op, 0)) != MULT)
return false;
/* Check multiplication operands. */
if (!RTX_OK_FOR_INDEX_P (XEXP (XEXP (op, 0), 0), strict))
return false;
if (!CONST_INT_P (XEXP (XEXP (op, 0), 1)))
return false;
switch (GET_MODE_SIZE (mode))
{
case 2:
if (INTVAL (XEXP (XEXP (op, 0), 1)) != 2)
return false;
break;
case 8:
if (!TARGET_LL64)
return false;
/* Fall through. */
case 4:
if (INTVAL (XEXP (XEXP (op, 0), 1)) != 4)
return false;
/* Fall through. */
default:
return false;
}
/* Check the base. */
if (RTX_OK_FOR_BASE_P (XEXP (op, 1), (strict)))
return true;
if (flag_pic)
{
if (CONST_INT_P (XEXP (op, 1)))
return true;
return false;
}
/* Scalled addresses for sdata is done other places. */
if (legitimate_small_data_address_p (op, mode))
return false;
if (CONSTANT_P (XEXP (op, 1)))
return true;
return false;
}
/* Check for constructions like REG + OFFS, where OFFS can be a
register, an immediate or an long immediate. */
static bool
legitimate_offset_address_p (machine_mode mode, rtx x, bool index, bool strict)
{
if (GET_CODE (x) != PLUS)
return false;
if (!RTX_OK_FOR_BASE_P (XEXP (x, 0), (strict)))
return false;
/* Check for: [Rx + small offset] or [Rx + Ry]. */
if (((index && RTX_OK_FOR_INDEX_P (XEXP (x, 1), (strict))
&& GET_MODE_SIZE ((mode)) <= 4)
|| RTX_OK_FOR_OFFSET_P (mode, XEXP (x, 1))))
return true;
/* Check for [Rx + symbol]. */
if (!flag_pic
&& (GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
/* Avoid this type of address for double or larger modes. */
&& (GET_MODE_SIZE (mode) <= 4)
/* Avoid small data which ends in something like GP +
symb@sda. */
&& (!SYMBOL_REF_SMALL_P (XEXP (x, 1))))
return true;
return false;
}
/* Implements target hook vector_mode_supported_p. */
static bool
arc_vector_mode_supported_p (machine_mode mode)
{
switch (mode)
{
case E_V2HImode:
return TARGET_PLUS_DMPY;
case E_V4HImode:
case E_V2SImode:
return TARGET_PLUS_QMACW;
case E_V4SImode:
case E_V8HImode:
return TARGET_SIMD_SET;
default:
return false;
}
}
/* Implements target hook TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
static machine_mode
arc_preferred_simd_mode (scalar_mode mode)
{
switch (mode)
{
case E_HImode:
return TARGET_PLUS_QMACW ? V4HImode : V2HImode;
case E_SImode:
return V2SImode;
default:
return word_mode;
}
}
/* Implements target hook
TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES. */
static unsigned int
arc_autovectorize_vector_modes (vector_modes *modes, bool)
{
if (TARGET_PLUS_QMACW)
{
modes->quick_push (V4HImode);
modes->quick_push (V2HImode);
}
return 0;
}
/* Implements target hook TARGET_SCHED_ISSUE_RATE. */
static int
arc_sched_issue_rate (void)
{
switch (arc_tune)
{
case TUNE_ARCHS4X:
case TUNE_ARCHS4XD:
return 3;
default:
break;
}
return 1;
}
/* TARGET_PRESERVE_RELOAD_P is still awaiting patch re-evaluation / review. */
static bool arc_preserve_reload_p (rtx in) ATTRIBUTE_UNUSED;
static rtx arc_delegitimize_address (rtx);
static bool arc_can_follow_jump (const rtx_insn *follower,
const rtx_insn *followee);
static rtx frame_insn (rtx);
static void arc_function_arg_advance (cumulative_args_t,
const function_arg_info &);
static rtx arc_legitimize_address_0 (rtx, rtx, machine_mode mode);
/* initialize the GCC target structure. */
#undef TARGET_COMP_TYPE_ATTRIBUTES
#define TARGET_COMP_TYPE_ATTRIBUTES arc_comp_type_attributes
#undef TARGET_ASM_FILE_START
#define TARGET_ASM_FILE_START arc_file_start
#undef TARGET_ATTRIBUTE_TABLE
#define TARGET_ATTRIBUTE_TABLE arc_attribute_table
#undef TARGET_ASM_INTERNAL_LABEL
#define TARGET_ASM_INTERNAL_LABEL arc_internal_label
#undef TARGET_RTX_COSTS
#define TARGET_RTX_COSTS arc_rtx_costs
#undef TARGET_ADDRESS_COST
#define TARGET_ADDRESS_COST arc_address_cost
#undef TARGET_ENCODE_SECTION_INFO
#define TARGET_ENCODE_SECTION_INFO arc_encode_section_info
#undef TARGET_CANNOT_FORCE_CONST_MEM
#define TARGET_CANNOT_FORCE_CONST_MEM arc_cannot_force_const_mem
#undef TARGET_INIT_BUILTINS
#define TARGET_INIT_BUILTINS arc_init_builtins
#undef TARGET_EXPAND_BUILTIN
#define TARGET_EXPAND_BUILTIN arc_expand_builtin
#undef TARGET_BUILTIN_DECL
#define TARGET_BUILTIN_DECL arc_builtin_decl
#undef TARGET_ASM_OUTPUT_MI_THUNK
#define TARGET_ASM_OUTPUT_MI_THUNK arc_output_mi_thunk
#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
#undef TARGET_FUNCTION_OK_FOR_SIBCALL
#define TARGET_FUNCTION_OK_FOR_SIBCALL arc_function_ok_for_sibcall
#undef TARGET_MACHINE_DEPENDENT_REORG
#define TARGET_MACHINE_DEPENDENT_REORG arc_reorg
#undef TARGET_IN_SMALL_DATA_P
#define TARGET_IN_SMALL_DATA_P arc_in_small_data_p
#undef TARGET_PROMOTE_FUNCTION_MODE
#define TARGET_PROMOTE_FUNCTION_MODE \
default_promote_function_mode_always_promote
#undef TARGET_PROMOTE_PROTOTYPES
#define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
#undef TARGET_RETURN_IN_MEMORY
#define TARGET_RETURN_IN_MEMORY arc_return_in_memory
#undef TARGET_PASS_BY_REFERENCE
#define TARGET_PASS_BY_REFERENCE arc_pass_by_reference
#undef TARGET_SETUP_INCOMING_VARARGS
#define TARGET_SETUP_INCOMING_VARARGS arc_setup_incoming_varargs
#undef TARGET_ARG_PARTIAL_BYTES
#define TARGET_ARG_PARTIAL_BYTES arc_arg_partial_bytes
#undef TARGET_MUST_PASS_IN_STACK
#define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
#undef TARGET_FUNCTION_VALUE
#define TARGET_FUNCTION_VALUE arc_function_value
#undef TARGET_SCHED_ADJUST_PRIORITY
#define TARGET_SCHED_ADJUST_PRIORITY arc_sched_adjust_priority
#undef TARGET_SCHED_ISSUE_RATE
#define TARGET_SCHED_ISSUE_RATE arc_sched_issue_rate
#undef TARGET_VECTOR_MODE_SUPPORTED_P
#define TARGET_VECTOR_MODE_SUPPORTED_P arc_vector_mode_supported_p
#undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
#define TARGET_VECTORIZE_PREFERRED_SIMD_MODE arc_preferred_simd_mode
#undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES
#define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES arc_autovectorize_vector_modes
#undef TARGET_CAN_USE_DOLOOP_P
#define TARGET_CAN_USE_DOLOOP_P arc_can_use_doloop_p
#undef TARGET_INVALID_WITHIN_DOLOOP
#define TARGET_INVALID_WITHIN_DOLOOP arc_invalid_within_doloop
#undef TARGET_PRESERVE_RELOAD_P
#define TARGET_PRESERVE_RELOAD_P arc_preserve_reload_p
#undef TARGET_CAN_FOLLOW_JUMP
#define TARGET_CAN_FOLLOW_JUMP arc_can_follow_jump
#undef TARGET_DELEGITIMIZE_ADDRESS
#define TARGET_DELEGITIMIZE_ADDRESS arc_delegitimize_address
#undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
#define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
arc_use_by_pieces_infrastructure_p
/* Usually, we will be able to scale anchor offsets.
When this fails, we want LEGITIMIZE_ADDRESS to kick in. */
#undef TARGET_MIN_ANCHOR_OFFSET
#define TARGET_MIN_ANCHOR_OFFSET (-1024)
#undef TARGET_MAX_ANCHOR_OFFSET
#define TARGET_MAX_ANCHOR_OFFSET (1020)
#undef TARGET_SECONDARY_RELOAD
#define TARGET_SECONDARY_RELOAD arc_secondary_reload
#define TARGET_OPTION_OVERRIDE arc_override_options
#define TARGET_CONDITIONAL_REGISTER_USAGE arc_conditional_register_usage
#define TARGET_TRAMPOLINE_INIT arc_initialize_trampoline
#define TARGET_CAN_ELIMINATE arc_can_eliminate
#define TARGET_FRAME_POINTER_REQUIRED arc_frame_pointer_required
#define TARGET_FUNCTION_ARG arc_function_arg
#define TARGET_FUNCTION_ARG_ADVANCE arc_function_arg_advance
#define TARGET_LEGITIMATE_CONSTANT_P arc_legitimate_constant_p
#define TARGET_LEGITIMATE_ADDRESS_P arc_legitimate_address_p
#define TARGET_MODE_DEPENDENT_ADDRESS_P arc_mode_dependent_address_p
#define TARGET_LEGITIMIZE_ADDRESS arc_legitimize_address
#undef TARGET_NO_SPECULATION_IN_DELAY_SLOTS_P
#define TARGET_NO_SPECULATION_IN_DELAY_SLOTS_P \
arc_no_speculation_in_delay_slots_p
#undef TARGET_LRA_P
#define TARGET_LRA_P arc_lra_p
#define TARGET_REGISTER_PRIORITY arc_register_priority
/* Stores with scaled offsets have different displacement ranges. */
#define TARGET_DIFFERENT_ADDR_DISPLACEMENT_P hook_bool_void_true
#define TARGET_SPILL_CLASS arc_spill_class
#undef TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS
#define TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS arc_allocate_stack_slots_for_args
#undef TARGET_WARN_FUNC_RETURN
#define TARGET_WARN_FUNC_RETURN arc_warn_func_return
#include "target-def.h"
#undef TARGET_ASM_ALIGNED_HI_OP
#define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
#undef TARGET_ASM_ALIGNED_SI_OP
#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
#ifdef HAVE_AS_TLS
#undef TARGET_HAVE_TLS
#define TARGET_HAVE_TLS HAVE_AS_TLS
#endif
#undef TARGET_DWARF_REGISTER_SPAN
#define TARGET_DWARF_REGISTER_SPAN arc_dwarf_register_span
#undef TARGET_HARD_REGNO_NREGS
#define TARGET_HARD_REGNO_NREGS arc_hard_regno_nregs
#undef TARGET_HARD_REGNO_MODE_OK
#define TARGET_HARD_REGNO_MODE_OK arc_hard_regno_mode_ok
#undef TARGET_MODES_TIEABLE_P
#define TARGET_MODES_TIEABLE_P arc_modes_tieable_p
/* Try to keep the (mov:DF _, reg) as early as possible so
that the d<add/sub/mul>h-lr insns appear together and can
use the peephole2 pattern. */
static int
arc_sched_adjust_priority (rtx_insn *insn, int priority)
{
rtx set = single_set (insn);
if (set
&& GET_MODE (SET_SRC(set)) == DFmode
&& GET_CODE (SET_SRC(set)) == REG)
{
/* Incrementing priority by 20 (empirically derived). */
return priority + 20;
}
return priority;
}
/* For ARC base register + offset addressing, the validity of the
address is mode-dependent for most of the offset range, as the
offset can be scaled by the access size.
We don't expose these as mode-dependent addresses in the
mode_dependent_address_p target hook, because that would disable
lots of optimizations, and most uses of these addresses are for 32
or 64 bit accesses anyways, which are fine.
However, that leaves some addresses for 8 / 16 bit values not
properly reloaded by the generic code, which is why we have to
schedule secondary reloads for these. */
static reg_class_t
arc_secondary_reload (bool in_p,
rtx x,
reg_class_t cl,
machine_mode mode,
secondary_reload_info *sri)
{
enum rtx_code code = GET_CODE (x);
if (cl == DOUBLE_REGS)
return GENERAL_REGS;
/* If we have a subreg (reg), where reg is a pseudo (that will end in
a memory location), then we may need a scratch register to handle
the fp/sp+largeoffset address. */
if (code == SUBREG)
{
rtx addr = NULL_RTX;
x = SUBREG_REG (x);
if (REG_P (x))
{
int regno = REGNO (x);
if (regno >= FIRST_PSEUDO_REGISTER)
regno = reg_renumber[regno];
if (regno != -1)
return NO_REGS;
/* It is a pseudo that ends in a stack location. This
procedure only works with the old reload step. */
if (!lra_in_progress && reg_equiv_mem (REGNO (x)))
{
/* Get the equivalent address and check the range of the
offset. */
rtx mem = reg_equiv_mem (REGNO (x));
addr = find_replacement (&XEXP (mem, 0));
}
}
else
{
gcc_assert (MEM_P (x));
addr = XEXP (x, 0);
addr = simplify_rtx (addr);
}
if (addr && GET_CODE (addr) == PLUS
&& CONST_INT_P (XEXP (addr, 1))
&& (!RTX_OK_FOR_OFFSET_P (mode, XEXP (addr, 1))))
{
switch (mode)
{
case E_QImode:
sri->icode =
in_p ? CODE_FOR_reload_qi_load : CODE_FOR_reload_qi_store;
break;
case E_HImode:
sri->icode =
in_p ? CODE_FOR_reload_hi_load : CODE_FOR_reload_hi_store;
break;
default:
break;
}
}
}
return NO_REGS;
}
/* Convert reloads using offsets that are too large to use indirect
addressing. */
void
arc_secondary_reload_conv (rtx reg, rtx mem, rtx scratch, bool store_p)
{
rtx addr;
gcc_assert (GET_CODE (mem) == MEM);
addr = XEXP (mem, 0);
/* Large offset: use a move. FIXME: ld ops accepts limms as
offsets. Hence, the following move insn is not required. */
emit_move_insn (scratch, addr);
mem = replace_equiv_address_nv (mem, scratch);
/* Now create the move. */
if (store_p)
emit_insn (gen_rtx_SET (mem, reg));
else
emit_insn (gen_rtx_SET (reg, mem));
return;
}
static unsigned arc_ifcvt (void);
namespace {
const pass_data pass_data_arc_ifcvt =
{
RTL_PASS,
"arc_ifcvt", /* name */
OPTGROUP_NONE, /* optinfo_flags */
TV_IFCVT2, /* tv_id */
0, /* properties_required */
0, /* properties_provided */
0, /* properties_destroyed */
0, /* todo_flags_start */
TODO_df_finish /* todo_flags_finish */
};
class pass_arc_ifcvt : public rtl_opt_pass
{
public:
pass_arc_ifcvt (gcc::context *ctxt)
: rtl_opt_pass (pass_data_arc_ifcvt, ctxt)
{}
/* opt_pass methods: */
opt_pass * clone ()
{
return new pass_arc_ifcvt (m_ctxt);
}
virtual unsigned int execute (function *)
{
return arc_ifcvt ();
}
virtual bool gate (function *)
{
return (optimize > 1 && !TARGET_NO_COND_EXEC);
}
};
} // anon namespace
rtl_opt_pass *
make_pass_arc_ifcvt (gcc::context *ctxt)
{
return new pass_arc_ifcvt (ctxt);
}
static unsigned arc_predicate_delay_insns (void);
namespace {
const pass_data pass_data_arc_predicate_delay_insns =
{
RTL_PASS,
"arc_predicate_delay_insns", /* name */
OPTGROUP_NONE, /* optinfo_flags */
TV_IFCVT2, /* tv_id */
0, /* properties_required */
0, /* properties_provided */
0, /* properties_destroyed */
0, /* todo_flags_start */
TODO_df_finish /* todo_flags_finish */
};
class pass_arc_predicate_delay_insns : public rtl_opt_pass
{
public:
pass_arc_predicate_delay_insns(gcc::context *ctxt)
: rtl_opt_pass(pass_data_arc_predicate_delay_insns, ctxt)
{}
/* opt_pass methods: */
virtual unsigned int execute (function *)
{
return arc_predicate_delay_insns ();
}
virtual bool gate (function *)
{
return flag_delayed_branch;
}
};
} // anon namespace
rtl_opt_pass *
make_pass_arc_predicate_delay_insns (gcc::context *ctxt)
{
return new pass_arc_predicate_delay_insns (ctxt);
}
/* Called by OVERRIDE_OPTIONS to initialize various things. */
static void
arc_init (void)
{
if (TARGET_V2)
{
/* I have the multiplier, then use it*/
if (TARGET_MPYW || TARGET_MULTI)
arc_multcost = COSTS_N_INSNS (1);
}
/* Note: arc_multcost is only used in rtx_cost if speed is true. */
if (arc_multcost < 0)
switch (arc_tune)
{
case ARC_TUNE_ARC700_4_2_STD:
/* latency 7;
max throughput (1 multiply + 4 other insns) / 5 cycles. */
arc_multcost = COSTS_N_INSNS (4);
if (TARGET_NOMPY_SET)
arc_multcost = COSTS_N_INSNS (30);
break;
case ARC_TUNE_ARC700_4_2_XMAC:
/* latency 5;
max throughput (1 multiply + 2 other insns) / 3 cycles. */
arc_multcost = COSTS_N_INSNS (3);
if (TARGET_NOMPY_SET)
arc_multcost = COSTS_N_INSNS (30);
break;
case ARC_TUNE_ARC600:
if (TARGET_MUL64_SET)
{
arc_multcost = COSTS_N_INSNS (4);
break;
}
/* Fall through. */
default:
arc_multcost = COSTS_N_INSNS (30);
break;
}
/* MPY instructions valid only for ARC700 or ARCv2. */
if (TARGET_NOMPY_SET && TARGET_ARC600_FAMILY)
error ("%<-mno-mpy%> supported only for ARC700 or ARCv2");
if (!TARGET_DPFP && TARGET_DPFP_DISABLE_LRSR)
error ("%<-mno-dpfp-lrsr%> supported only with %<-mdpfp%>");
/* FPX-1. No fast and compact together. */
if ((TARGET_DPFP_FAST_SET && TARGET_DPFP_COMPACT_SET)
|| (TARGET_SPFP_FAST_SET && TARGET_SPFP_COMPACT_SET))
error ("FPX fast and compact options cannot be specified together");
/* FPX-2. No fast-spfp for arc600 or arc601. */
if (TARGET_SPFP_FAST_SET && TARGET_ARC600_FAMILY)
error ("%<-mspfp_fast%> not available on ARC600 or ARC601");
/* FPX-4. No FPX extensions mixed with FPU extensions. */
if ((TARGET_DPFP_FAST_SET || TARGET_DPFP_COMPACT_SET || TARGET_SPFP)
&& TARGET_HARD_FLOAT)
error ("no FPX/FPU mixing allowed");
/* Warn for unimplemented PIC in pre-ARC700 cores, and disable flag_pic. */
if (flag_pic && TARGET_ARC600_FAMILY)
{
warning (0, "PIC is not supported for %qs",
arc_cpu_string);
flag_pic = 0;
}
arc_init_reg_tables ();
/* Initialize array for PRINT_OPERAND_PUNCT_VALID_P. */
memset (arc_punct_chars, 0, sizeof (arc_punct_chars));
arc_punct_chars['#'] = 1;
arc_punct_chars['*'] = 1;
arc_punct_chars['?'] = 1;
arc_punct_chars['!'] = 1;
arc_punct_chars['^'] = 1;
arc_punct_chars['&'] = 1;
arc_punct_chars['+'] = 1;
arc_punct_chars['_'] = 1;
}
/* Parse -mirq-ctrl-saved=RegisterRange, blink, lp_copunt. The
register range is specified as two registers separated by a dash.
It always starts with r0, and its upper limit is fp register.
blink and lp_count registers are optional. */
static void
irq_range (const char *cstr)
{
int i, first, last, blink, lpcount, xreg;
char *str, *dash, *comma;
i = strlen (cstr);
str = (char *) alloca (i + 1);
memcpy (str, cstr, i + 1);
blink = -1;
lpcount = -1;
dash = strchr (str, '-');
if (!dash)
{
warning (OPT_mirq_ctrl_saved_, "missing dash");
return;
}
*dash = '\0';
comma = strchr (dash + 1, ',');
if (comma)
*comma = '\0';
first = decode_reg_name (str);
if (first != 0)
{
warning (OPT_mirq_ctrl_saved_, "first register must be R0");
return;
}
/* At this moment we do not have the register names initialized
accordingly. */
if (!strcmp (dash + 1, "ilink"))
last = 29;
else
last = decode_reg_name (dash + 1);
if (last < 0)
{
warning (OPT_mirq_ctrl_saved_, "unknown register name: %s", dash + 1);
return;
}
if (!(last & 0x01))
{
warning (OPT_mirq_ctrl_saved_,
"last register name %s must be an odd register", dash + 1);
return;
}
*dash = '-';
if (first > last)
{
warning (OPT_mirq_ctrl_saved_,
"%s-%s is an empty range", str, dash + 1);
return;
}
while (comma)
{
*comma = ',';
str = comma + 1;
comma = strchr (str, ',');
if (comma)
*comma = '\0';
xreg = decode_reg_name (str);
switch (xreg)
{
case 31:
blink = 31;
break;
case 60:
lpcount = 60;
break;
default:
warning (OPT_mirq_ctrl_saved_,
"unknown register name: %s", str);
return;
}
}
irq_ctrl_saved.irq_save_last_reg = last;
irq_ctrl_saved.irq_save_blink = (blink == 31) || (last == 31);
irq_ctrl_saved.irq_save_lpcount = (lpcount == 60);
}
/* Parse -mrgf-banked-regs=NUM option string. Valid values for NUM are 4,
8, 16, or 32. */
static void
parse_mrgf_banked_regs_option (const char *arg)
{
long int val;
char *end_ptr;
errno = 0;
val = strtol (arg, &end_ptr, 10);
if (errno != 0 || *arg == '\0' || *end_ptr != '\0'
|| (val != 0 && val != 4 && val != 8 && val != 16 && val != 32))
{
error ("invalid number in %<-mrgf-banked-regs=%s%> "
"valid values are 0, 4, 8, 16, or 32", arg);
return;
}
rgf_banked_register_count = (int) val;
}
/* Check ARC options, generate derived target attributes. */
static void
arc_override_options (void)
{
unsigned int i;
cl_deferred_option *opt;
vec<cl_deferred_option> *vopt
= (vec<cl_deferred_option> *) arc_deferred_options;
if (arc_cpu == PROCESSOR_NONE)
arc_cpu = TARGET_CPU_DEFAULT;
/* Set the default cpu options. */
arc_selected_cpu = &arc_cpu_types[(int) arc_cpu];
/* Set the architectures. */
switch (arc_selected_cpu->arch_info->arch_id)
{
case BASE_ARCH_em:
arc_cpu_string = "EM";
break;
case BASE_ARCH_hs:
arc_cpu_string = "HS";
break;
case BASE_ARCH_700:
if (arc_selected_cpu->processor == PROCESSOR_nps400)
arc_cpu_string = "NPS400";
else
arc_cpu_string = "ARC700";
break;
case BASE_ARCH_6xx:
arc_cpu_string = "ARC600";
break;
default:
gcc_unreachable ();
}
irq_ctrl_saved.irq_save_last_reg = -1;
irq_ctrl_saved.irq_save_blink = false;
irq_ctrl_saved.irq_save_lpcount = false;
rgf_banked_register_count = 0;
/* Handle the deferred options. */
if (vopt)
FOR_EACH_VEC_ELT (*vopt, i, opt)
{
switch (opt->opt_index)
{
case OPT_mirq_ctrl_saved_:
if (TARGET_V2)
irq_range (opt->arg);
else
warning (OPT_mirq_ctrl_saved_,
"option %<-mirq-ctrl-saved%> valid only "
"for ARC v2 processors");
break;
case OPT_mrgf_banked_regs_:
if (TARGET_V2)
parse_mrgf_banked_regs_option (opt->arg);
else
warning (OPT_mrgf_banked_regs_,
"option %<-mrgf-banked-regs%> valid only for "
"ARC v2 processors");
break;
default:
gcc_unreachable();
}
}
CLEAR_HARD_REG_SET (overrideregs);
if (common_deferred_options)
{
vec<cl_deferred_option> v =
*((vec<cl_deferred_option> *) common_deferred_options);
int reg, nregs, j;
FOR_EACH_VEC_ELT (v, i, opt)
{
switch (opt->opt_index)
{
case OPT_ffixed_:
case OPT_fcall_used_:
case OPT_fcall_saved_:
if ((reg = decode_reg_name_and_count (opt->arg, &nregs)) >= 0)
for (j = reg; j < reg + nregs; j++)
SET_HARD_REG_BIT (overrideregs, j);
break;
default:
break;
}
}
}
/* Check options against architecture options. Throw an error if
option is not allowed. Extra, check options against default
architecture/cpu flags and throw an warning if we find a
mismatch. */
/* TRANSLATORS: the DOC/DOC0/DOC1 are strings which shouldn't be
translated. They are like keywords which one can relate with the
architectural choices taken for an ARC CPU implementation. */
#define ARC_OPTX(NAME, CODE, VAR, VAL, DOC0, DOC1) \
do { \
if ((!(arc_selected_cpu->arch_info->flags & CODE)) \
&& (VAR == VAL)) \
error ("option %<%s=%s%> is not available for %qs CPU", \
DOC0, DOC1, arc_selected_cpu->name); \
if ((arc_selected_cpu->arch_info->dflags & CODE) \
&& (VAR != DEFAULT_##VAR) \
&& (VAR != VAL)) \
warning (0, "option %qs is ignored, the default value %qs" \
" is considered for %qs CPU", DOC0, DOC1, \
arc_selected_cpu->name); \
} while (0);
#define ARC_OPT(NAME, CODE, MASK, DOC) \
do { \
if ((!(arc_selected_cpu->arch_info->flags & CODE)) \
&& (target_flags & MASK)) \
error ("option %qs is not available for %qs CPU", \
DOC, arc_selected_cpu->name); \
if ((arc_selected_cpu->arch_info->dflags & CODE) \
&& (target_flags_explicit & MASK) \
&& (!(target_flags & MASK))) \
warning (0, "unset option %qs is ignored, it is always" \
" enabled for %qs CPU", DOC, \
arc_selected_cpu->name); \
} while (0);
#include "arc-options.def"
#undef ARC_OPTX
#undef ARC_OPT
/* Set cpu flags accordingly to architecture/selected cpu. The cpu
specific flags are set in arc-common.c. The architecture forces
the default hardware configurations in, regardless what command
line options are saying. The CPU optional hw options can be
turned on or off. */
#define ARC_OPT(NAME, CODE, MASK, DOC) \
do { \
if ((arc_selected_cpu->flags & CODE) \
&& ((target_flags_explicit & MASK) == 0)) \
target_flags |= MASK; \
if (arc_selected_cpu->arch_info->dflags & CODE) \
target_flags |= MASK; \
} while (0);
#define ARC_OPTX(NAME, CODE, VAR, VAL, DOC0, DOC1) \
do { \
if ((arc_selected_cpu->flags & CODE) \
&& (VAR == DEFAULT_##VAR)) \
VAR = VAL; \
if (arc_selected_cpu->arch_info->dflags & CODE) \
VAR = VAL; \
} while (0);
#include "arc-options.def"
#undef ARC_OPTX
#undef ARC_OPT
/* Set extras. */
switch (arc_selected_cpu->extra)
{
case HAS_LPCOUNT_16:
arc_lpcwidth = 16;
break;
default:
break;
}
/* Set Tune option. */
if (arc_tune == ARC_TUNE_NONE)
arc_tune = (enum arc_tune_attr) arc_selected_cpu->tune;
if (arc_size_opt_level == 3)
optimize_size = 1;
if (TARGET_V2 && optimize_size && (ATTRIBUTE_PCS == 2))
TARGET_CODE_DENSITY_FRAME = 1;
if (flag_pic)
target_flags |= MASK_NO_SDATA_SET;
/* Check for small data option */
if (!OPTION_SET_P (g_switch_value) && !TARGET_NO_SDATA_SET)
g_switch_value = TARGET_LL64 ? 8 : 4;
/* A7 has an issue with delay slots. */
if (TARGET_ARC700 && (arc_tune != ARC_TUNE_ARC7XX))
flag_delayed_branch = 0;
/* Millicode thunks doesn't work for long calls. */
if (TARGET_LONG_CALLS_SET
/* neither for RF16. */
|| TARGET_RF16)
target_flags &= ~MASK_MILLICODE_THUNK_SET;
/* Set unaligned to all HS cpus. */
if (!OPTION_SET_P (unaligned_access) && TARGET_HS)
unaligned_access = 1;
/* These need to be done at start up. It's convenient to do them here. */
arc_init ();
}
/* The condition codes of the ARC, and the inverse function. */
/* For short branches, the "c" / "nc" names are not defined in the ARC
Programmers manual, so we have to use "lo" / "hs"" instead. */
static const char *arc_condition_codes[] =
{
"al", 0, "eq", "ne", "p", "n", "lo", "hs", "v", "nv",
"gt", "le", "ge", "lt", "hi", "ls", "pnz", 0
};
enum arc_cc_code_index
{
ARC_CC_AL, ARC_CC_EQ = ARC_CC_AL+2, ARC_CC_NE, ARC_CC_P, ARC_CC_N,
ARC_CC_C, ARC_CC_NC, ARC_CC_V, ARC_CC_NV,
ARC_CC_GT, ARC_CC_LE, ARC_CC_GE, ARC_CC_LT, ARC_CC_HI, ARC_CC_LS, ARC_CC_PNZ,
ARC_CC_LO = ARC_CC_C, ARC_CC_HS = ARC_CC_NC
};
#define ARC_INVERSE_CONDITION_CODE(X) ((X) ^ 1)
/* Returns the index of the ARC condition code string in
`arc_condition_codes'. COMPARISON should be an rtx like
`(eq (...) (...))'. */
static int
get_arc_condition_code (rtx comparison)
{
switch (GET_MODE (XEXP (comparison, 0)))
{
case E_CCmode:
case E_SImode: /* For BRcc. */
switch (GET_CODE (comparison))
{
case EQ : return ARC_CC_EQ;
case NE : return ARC_CC_NE;
case GT : return ARC_CC_GT;
case LE : return ARC_CC_LE;
case GE : return ARC_CC_GE;
case LT : return ARC_CC_LT;
case GTU : return ARC_CC_HI;
case LEU : return ARC_CC_LS;
case LTU : return ARC_CC_LO;
case GEU : return ARC_CC_HS;
default : gcc_unreachable ();
}
case E_CC_ZNmode:
switch (GET_CODE (comparison))
{
case EQ : return ARC_CC_EQ;
case NE : return ARC_CC_NE;
case GE: return ARC_CC_P;
case LT: return ARC_CC_N;
case GT : return ARC_CC_PNZ;
default : gcc_unreachable ();
}
case E_CC_Zmode:
switch (GET_CODE (comparison))
{
case EQ : return ARC_CC_EQ;
case NE : return ARC_CC_NE;
default : gcc_unreachable ();
}
case E_CC_Cmode:
switch (GET_CODE (comparison))
{
case LTU : return ARC_CC_C;
case GEU : return ARC_CC_NC;
default : gcc_unreachable ();
}
case E_CC_FP_GTmode:
if (TARGET_ARGONAUT_SET && TARGET_SPFP)
switch (GET_CODE (comparison))
{
case GT : return ARC_CC_N;
case UNLE: return ARC_CC_P;
default : gcc_unreachable ();
}
else
switch (GET_CODE (comparison))
{
case GT : return ARC_CC_HI;
case UNLE : return ARC_CC_LS;
default : gcc_unreachable ();
}
case E_CC_FP_GEmode:
/* Same for FPX and non-FPX. */
switch (GET_CODE (comparison))
{
case GE : return ARC_CC_HS;
case UNLT : return ARC_CC_LO;
default : gcc_unreachable ();
}
case E_CC_FP_UNEQmode:
switch (GET_CODE (comparison))
{
case UNEQ : return ARC_CC_EQ;
case LTGT : return ARC_CC_NE;
default : gcc_unreachable ();
}
case E_CC_FP_ORDmode:
switch (GET_CODE (comparison))
{
case UNORDERED : return ARC_CC_C;
case ORDERED : return ARC_CC_NC;
default : gcc_unreachable ();
}
case E_CC_FPXmode:
switch (GET_CODE (comparison))
{
case EQ : return ARC_CC_EQ;
case NE : return ARC_CC_NE;
case UNORDERED : return ARC_CC_C;
case ORDERED : return ARC_CC_NC;
case LTGT : return ARC_CC_HI;
case UNEQ : return ARC_CC_LS;
default : gcc_unreachable ();
}
case E_CC_FPUmode:
case E_CC_FPUEmode:
switch (GET_CODE (comparison))
{
case EQ : return ARC_CC_EQ;
case NE : return ARC_CC_NE;
case GT : return ARC_CC_GT;
case GE : return ARC_CC_GE;
case LT : return ARC_CC_C;
case LE : return ARC_CC_LS;
case UNORDERED : return ARC_CC_V;
case ORDERED : return ARC_CC_NV;
case UNGT : return ARC_CC_HI;
case UNGE : return ARC_CC_HS;
case UNLT : return ARC_CC_LT;
case UNLE : return ARC_CC_LE;
/* UNEQ and LTGT do not have representation. */
case LTGT : /* Fall through. */
case UNEQ : /* Fall through. */
default : gcc_unreachable ();
}
case E_CC_FPU_UNEQmode:
switch (GET_CODE (comparison))
{
case LTGT : return ARC_CC_NE;
case UNEQ : return ARC_CC_EQ;
default : gcc_unreachable ();
}
default : gcc_unreachable ();
}
/*NOTREACHED*/
return (42);
}
/* Return true if COMPARISON has a short form that can accomodate OFFSET. */
bool
arc_short_comparison_p (rtx comparison, int offset)
{
gcc_assert (ARC_CC_NC == ARC_CC_HS);
gcc_assert (ARC_CC_C == ARC_CC_LO);
switch (get_arc_condition_code (comparison))
{
case ARC_CC_EQ: case ARC_CC_NE:
return offset >= -512 && offset <= 506;
case ARC_CC_GT: case ARC_CC_LE: case ARC_CC_GE: case ARC_CC_LT:
case ARC_CC_HI: case ARC_CC_LS: case ARC_CC_LO: case ARC_CC_HS:
return offset >= -64 && offset <= 58;
default:
return false;
}
}
/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
return the mode to be used for the comparison. */
machine_mode
arc_select_cc_mode (enum rtx_code op, rtx x, rtx y)
{
machine_mode mode = GET_MODE (x);
rtx x1;
/* For an operation that sets the condition codes as a side-effect, the
C and V flags is not set as for cmp, so we can only use comparisons where
this doesn't matter. (For LT and GE we can use "mi" and "pl"
instead.) */
/* ??? We could use "pnz" for greater than zero, however, we could then
get into trouble because the comparison could not be reversed. */
if (GET_MODE_CLASS (mode) == MODE_INT
&& y == const0_rtx
&& (op == EQ || op == NE
|| ((op == LT || op == GE) && GET_MODE_SIZE (GET_MODE (x)) <= 4)))
return CC_ZNmode;
/* add.f for if (a+b) */
if (mode == SImode
&& GET_CODE (y) == NEG
&& (op == EQ || op == NE))
return CC_ZNmode;
/* Check if this is a test suitable for bxor.f . */
if (mode == SImode && (op == EQ || op == NE) && CONST_INT_P (y)
&& ((INTVAL (y) - 1) & INTVAL (y)) == 0
&& INTVAL (y))
return CC_Zmode;
/* Check if this is a test suitable for add / bmsk.f . */
if (mode == SImode && (op == EQ || op == NE) && CONST_INT_P (y)
&& GET_CODE (x) == AND && CONST_INT_P ((x1 = XEXP (x, 1)))
&& ((INTVAL (x1) + 1) & INTVAL (x1)) == 0
&& (~INTVAL (x1) | INTVAL (y)) < 0
&& (~INTVAL (x1) | INTVAL (y)) > -0x800)
return CC_Zmode;
if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
&& GET_CODE (x) == PLUS
&& (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
return CC_Cmode;
if (TARGET_ARGONAUT_SET
&& ((mode == SFmode && TARGET_SPFP) || (mode == DFmode && TARGET_DPFP)))
switch (op)
{
case EQ: case NE: case UNEQ: case LTGT: case ORDERED: case UNORDERED:
return CC_FPXmode;
case LT: case UNGE: case GT: case UNLE:
return CC_FP_GTmode;
case LE: case UNGT: case GE: case UNLT:
return CC_FP_GEmode;
default: gcc_unreachable ();
}
else if (TARGET_HARD_FLOAT
&& ((mode == SFmode && TARGET_FP_SP_BASE)
|| (mode == DFmode && TARGET_FP_DP_BASE)))
switch (op)
{
case EQ:
case NE:
case UNORDERED:
case ORDERED:
case UNLT:
case UNLE:
case UNGT:
case UNGE:
return CC_FPUmode;
case LT:
case LE:
case GT:
case GE:
return CC_FPUEmode;
case LTGT:
case UNEQ:
return CC_FPU_UNEQmode;
default:
gcc_unreachable ();
}
else if (GET_MODE_CLASS (mode) == MODE_FLOAT && TARGET_OPTFPE)
{
switch (op)
{
case EQ: case NE: return CC_Zmode;
case LT: case UNGE:
case GT: case UNLE: return CC_FP_GTmode;
case LE: case UNGT:
case GE: case UNLT: return CC_FP_GEmode;
case UNEQ: case LTGT: return CC_FP_UNEQmode;
case ORDERED: case UNORDERED: return CC_FP_ORDmode;
default: gcc_unreachable ();
}
}
return CCmode;
}
/* Vectors to keep interesting information about registers where it can easily
be got. We use to use the actual mode value as the bit number, but there
is (or may be) more than 32 modes now. Instead we use two tables: one
indexed by hard register number, and one indexed by mode. */
/* The purpose of arc_mode_class is to shrink the range of modes so that
they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
mapped into one arc_mode_class mode. */
enum arc_mode_class {
C_MODE,
S_MODE, D_MODE, T_MODE, O_MODE,
SF_MODE, DF_MODE, TF_MODE, OF_MODE,
V_MODE
};
/* Modes for condition codes. */
#define C_MODES (1 << (int) C_MODE)
/* Modes for single-word and smaller quantities. */
#define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
/* Modes for double-word and smaller quantities. */
#define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
/* Mode for 8-byte DF values only. */
#define DF_MODES (1 << DF_MODE)
/* Modes for quad-word and smaller quantities. */
#define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
/* Modes for 128-bit vectors. */
#define V_MODES (1 << (int) V_MODE)
/* Value is 1 if register/mode pair is acceptable on arc. */
static unsigned int arc_hard_regno_modes[] = {
T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES,
T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES,
T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, D_MODES,
D_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES,
/* ??? Leave these as S_MODES for now. */
S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES,
DF_MODES, 0, DF_MODES, 0, S_MODES, S_MODES, S_MODES, S_MODES,
S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES,
S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, C_MODES, S_MODES,
V_MODES, V_MODES, V_MODES, V_MODES, V_MODES, V_MODES, V_MODES, V_MODES,
V_MODES, V_MODES, V_MODES, V_MODES, V_MODES, V_MODES, V_MODES, V_MODES,
V_MODES, V_MODES, V_MODES, V_MODES, V_MODES, V_MODES, V_MODES, V_MODES,
V_MODES, V_MODES, V_MODES, V_MODES, V_MODES, V_MODES, V_MODES, V_MODES,
V_MODES, V_MODES, V_MODES, V_MODES, V_MODES, V_MODES, V_MODES, V_MODES,
V_MODES, V_MODES, V_MODES, V_MODES, V_MODES, V_MODES, V_MODES, V_MODES,
V_MODES, V_MODES, V_MODES, V_MODES, V_MODES, V_MODES, V_MODES, V_MODES,
V_MODES, V_MODES, V_MODES, V_MODES, V_MODES, V_MODES, V_MODES, V_MODES,
S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES,
S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES,
S_MODES, S_MODES
};
static unsigned int arc_mode_class [NUM_MACHINE_MODES];
enum reg_class arc_regno_reg_class[FIRST_PSEUDO_REGISTER];
enum reg_class
arc_preferred_reload_class (rtx, enum reg_class cl)
{
return cl;
}
/* Initialize the arc_mode_class array. */
static void
arc_init_reg_tables (void)
{
int i;
for (i = 0; i < NUM_MACHINE_MODES; i++)
{
machine_mode m = (machine_mode) i;
switch (GET_MODE_CLASS (m))
{
case MODE_INT:
case MODE_PARTIAL_INT:
case MODE_COMPLEX_INT:
if (GET_MODE_SIZE (m) <= 4)
arc_mode_class[i] = 1 << (int) S_MODE;
else if (GET_MODE_SIZE (m) == 8)
arc_mode_class[i] = 1 << (int) D_MODE;
else if (GET_MODE_SIZE (m) == 16)
arc_mode_class[i] = 1 << (int) T_MODE;
else if (GET_MODE_SIZE (m) == 32)
arc_mode_class[i] = 1 << (int) O_MODE;
else
arc_mode_class[i] = 0;
break;
case MODE_FLOAT:
case MODE_COMPLEX_FLOAT:
if (GET_MODE_SIZE (m) <= 4)
arc_mode_class[i] = 1 << (int) SF_MODE;
else if (GET_MODE_SIZE (m) == 8)
arc_mode_class[i] = 1 << (int) DF_MODE;
else if (GET_MODE_SIZE (m) == 16)
arc_mode_class[i] = 1 << (int) TF_MODE;
else if (GET_MODE_SIZE (m) == 32)
arc_mode_class[i] = 1 << (int) OF_MODE;
else
arc_mode_class[i] = 0;
break;
case MODE_VECTOR_INT:
if (GET_MODE_SIZE (m) == 4)
arc_mode_class[i] = (1 << (int) S_MODE);
else if (GET_MODE_SIZE (m) == 8)
arc_mode_class[i] = (1 << (int) D_MODE);
else
arc_mode_class[i] = (1 << (int) V_MODE);
break;
case MODE_CC:
default:
/* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
we must explicitly check for them here. */
if (i == (int) CCmode || i == (int) CC_ZNmode || i == (int) CC_Zmode
|| i == (int) CC_Cmode
|| i == CC_FP_GTmode || i == CC_FP_GEmode || i == CC_FP_ORDmode
|| i == CC_FPUmode || i == CC_FPUEmode || i == CC_FPU_UNEQmode)
arc_mode_class[i] = 1 << (int) C_MODE;
else
arc_mode_class[i] = 0;
break;
}
}
}
/* Core registers 56..59 are used for multiply extension options.
The dsp option uses r56 and r57, these are then named acc1 and acc2.
acc1 is the highpart, and acc2 the lowpart, so which register gets which
number depends on endianness.
The mul64 multiplier options use r57 for mlo, r58 for mmid and r59 for mhi.
Because mlo / mhi form a 64 bit value, we use different gcc internal
register numbers to make them form a register pair as the gcc internals
know it. mmid gets number 57, if still available, and mlo / mhi get
number 58 and 59, depending on endianness. We use DBX_REGISTER_NUMBER
to map this back. */
char rname56[5] = "r56";
char rname57[5] = "r57";
char rname58[5] = "r58";
char rname59[5] = "r59";
char rname29[7] = "ilink1";
char rname30[7] = "ilink2";
static void
arc_conditional_register_usage (void)
{
int regno;
int i;
int fix_start = 60, fix_end = 55;
if (TARGET_V2)
{
/* For ARCv2 the core register set is changed. */
strcpy (rname29, "ilink");
strcpy (rname30, "r30");
if (!TEST_HARD_REG_BIT (overrideregs, R30_REG))
{
/* No user interference. Set the r30 to be used by the
compiler. */
call_used_regs[R30_REG] = 1;
fixed_regs[R30_REG] = 0;
arc_regno_reg_class[R30_REG] = GENERAL_REGS;
}
}
if (TARGET_MUL64_SET)
{
fix_start = R57_REG;
fix_end = R59_REG;
/* We don't provide a name for mmed. In rtl / assembly resource lists,
you are supposed to refer to it as mlo & mhi, e.g
(zero_extract:SI (reg:DI 58) (const_int 32) (16)) .
In an actual asm instruction, you are of course use mmed.
The point of avoiding having a separate register for mmed is that
this way, we don't have to carry clobbers of that reg around in every
isntruction that modifies mlo and/or mhi. */
strcpy (rname57, "");
strcpy (rname58, "mlo");
strcpy (rname59, "mhi");
}
/* The nature of arc_tp_regno is actually something more like a global
register, however globalize_reg requires a declaration.
We use EPILOGUE_USES to compensate so that sets from
__builtin_set_frame_pointer are not deleted. */
if (arc_tp_regno != -1)
fixed_regs[arc_tp_regno] = call_used_regs[arc_tp_regno] = 1;
if (TARGET_MULMAC_32BY16_SET)
{
fix_start = MUL32x16_REG;
fix_end = fix_end > R57_REG ? fix_end : R57_REG;
strcpy (rname56, TARGET_BIG_ENDIAN ? "acc1" : "acc2");
strcpy (rname57, TARGET_BIG_ENDIAN ? "acc2" : "acc1");
}
for (regno = fix_start; regno <= fix_end; regno++)
{
if (!fixed_regs[regno])
warning (0, "multiply option implies r%d is fixed", regno);
fixed_regs [regno] = call_used_regs[regno] = 1;
}
/* Reduced configuration: don't use r4-r9, r16-r25. */
if (TARGET_RF16)
{
for (i = R4_REG; i <= R9_REG; i++)
fixed_regs[i] = call_used_regs[i] = 1;
for (i = R16_REG; i <= R25_REG; i++)
fixed_regs[i] = call_used_regs[i] = 1;
}
/* ARCHS has 64-bit data-path which makes use of the even-odd paired
registers. */
if (TARGET_HS)
for (regno = R1_REG; regno < R32_REG; regno +=2)
arc_hard_regno_modes[regno] = S_MODES;
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
if (i < ILINK1_REG)
{
if ((i <= R3_REG) || ((i >= R12_REG) && (i <= R15_REG)))
arc_regno_reg_class[i] = ARCOMPACT16_REGS;
else
arc_regno_reg_class[i] = GENERAL_REGS;
}
else if (i < LP_COUNT)
arc_regno_reg_class[i] = GENERAL_REGS;
else
arc_regno_reg_class[i] = NO_REGS;
/* Handle Special Registers. */
arc_regno_reg_class[CC_REG] = NO_REGS; /* CC_REG: must be NO_REGS. */
arc_regno_reg_class[FRAME_POINTER_REGNUM] = GENERAL_REGS;
arc_regno_reg_class[ARG_POINTER_REGNUM] = GENERAL_REGS;
if (TARGET_DPFP)
for (i = R40_REG; i < R44_REG; ++i)
{
arc_regno_reg_class[i] = DOUBLE_REGS;
if (!TARGET_ARGONAUT_SET)
CLEAR_HARD_REG_BIT (reg_class_contents[GENERAL_REGS], i);
}
else
{
/* Disable all DOUBLE_REGISTER settings, if not generating DPFP
code. */
arc_regno_reg_class[R40_REG] = ALL_REGS;
arc_regno_reg_class[R41_REG] = ALL_REGS;
arc_regno_reg_class[R42_REG] = ALL_REGS;
arc_regno_reg_class[R43_REG] = ALL_REGS;
fixed_regs[R40_REG] = 1;
fixed_regs[R41_REG] = 1;
fixed_regs[R42_REG] = 1;
fixed_regs[R43_REG] = 1;
arc_hard_regno_modes[R40_REG] = 0;
arc_hard_regno_modes[R42_REG] = 0;
}
if (TARGET_SIMD_SET)
{
gcc_assert (ARC_FIRST_SIMD_VR_REG == 64);
gcc_assert (ARC_LAST_SIMD_VR_REG == 127);
for (i = ARC_FIRST_SIMD_VR_REG; i <= ARC_LAST_SIMD_VR_REG; i++)
arc_regno_reg_class [i] = SIMD_VR_REGS;
gcc_assert (ARC_FIRST_SIMD_DMA_CONFIG_REG == 128);
gcc_assert (ARC_FIRST_SIMD_DMA_CONFIG_IN_REG == 128);
gcc_assert (ARC_FIRST_SIMD_DMA_CONFIG_OUT_REG == 136);
gcc_assert (ARC_LAST_SIMD_DMA_CONFIG_REG == 143);
for (i = ARC_FIRST_SIMD_DMA_CONFIG_REG;
i <= ARC_LAST_SIMD_DMA_CONFIG_REG; i++)
arc_regno_reg_class [i] = SIMD_DMA_CONFIG_REGS;
}
/* pc : r63 */
arc_regno_reg_class[PCL_REG] = NO_REGS;
/*ARCV2 Accumulator. */
if ((TARGET_V2
&& (TARGET_FP_DP_FUSED || TARGET_FP_SP_FUSED))
|| TARGET_PLUS_DMPY)
{
arc_regno_reg_class[ACCL_REGNO] = GENERAL_REGS;
arc_regno_reg_class[ACCH_REGNO] = GENERAL_REGS;
/* Allow the compiler to freely use them. */
if (!TEST_HARD_REG_BIT (overrideregs, ACCL_REGNO))
fixed_regs[ACCL_REGNO] = 0;
if (!TEST_HARD_REG_BIT (overrideregs, ACCH_REGNO))
fixed_regs[ACCH_REGNO] = 0;
if (!fixed_regs[ACCH_REGNO] && !fixed_regs[ACCL_REGNO])
arc_hard_regno_modes[ACC_REG_FIRST] = D_MODES;
}
}
/* Implement TARGET_HARD_REGNO_NREGS. */
static unsigned int
arc_hard_regno_nregs (unsigned int regno, machine_mode mode)
{
if (GET_MODE_SIZE (mode) == 16
&& regno >= ARC_FIRST_SIMD_VR_REG
&& regno <= ARC_LAST_SIMD_VR_REG)
return 1;
return CEIL (GET_MODE_SIZE (mode), UNITS_PER_WORD);
}
/* Implement TARGET_HARD_REGNO_MODE_OK. */
static bool
arc_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
return (arc_hard_regno_modes[regno] & arc_mode_class[mode]) != 0;
}
/* Implement TARGET_MODES_TIEABLE_P. Tie QI/HI/SI modes together. */
static bool
arc_modes_tieable_p (machine_mode mode1, machine_mode mode2)
{
return (GET_MODE_CLASS (mode1) == MODE_INT
&& GET_MODE_CLASS (mode2) == MODE_INT
&& GET_MODE_SIZE (mode1) <= UNITS_PER_WORD
&& GET_MODE_SIZE (mode2) <= UNITS_PER_WORD);
}
/* Handle an "interrupt" attribute; arguments as in
struct attribute_spec.handler. */
static tree
arc_handle_interrupt_attribute (tree *, tree name, tree args, int,
bool *no_add_attrs)
{
gcc_assert (args);
tree value = TREE_VALUE (args);
if (TREE_CODE (value) != STRING_CST)
{
warning (OPT_Wattributes,
"argument of %qE attribute is not a string constant",
name);
*no_add_attrs = true;
}
else if (!TARGET_V2
&& strcmp (TREE_STRING_POINTER (value), "ilink1")
&& strcmp (TREE_STRING_POINTER (value), "ilink2"))
{
warning (OPT_Wattributes,
"argument of %qE attribute is not \"ilink1\" or \"ilink2\"",
name);
*no_add_attrs = true;
}
else if (TARGET_V2
&& strcmp (TREE_STRING_POINTER (value), "ilink")
&& strcmp (TREE_STRING_POINTER (value), "firq"))
{
warning (OPT_Wattributes,
"argument of %qE attribute is not \"ilink\" or \"firq\"",
name);
*no_add_attrs = true;
}
return NULL_TREE;
}
static tree
arc_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED,
int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
{
if (TREE_CODE (*node) != FUNCTION_DECL)
{
warning (OPT_Wattributes, "%qE attribute only applies to functions",
name);
*no_add_attrs = true;
}
return NULL_TREE;
}
/* Type of function DECL.
The result is cached. To reset the cache at the end of a function,
call with DECL = NULL_TREE. */
static unsigned int
arc_compute_function_type (struct function *fun)
{
tree attr, decl = fun->decl;
unsigned int fn_type = fun->machine->fn_type;
if (fn_type != ARC_FUNCTION_UNKNOWN)
return fn_type;
/* Check if it is a naked function. */
if (lookup_attribute ("naked", DECL_ATTRIBUTES (decl)) != NULL_TREE)
fn_type |= ARC_FUNCTION_NAKED;
else
fn_type |= ARC_FUNCTION_NORMAL;
/* Now see if this is an interrupt handler. */
attr = lookup_attribute ("interrupt", DECL_ATTRIBUTES (decl));
if (attr != NULL_TREE)
{
tree value, args = TREE_VALUE (attr);
gcc_assert (list_length (args) == 1);
value = TREE_VALUE (args);
gcc_assert (TREE_CODE (value) == STRING_CST);
if (!strcmp (TREE_STRING_POINTER (value), "ilink1")
|| !strcmp (TREE_STRING_POINTER (value), "ilink"))
fn_type |= ARC_FUNCTION_ILINK1;
else if (!strcmp (TREE_STRING_POINTER (value), "ilink2"))
fn_type |= ARC_FUNCTION_ILINK2;
else if (!strcmp (TREE_STRING_POINTER (value), "firq"))
fn_type |= ARC_FUNCTION_FIRQ;
else
gcc_unreachable ();
}
return fun->machine->fn_type = fn_type;
}
/* Implement `TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS' */
static bool
arc_allocate_stack_slots_for_args (void)
{
/* Naked functions should not allocate stack slots for arguments. */
unsigned int fn_type = arc_compute_function_type (cfun);
return !ARC_NAKED_P(fn_type);
}
/* Implement `TARGET_WARN_FUNC_RETURN'. */
static bool
arc_warn_func_return (tree decl)
{
struct function *func = DECL_STRUCT_FUNCTION (decl);
unsigned int fn_type = arc_compute_function_type (func);
return !ARC_NAKED_P (fn_type);
}
/* Return zero if TYPE1 and TYPE are incompatible, one if they are compatible,
and two if they are nearly compatible (which causes a warning to be
generated). */
static int
arc_comp_type_attributes (const_tree type1,
const_tree type2)
{
int l1, l2, m1, m2, s1, s2;
/* Check for mismatch of non-default calling convention. */
if (TREE_CODE (type1) != FUNCTION_TYPE)
return 1;
/* Check for mismatched call attributes. */
l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
m1 = lookup_attribute ("medium_call", TYPE_ATTRIBUTES (type1)) != NULL;
m2 = lookup_attribute ("medium_call", TYPE_ATTRIBUTES (type2)) != NULL;
s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
/* Only bother to check if an attribute is defined. */
if (l1 | l2 | m1 | m2 | s1 | s2)
{
/* If one type has an attribute, the other must have the same attribute. */
if ((l1 != l2) || (m1 != m2) || (s1 != s2))
return 0;
/* Disallow mixed attributes. */
if (l1 + m1 + s1 > 1)
return 0;
}
return 1;
}
/* Misc. utilities. */
/* X and Y are two things to compare using CODE. Emit the compare insn and
return the rtx for the cc reg in the proper mode. */
rtx
gen_compare_reg (rtx comparison, machine_mode omode)
{
enum rtx_code code = GET_CODE (comparison);
rtx x = XEXP (comparison, 0);
rtx y = XEXP (comparison, 1);
rtx tmp, cc_reg;
machine_mode mode, cmode;
cmode = GET_MODE (x);
if (cmode == VOIDmode)
cmode = GET_MODE (y);
gcc_assert (cmode == SImode || cmode == SFmode || cmode == DFmode);
if (cmode == SImode)
{
if (!register_operand (x, SImode))
{
if (register_operand (y, SImode))
{
tmp = x;
x = y;
y = tmp;
code = swap_condition (code);
}
else
x = copy_to_mode_reg (SImode, x);
}
if (GET_CODE (y) == SYMBOL_REF && flag_pic)
y = copy_to_mode_reg (SImode, y);
}
else
{
x = force_reg (cmode, x);
y = force_reg (cmode, y);
}
mode = SELECT_CC_MODE (code, x, y);
cc_reg = gen_rtx_REG (mode, CC_REG);
/* ??? FIXME (x-y)==0, as done by both cmpsfpx_raw and
cmpdfpx_raw, is not a correct comparison for floats:
http://www.cygnus-software.com/papers/comparingfloats/comparingfloats.htm
*/
if (TARGET_ARGONAUT_SET
&& ((cmode == SFmode && TARGET_SPFP) || (cmode == DFmode && TARGET_DPFP)))
{
switch (code)
{
case NE: case EQ: case LT: case UNGE: case LE: case UNGT:
case UNEQ: case LTGT: case ORDERED: case UNORDERED:
break;
case GT: case UNLE: case GE: case UNLT:
code = swap_condition (code);
tmp = x;
x = y;
y = tmp;
break;
default:
gcc_unreachable ();
}
if (cmode == SFmode)
{
emit_insn (gen_cmpsfpx_raw (x, y));
}
else /* DFmode */
{
/* Accepts Dx regs directly by insns. */
emit_insn (gen_cmpdfpx_raw (x, y));
}
if (mode != CC_FPXmode)
emit_insn (gen_rtx_SET (cc_reg,
gen_rtx_COMPARE (mode,
gen_rtx_REG (CC_FPXmode, 61),
const0_rtx)));
}
else if (TARGET_FPX_QUARK && (cmode == SFmode))
{
switch (code)
{
case NE: case EQ: case GT: case UNLE: case GE: case UNLT:
case UNEQ: case LTGT: case ORDERED: case UNORDERED:
break;
case LT: case UNGE: case LE: case UNGT:
code = swap_condition (code);
tmp = x;
x = y;
y = tmp;
break;
default:
gcc_unreachable ();
}
emit_insn (gen_cmp_quark (cc_reg,
gen_rtx_COMPARE (mode, x, y)));
}
else if (TARGET_HARD_FLOAT
&& ((cmode == SFmode && TARGET_FP_SP_BASE)
|| (cmode == DFmode && TARGET_FP_DP_BASE)))
emit_insn (gen_rtx_SET (cc_reg, gen_rtx_COMPARE (mode, x, y)));
else if (GET_MODE_CLASS (cmode) == MODE_FLOAT && TARGET_OPTFPE)
{
rtx op0 = gen_rtx_REG (cmode, 0);
rtx op1 = gen_rtx_REG (cmode, GET_MODE_SIZE (cmode) / UNITS_PER_WORD);
bool swap = false;
switch (code)
{
case NE: case EQ: case GT: case UNLE: case GE: case UNLT:
case UNEQ: case LTGT: case ORDERED: case UNORDERED:
break;
case LT: case UNGE: case LE: case UNGT:
code = swap_condition (code);
swap = true;
break;
default:
gcc_unreachable ();
}
if (currently_expanding_to_rtl)
{
if (swap)
{
tmp = x;
x = y;
y = tmp;
}
emit_move_insn (op0, x);
emit_move_insn (op1, y);
}
else
{
gcc_assert (rtx_equal_p (op0, x));
gcc_assert (rtx_equal_p (op1, y));
if (swap)
{
op0 = y;
op1 = x;
}
}
emit_insn (gen_cmp_float (cc_reg, gen_rtx_COMPARE (mode, op0, op1)));
}
else
emit_insn (gen_rtx_SET (cc_reg, gen_rtx_COMPARE (mode, x, y)));
return gen_rtx_fmt_ee (code, omode, cc_reg, const0_rtx);
}
/* Return true if VALUE, a const_double, will fit in a limm (4 byte number).
We assume the value can be either signed or unsigned. */
bool
arc_double_limm_p (rtx value)
{
HOST_WIDE_INT low, high;
gcc_assert (GET_CODE (value) == CONST_DOUBLE);
if (TARGET_DPFP)
return true;
low = CONST_DOUBLE_LOW (value);
high = CONST_DOUBLE_HIGH (value);
if (low & 0x80000000)
{
return (((unsigned HOST_WIDE_INT) low <= 0xffffffff && high == 0)
|| (((low & - (unsigned HOST_WIDE_INT) 0x80000000)
== - (unsigned HOST_WIDE_INT) 0x80000000)
&& high == -1));
}
else
{
return (unsigned HOST_WIDE_INT) low <= 0x7fffffff && high == 0;
}
}
/* Do any needed setup for a variadic function. For the ARC, we must
create a register parameter block, and then copy any anonymous arguments
in registers to memory.
CUM has not been updated for the last named argument (which is given
by ARG), and we rely on this fact. */
static void
arc_setup_incoming_varargs (cumulative_args_t args_so_far,
const function_arg_info &arg,
int *pretend_size, int no_rtl)
{
int first_anon_arg;
CUMULATIVE_ARGS next_cum;
/* We must treat `__builtin_va_alist' as an anonymous arg. */
next_cum = *get_cumulative_args (args_so_far);
arc_function_arg_advance (pack_cumulative_args (&next_cum), arg);
first_anon_arg = next_cum;
if (FUNCTION_ARG_REGNO_P (first_anon_arg))
{
/* First anonymous (unnamed) argument is in a reg. */
/* Note that first_reg_offset < MAX_ARC_PARM_REGS. */
int first_reg_offset = first_anon_arg;
if (!no_rtl)
{
rtx regblock
= gen_rtx_MEM (BLKmode, plus_constant (Pmode, arg_pointer_rtx,
FIRST_PARM_OFFSET (0)));
move_block_from_reg (first_reg_offset, regblock,
MAX_ARC_PARM_REGS - first_reg_offset);
}
*pretend_size
= ((MAX_ARC_PARM_REGS - first_reg_offset ) * UNITS_PER_WORD);
}
}
/* Cost functions. */
/* Provide the costs of an addressing mode that contains ADDR.
If ADDR is not a valid address, its cost is irrelevant. */
static int
arc_address_cost (rtx addr, machine_mode, addr_space_t, bool speed)
{
switch (GET_CODE (addr))
{
case REG :
return speed || satisfies_constraint_Rcq (addr) ? 0 : 1;
case PRE_INC: case PRE_DEC: case POST_INC: case POST_DEC:
case PRE_MODIFY: case POST_MODIFY:
return !speed;
case LABEL_REF :
case SYMBOL_REF :
case CONST :
if (TARGET_NPS_CMEM && cmem_address (addr, SImode))
return 0;
/* Most likely needs a LIMM. */
return COSTS_N_INSNS (1);
case PLUS :
{
rtx plus0 = XEXP (addr, 0);
rtx plus1 = XEXP (addr, 1);
if (GET_CODE (plus0) != REG
&& (GET_CODE (plus0) != MULT
|| !CONST_INT_P (XEXP (plus0, 1))
|| (INTVAL (XEXP (plus0, 1)) != 2
&& INTVAL (XEXP (plus0, 1)) != 4)))
break;
switch (GET_CODE (plus1))
{
case CONST_INT :
return (!RTX_OK_FOR_OFFSET_P (SImode, plus1)
? COSTS_N_INSNS (1)
: speed
? 0
: (satisfies_constraint_Rcq (plus0)
&& satisfies_constraint_O (plus1))
? 0
: 1);
case REG:
return (speed < 1 ? 0
: (satisfies_constraint_Rcq (plus0)
&& satisfies_constraint_Rcq (plus1))
? 0 : 1);
case CONST :
case SYMBOL_REF :
case LABEL_REF :
return COSTS_N_INSNS (1);
default:
break;
}
break;
}
default:
break;
}
return 4;
}
/* Emit instruction X with the frame related bit set. */
static rtx
frame_insn (rtx x)
{
x = emit_insn (x);
RTX_FRAME_RELATED_P (x) = 1;
return x;
}
/* Emit a frame insn to move SRC to DST. */
static rtx
frame_move (rtx dst, rtx src)
{
rtx tmp = gen_rtx_SET (dst, src);
RTX_FRAME_RELATED_P (tmp) = 1;
return frame_insn (tmp);
}
/* Like frame_move, but add a REG_INC note for REG if ADDR contains an
auto increment address, or is zero. */
static rtx
frame_move_inc (rtx dst, rtx src, rtx reg, rtx addr)
{
rtx insn = frame_move (dst, src);
if (!addr
|| GET_CODE (addr) == PRE_DEC || GET_CODE (addr) == POST_INC
|| GET_CODE (addr) == PRE_MODIFY || GET_CODE (addr) == POST_MODIFY)
add_reg_note (insn, REG_INC, reg);
return insn;
}
/* Emit a frame insn which adjusts a frame address register REG by OFFSET. */
static rtx
frame_add (rtx reg, HOST_WIDE_INT offset)
{
gcc_assert ((offset & 0x3) == 0);
if (!offset)
return NULL_RTX;
return frame_move (reg, plus_constant (Pmode, reg, offset));
}
/* Emit a frame insn which adjusts stack pointer by OFFSET. */
static rtx
frame_stack_add (HOST_WIDE_INT offset)
{
return frame_add (stack_pointer_rtx, offset);
}
/* Helper function to wrap FRAME_POINTER_NEEDED. We do this as
FRAME_POINTER_NEEDED will not be true until the IRA (Integrated
Register Allocator) pass, while we want to get the frame size
correct earlier than the IRA pass.
When a function uses eh_return we must ensure that the fp register
is saved and then restored so that the unwinder can restore the
correct value for the frame we are going to jump to.
To do this we force all frames that call eh_return to require a
frame pointer (see arc_frame_pointer_required), this
will ensure that the previous frame pointer is stored on entry to
the function, and will then be reloaded at function exit.
As the frame pointer is handled as a special case in our prologue
and epilogue code it must not be saved and restored using the
MUST_SAVE_REGISTER mechanism otherwise we run into issues where GCC
believes that the function is not using a frame pointer and that
the value in the fp register is the frame pointer, while the
prologue and epilogue are busy saving and restoring the fp
register.
During compilation of a function the frame size is evaluated
multiple times, it is not until the reload pass is complete the
frame size is considered fixed (it is at this point that space for
all spills has been allocated). However the frame_pointer_needed
variable is not set true until the register allocation pass, as a
result in the early stages the frame size does not include space
for the frame pointer to be spilled.
The problem that this causes is that the rtl generated for
EH_RETURN_HANDLER_RTX uses the details of the frame size to compute
the offset from the frame pointer at which the return address
lives. However, in early passes GCC has not yet realised we need a
frame pointer, and so has not included space for the frame pointer
in the frame size, and so gets the offset of the return address
wrong. This should not be an issue as in later passes GCC has
realised that the frame pointer needs to be spilled, and has
increased the frame size. However, the rtl for the
EH_RETURN_HANDLER_RTX is not regenerated to use the newer, larger
offset, and the wrong smaller offset is used. */
static bool
arc_frame_pointer_needed (void)
{
return (frame_pointer_needed || crtl->calls_eh_return);
}
/* Tell prologue and epilogue if register REGNO should be saved /
restored. The SPECIAL_P is true when the register may need special
ld/st sequence. The return address, and stack pointer are treated
separately. Don't consider them here. */
static bool
arc_must_save_register (int regno, struct function *func, bool special_p)
{
unsigned int fn_type = arc_compute_function_type (func);
bool irq_auto_save_p = ((irq_ctrl_saved.irq_save_last_reg >= regno)
&& ARC_AUTO_IRQ_P (fn_type));
bool firq_auto_save_p = ARC_FAST_INTERRUPT_P (fn_type);
switch (rgf_banked_register_count)
{
case 4:
firq_auto_save_p &= (regno < 4);
break;
case 8:
firq_auto_save_p &= ((regno < 4) || ((regno > 11) && (regno < 16)));
break;
case 16:
firq_auto_save_p &= ((regno < 4) || ((regno > 9) && (regno < 16))
|| ((regno > 25) && (regno < 29))
|| ((regno > 29) && (regno < 32)));
break;
case 32:
firq_auto_save_p &= (regno != 29) && (regno < 32);
break;
default:
firq_auto_save_p = false;
break;
}
switch (regno)
{
case ILINK1_REG:
case RETURN_ADDR_REGNUM:
case STACK_POINTER_REGNUM:
/* The stack pointer and the return address are handled
separately. */
return false;
case R30_REG:
/* r30 is either used as ilink2 by ARCv1 or as a free register
by ARCv2. */
if (!TARGET_V2)
return false;
break;
case R40_REG:
case R41_REG:
case R42_REG:
case R43_REG:
case R44_REG:
/* If those ones are used by the FPX machinery, we handle them
separately. */
if (TARGET_DPFP && !special_p)
return false;
/* FALLTHRU. */
case R32_REG:
case R33_REG:
case R34_REG:
case R35_REG:
case R36_REG:
case R37_REG:
case R38_REG:
case R39_REG:
case R45_REG:
case R46_REG:
case R47_REG:
case R48_REG:
case R49_REG:
case R50_REG:
case R51_REG:
case R52_REG:
case R53_REG:
case R54_REG:
case R55_REG:
case R56_REG:
case R57_REG:
/* The Extension Registers. */
if (ARC_INTERRUPT_P (fn_type)
&& (df_regs_ever_live_p (RETURN_ADDR_REGNUM)
|| df_regs_ever_live_p (regno))
/* Not all extension registers are available, choose the
real ones. */
&& !fixed_regs[regno])
return true;
return false;
case R58_REG:
case R59_REG:
/* ARC600 specifies those ones as mlo/mhi registers, otherwise
just handle them like any other extension register. */
if (ARC_INTERRUPT_P (fn_type)
&& (df_regs_ever_live_p (RETURN_ADDR_REGNUM)
|| df_regs_ever_live_p (regno))
/* Not all extension registers are available, choose the
real ones. */
&& ((!fixed_regs[regno] && !special_p)
|| (TARGET_MUL64_SET && special_p)))
return true;
return false;
case 61:
case 62:
case 63:
/* Fixed/control register, nothing to do. LP_COUNT is
different. */
return false;
case HARD_FRAME_POINTER_REGNUM:
/* If we need FP reg as a frame pointer then don't save it as a
regular reg. */
if (arc_frame_pointer_needed ())
return false;
break;
default:
break;
}
if (((df_regs_ever_live_p (regno) && !call_used_or_fixed_reg_p (regno))
/* In an interrupt save everything. */
|| (ARC_INTERRUPT_P (fn_type)
&& (df_regs_ever_live_p (RETURN_ADDR_REGNUM)
|| df_regs_ever_live_p (regno))))
/* Do not emit code for auto saved regs. */
&& !irq_auto_save_p
&& !firq_auto_save_p)
return true;
return false;
}
/* Return true if the return address must be saved in the current function,
otherwise return false. */
static bool
arc_must_save_return_addr (struct function *func)
{
if (func->machine->frame_info.save_return_addr)
return true;
return false;
}
/* Return non-zero if there are registers to be saved or loaded using
millicode thunks. We can only use consecutive sequences starting
with r13, and not going beyond r25.
GMASK is a bitmask of registers to save. This function sets
FRAME->millicod_start_reg .. FRAME->millicode_end_reg to the range
of registers to be saved / restored with a millicode call. */
static int
arc_compute_millicode_save_restore_regs (uint64_t gmask,
struct arc_frame_info *frame)
{
int regno;
int start_reg = 13, end_reg = 25;
for (regno = start_reg; regno <= end_reg && (gmask & (1ULL << regno));)
regno++;
end_reg = regno - 1;
/* There is no point in using millicode thunks if we don't save/restore
at least three registers. For non-leaf functions we also have the
blink restore. */
if (regno - start_reg >= 3 - (crtl->is_leaf == 0))
{
frame->millicode_start_reg = 13;
frame->millicode_end_reg = regno - 1;
return 1;
}
return 0;
}
/* Return the bytes needed to compute the frame pointer from the
current stack pointer. */
static unsigned int
arc_compute_frame_size (void)
{
int regno;
unsigned int total_size, var_size, args_size, pretend_size, extra_size;
unsigned int reg_size;
uint64_t gmask;
struct arc_frame_info *frame_info;
int size;
unsigned int extra_plus_reg_size;
unsigned int extra_plus_reg_size_aligned;
unsigned int fn_type = arc_compute_function_type (cfun);
/* The answer might already be known. */
if (cfun->machine->frame_info.initialized)
return cfun->machine->frame_info.total_size;
frame_info = &cfun->machine->frame_info;
size = ARC_STACK_ALIGN (get_frame_size ());