RISC-V: Allow RVV register overlap for vwmulsu.vx

Like vw{add,sub,mul}[u].vx, allow the rvv register overlap for
the dual widen vx insn vwmulsu.vx.

gcc/ChangeLog:

	* config/riscv/vector.md: Leverage Wvr constraint.

Signed-off-by: Pan Li <pan2.li@intel.com>