Google Git
Sign in
gnu / gcc / refs/heads/devel/gccgo / . / gcc / ChangeLog
blob: a7d51b5038aaaf598e35b6c07bc1e5cb865928e7 [file] [log] [blame]
2023-06-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vsetvl.cc (vector_insn_info::parse_insn): Ehance
AVL propagation.
* config/riscv/riscv-vsetvl.h: New function.
2023-06-25 Li Xu <xuli1@eswincomputing.com>
* config/riscv/riscv-vector-builtins-bases.cc: change emit_insn to
emit_move_insn
2023-06-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/autovec.md (len_load_<mode>): Remove.
(len_maskload<mode><vm>): Remove.
(len_store_<mode>): New pattern.
(len_maskstore<mode><vm>): New pattern.
* config/riscv/predicates.md (autovec_length_operand): New predicate.
* config/riscv/riscv-protos.h (enum insn_type): New enum.
(expand_load_store): New function.
* config/riscv/riscv-v.cc (emit_vlmax_masked_insn): Ditto.
(emit_nonvlmax_masked_insn): Ditto.
(expand_load_store): Ditto.
* config/riscv/riscv-vector-builtins.cc
(function_expander::use_contiguous_store_insn): Add avl_type operand
into pred_store.
* config/riscv/vector.md: Ditto.
2023-06-25 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* internal-fn.cc (expand_partial_store_optab_fn): Fix bug of BIAS
argument index.
2023-06-25 Pan Li <pan2.li@intel.com>
* config/riscv/vector.md: Revert.
2023-06-25 Pan Li <pan2.li@intel.com>
* config/riscv/genrvv-type-indexer.cc (valid_type): Revert changes.
* config/riscv/riscv-modes.def (RVV_TUPLE_MODES): Ditto.
(ADJUST_ALIGNMENT): Ditto.
(RVV_TUPLE_PARTIAL_MODES): Ditto.
(ADJUST_NUNITS): Ditto.
* config/riscv/riscv-vector-builtins-types.def (vfloat16mf4x2_t): Ditto.
(vfloat16mf4x3_t): Ditto.
(vfloat16mf4x4_t): Ditto.
(vfloat16mf4x5_t): Ditto.
(vfloat16mf4x6_t): Ditto.
(vfloat16mf4x7_t): Ditto.
(vfloat16mf4x8_t): Ditto.
(vfloat16mf2x2_t): Ditto.
(vfloat16mf2x3_t): Ditto.
(vfloat16mf2x4_t): Ditto.
(vfloat16mf2x5_t): Ditto.
(vfloat16mf2x6_t): Ditto.
(vfloat16mf2x7_t): Ditto.
(vfloat16mf2x8_t): Ditto.
(vfloat16m1x2_t): Ditto.
(vfloat16m1x3_t): Ditto.
(vfloat16m1x4_t): Ditto.
(vfloat16m1x5_t): Ditto.
(vfloat16m1x6_t): Ditto.
(vfloat16m1x7_t): Ditto.
(vfloat16m1x8_t): Ditto.
(vfloat16m2x2_t): Ditto.
(vfloat16m2x3_t): Diito.
(vfloat16m2x4_t): Diito.
(vfloat16m4x2_t): Diito.
* config/riscv/riscv-vector-builtins.def (vfloat16mf4x2_t): Ditto.
(vfloat16mf4x3_t): Ditto.
(vfloat16mf4x4_t): Ditto.
(vfloat16mf4x5_t): Ditto.
(vfloat16mf4x6_t): Ditto.
(vfloat16mf4x7_t): Ditto.
(vfloat16mf4x8_t): Ditto.
(vfloat16mf2x2_t): Ditto.
(vfloat16mf2x3_t): Ditto.
(vfloat16mf2x4_t): Ditto.
(vfloat16mf2x5_t): Ditto.
(vfloat16mf2x6_t): Ditto.
(vfloat16mf2x7_t): Ditto.
(vfloat16mf2x8_t): Ditto.
(vfloat16m1x2_t): Ditto.
(vfloat16m1x3_t): Ditto.
(vfloat16m1x4_t): Ditto.
(vfloat16m1x5_t): Ditto.
(vfloat16m1x6_t): Ditto.
(vfloat16m1x7_t): Ditto.
(vfloat16m1x8_t): Ditto.
(vfloat16m2x2_t): Ditto.
(vfloat16m2x3_t): Ditto.
(vfloat16m2x4_t): Ditto.
(vfloat16m4x2_t): Ditto.
* config/riscv/riscv-vector-switch.def (TUPLE_ENTRY): Ditto.
* config/riscv/riscv.md: Ditto.
* config/riscv/vector-iterators.md: Ditto.
2023-06-25 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* gimple-fold.cc (arith_overflowed_p): Apply LEN_MASK_{LOAD,STORE}.
(gimple_fold_partial_load_store_mem_ref): Ditto.
(gimple_fold_partial_store): Ditto.
(gimple_fold_call): Ditto.
2023-06-25 liuhongt <hongtao.liu@intel.com>
PR target/110309
* config/i386/sse.md (maskload<mode><avx512fmaskmodelower>):
Refine pattern with UNSPEC_MASKLOAD.
(maskload<mode><avx512fmaskmodelower>): Ditto.
(*<avx512>_load<mode>_mask): Extend mode iterator to
VI12HFBF_AVX512VL.
(*<avx512>_load<mode>): Ditto.
2023-06-25 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* tree-ssa-alias.cc (call_may_clobber_ref_p_1): Add LEN_MASK_STORE.
2023-06-25 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* tree-ssa-alias.cc (ref_maybe_used_by_call_p_1): Apply
LEN_MASK_{LOAD,STORE}
2023-06-25 yulong <shiyulong@iscas.ac.cn>
* config/riscv/vector.md: Add float16 attr at sew、vlmul and ratio.
2023-06-24 Roger Sayle <roger@nextmovesoftware.com>
* config/i386/i386.md (*<code>qi_ext<mode>_3): New define_insn.
2023-06-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/autovec.md (*fma<mode>): set clobber to Pmode in expand stage.
(*fma<VI:mode><P:mode>): Ditto.
(*fnma<mode>): Ditto.
(*fnma<VI:mode><P:mode>): Ditto.
2023-06-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/autovec.md (fma<mode>4): New pattern.
(*fma<mode>): Ditto.
(fnma<mode>4): Ditto.
(*fnma<mode>): Ditto.
(fms<mode>4): Ditto.
(*fms<mode>): Ditto.
(fnms<mode>4): Ditto.
(*fnms<mode>): Ditto.
* config/riscv/riscv-protos.h (emit_vlmax_fp_ternary_insn):
New function.
* config/riscv/riscv-v.cc (emit_vlmax_fp_ternary_insn): Ditto.
* config/riscv/vector.md: Fix attribute bug.
2023-06-24 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* tree-ssa-loop-ivopts.cc (get_mem_type_for_internal_fn):
Apply LEN_MASK_{LOAD,STORE}.
2023-06-24 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* tree-ssa-loop-ivopts.cc (get_alias_ptr_type_for_ptr_address):
Add LEN_MASK_{LOAD,STORE}.
2023-06-24 David Malcolm <dmalcolm@redhat.com>
* diagnostic-format-sarif.cc: Add #define INCLUDE_VECTOR.
* diagnostic.cc: Likewise.
* text-art/box-drawing.cc: Likewise.
* text-art/canvas.cc: Likewise.
* text-art/ruler.cc: Likewise.
* text-art/selftests.cc: Likewise.
* text-art/selftests.h (text_art::canvas): New forward decl.
* text-art/style.cc: Add #define INCLUDE_VECTOR.
* text-art/styled-string.cc: Likewise.
* text-art/table.cc: Likewise.
* text-art/table.h: Remove #include <vector>.
* text-art/theme.cc: Add #define INCLUDE_VECTOR.
* text-art/types.h: Check that INCLUDE_VECTOR is defined.
Remove #include of <vector> and <string>.
* text-art/widget.cc: Add #define INCLUDE_VECTOR.
* text-art/widget.h: Remove #include <vector>.
2023-06-24 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* internal-fn.cc (expand_partial_store_optab_fn): Adapt for LEN_MASK_STORE.
(internal_load_fn_p): Add LEN_MASK_LOAD.
(internal_store_fn_p): Add LEN_MASK_STORE.
(internal_fn_mask_index): Add LEN_MASK_{LOAD,STORE}.
(internal_fn_stored_value_index): Add LEN_MASK_STORE.
(internal_len_load_store_bias): Add LEN_MASK_{LOAD,STORE}.
* optabs-tree.cc (can_vec_mask_load_store_p): Adapt for LEN_MASK_{LOAD,STORE}.
(get_len_load_store_mode): Ditto.
* optabs-tree.h (can_vec_mask_load_store_p): Ditto.
(get_len_load_store_mode): Ditto.
* tree-vect-stmts.cc (check_load_store_for_partial_vectors): Ditto.
(get_all_ones_mask): New function.
(vectorizable_store): Apply LEN_MASK_{LOAD,STORE} into vectorizer.
(vectorizable_load): Ditto.
2023-06-23 Marek Polacek <polacek@redhat.com>
* doc/cpp.texi (__cplusplus): Document value for -std=c++26 and
-std=gnu++26. Document that for C++23, its value is 202302L.
* doc/invoke.texi: Document -std=c++26 and -std=gnu++26.
* dwarf2out.cc (highest_c_language): Handle GNU C++26.
(gen_compile_unit_die): Likewise.
2023-06-23 Jan Hubicka <jh@suse.cz>
* tree-ssa-phiprop.cc (propagate_with_phi): Compute post dominators on
demand.
(pass_phiprop::execute): Do not compute it here; return
update_ssa_only_virtuals if something changed.
(pass_data_phiprop): Remove TODO_update_ssa from todos.
2023-06-23 Michael Meissner <meissner@linux.ibm.com>
Aaron Sawdey <acsawdey@linux.ibm.com>
PR target/105325
* config/rs6000/genfusion.pl (gen_ld_cmpi_p10_one): Fix problems that
allowed prefixed lwa to be generated.
* config/rs6000/fusion.md: Regenerate.
* config/rs6000/predicates.md (ds_form_mem_operand): Delete.
* config/rs6000/rs6000.md (prefixed attribute): Add support for load
plus compare immediate fused insns.
(maybe_prefixed): Likewise.
2023-06-23 Roger Sayle <roger@nextmovesoftware.com>
* simplify-rtx.cc (simplify_subreg): Optimize lowpart SUBREGs
of ASHIFT to const0_rtx with sufficiently large shift count.
Optimize highpart SUBREGs of ASHIFT as the shift operand when
the shift count is the correct offset. Optimize SUBREGs of
multi-word logic operations if the SUBREGs of both operands
can be simplified.
2023-06-23 Richard Biener <rguenther@suse.de>
* varasm.cc (initializer_constant_valid_p_1): Only
allow conversions between scalar floating point types.
2023-06-23 Richard Biener <rguenther@suse.de>
* tree-vect-stmts.cc (vectorizable_assignment):
Properly handle non-integral operands when analyzing
conversions.
2023-06-23 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
PR tree-optimization/110280
* match.pd (vec_perm_expr(v, v, mask) -> v): Explicitly build vector
using build_vector_from_val with the element of input operand, and
mask's type if operand and mask's types don't match.
2023-06-23 Richard Biener <rguenther@suse.de>
* fold-const.cc (tree_simple_nonnegative_warnv_p): Guard
the truth_value_p case with !VECTOR_TYPE_P.
2023-06-23 Richard Biener <rguenther@suse.de>
* tree-vect-patterns.cc (vect_look_through_possible_promotion):
Exit early when the type isn't scalar integral.
2023-06-23 Richard Biener <rguenther@suse.de>
* match.pd ((outertype)((innertype0)a+(innertype1)b)
-> ((newtype)a+(newtype)b)): Use element_precision
where appropriate.
2023-06-23 Richard Biener <rguenther@suse.de>
* fold-const.cc (fold_binary_loc): Use element_precision
when trying (double)float1 CMP (double)float2 to
float1 CMP float2 simplification.
* match.pd: Likewise.
2023-06-23 Richard Biener <rguenther@suse.de>
* tree-vect-stmts.cc (vectorizable_load): Avoid useless
copies of VMAT_INVARIANT vectorized stmts, fix SLP support.
2023-06-23 Richard Biener <rguenther@suse.de>
* tree-vect-stmts.cc (vector_vector_composition_type):
Handle composition of a vector from a number of elements that
happens to match its number of lanes.
2023-06-22 Marek Polacek <polacek@redhat.com>
* configure.ac (--enable-host-bind-now): New check. Add
-Wl,-z,now to LD_PICFLAG if --enable-host-bind-now.
* configure: Regenerate.
* doc/install.texi: Document --enable-host-bind-now.
2023-06-22 Di Zhao OS <dizhao@os.amperecomputing.com>
* config/aarch64/aarch64.cc: Change fma_reassoc_width for ampere1.
2023-06-22 Richard Biener <rguenther@suse.de>
PR tree-optimization/110332
* tree-ssa-phiprop.cc (propagate_with_phi): Always
check aliasing with edge inserted loads.
2023-06-22 Roger Sayle <roger@nextmovesoftware.com>
Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386-expand.cc (ix86_expand_sse_ptest): Recognize
expansion of ptestc with equal operands as producing const1_rtx.
* config/i386/i386.cc (ix86_rtx_costs): Provide accurate cost
estimates of UNSPEC_PTEST, where the ptest performs the PAND
or PAND of its operands.
* config/i386/sse.md (define_split): Transform CCCmode UNSPEC_PTEST
of reg_equal_p operands into an x86_stc instruction.
(define_split): Split pandn/ptestz/set{n?}e into ptestc/set{n?}c.
(define_split): Similar to above for strict_low_part destinations.
(define_split): Split pandn/ptestz/j{n?}e into ptestc/j{n?}c.
2023-06-22 David Malcolm <dmalcolm@redhat.com>
PR analyzer/106626
* Makefile.in (ANALYZER_OBJS): Add analyzer/access-diagram.o.
* doc/invoke.texi (Wanalyzer-out-of-bounds): Add description of
text art.
(fanalyzer-debug-text-art): New.
2023-06-22 David Malcolm <dmalcolm@redhat.com>
* Makefile.in (OBJS-libcommon): Add text-art/box-drawing.o,
text-art/canvas.o, text-art/ruler.o, text-art/selftests.o,
text-art/style.o, text-art/styled-string.o, text-art/table.o,
text-art/theme.o, and text-art/widget.o.
* color-macros.h (COLOR_FG_BRIGHT_BLACK): New.
(COLOR_FG_BRIGHT_RED): New.
(COLOR_FG_BRIGHT_GREEN): New.
(COLOR_FG_BRIGHT_YELLOW): New.
(COLOR_FG_BRIGHT_BLUE): New.
(COLOR_FG_BRIGHT_MAGENTA): New.
(COLOR_FG_BRIGHT_CYAN): New.
(COLOR_FG_BRIGHT_WHITE): New.
(COLOR_BG_BRIGHT_BLACK): New.
(COLOR_BG_BRIGHT_RED): New.
(COLOR_BG_BRIGHT_GREEN): New.
(COLOR_BG_BRIGHT_YELLOW): New.
(COLOR_BG_BRIGHT_BLUE): New.
(COLOR_BG_BRIGHT_MAGENTA): New.
(COLOR_BG_BRIGHT_CYAN): New.
(COLOR_BG_BRIGHT_WHITE): New.
* common.opt (fdiagnostics-text-art-charset=): New option.
(diagnostic-text-art.h): New SourceInclude.
(diagnostic_text_art_charset) New Enum and EnumValues.
* configure: Regenerate.
* configure.ac (gccdepdir): Add text-art to loop.
* diagnostic-diagram.h: New file.
* diagnostic-format-json.cc (json_emit_diagram): New.
(diagnostic_output_format_init_json): Wire it up to
context->m_diagrams.m_emission_cb.
* diagnostic-format-sarif.cc: Include "diagnostic-diagram.h" and
"text-art/canvas.h".
(sarif_result::on_nested_diagnostic): Move code to...
(sarif_result::add_related_location): ...this new function.
(sarif_result::on_diagram): New.
(sarif_builder::emit_diagram): New.
(sarif_builder::make_message_object_for_diagram): New.
(sarif_emit_diagram): New.
(diagnostic_output_format_init_sarif): Set
context->m_diagrams.m_emission_cb to sarif_emit_diagram.
* diagnostic-text-art.h: New file.
* diagnostic.cc: Include "diagnostic-text-art.h",
"diagnostic-diagram.h", and "text-art/theme.h".
(diagnostic_initialize): Initialize context->m_diagrams and
call diagnostics_text_art_charset_init.
(diagnostic_finish): Clean up context->m_diagrams.m_theme.
(diagnostic_emit_diagram): New.
(diagnostics_text_art_charset_init): New.
* diagnostic.h (text_art::theme): New forward decl.
(class diagnostic_diagram): Likewise.
(diagnostic_context::m_diagrams): New field.
(diagnostic_emit_diagram): New decl.
* doc/invoke.texi (Diagnostic Message Formatting Options): Add
-fdiagnostics-text-art-charset=.
(-fdiagnostics-plain-output): Add
-fdiagnostics-text-art-charset=none.
* gcc.cc: Include "diagnostic-text-art.h".
(driver_handle_option): Handle OPT_fdiagnostics_text_art_charset_.
* opts-common.cc (decode_cmdline_options_to_array): Add
"-fdiagnostics-text-art-charset=none" to expanded_args for
-fdiagnostics-plain-output.
* opts.cc: Include "diagnostic-text-art.h".
(common_handle_option): Handle OPT_fdiagnostics_text_art_charset_.
* pretty-print.cc (pp_unicode_character): New.
* pretty-print.h (pp_unicode_character): New decl.
* selftest-run-tests.cc: Include "text-art/selftests.h".
(selftest::run_tests): Call text_art_tests.
* text-art/box-drawing-chars.inc: New file, generated by
contrib/unicode/gen-box-drawing-chars.py.
* text-art/box-drawing.cc: New file.
* text-art/box-drawing.h: New file.
* text-art/canvas.cc: New file.
* text-art/canvas.h: New file.
* text-art/ruler.cc: New file.
* text-art/ruler.h: New file.
* text-art/selftests.cc: New file.
* text-art/selftests.h: New file.
* text-art/style.cc: New file.
* text-art/styled-string.cc: New file.
* text-art/table.cc: New file.
* text-art/table.h: New file.
* text-art/theme.cc: New file.
* text-art/theme.h: New file.
* text-art/types.h: New file.
* text-art/widget.cc: New file.
* text-art/widget.h: New file.
2023-06-21 Uros Bizjak <ubizjak@gmail.com>
* function.h (emit_initial_value_sets):
Change return type from int to void.
(aggregate_value_p): Change return type from int to bool.
(prologue_contains): Ditto.
(epilogue_contains): Ditto.
(prologue_epilogue_contains): Ditto.
* function.cc (temp_slot): Make "in_use" variable bool.
(make_slot_available): Update for changed "in_use" variable.
(assign_stack_temp_for_type): Ditto.
(emit_initial_value_sets): Change return type from int to void
and update function body accordingly.
(instantiate_virtual_regs): Ditto.
(rest_of_handle_thread_prologue_and_epilogue): Ditto.
(safe_insn_predicate): Change return type from int to bool.
(aggregate_value_p): Change return type from int to bool
and update function body accordingly.
(prologue_contains): Change return type from int to bool.
(prologue_epilogue_contains): Ditto.
2023-06-21 Alexander Monakov <amonakov@ispras.ru>
* common.opt (fp_contract_mode) [on]: Remove fallback.
* config/sh/sh.md (*fmasf4): Correct flag_fp_contract_mode test.
* doc/invoke.texi (-ffp-contract): Update.
* trans-mem.cc (diagnose_tm_1): Skip internal function calls.
2023-06-21 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-sve.md (mask_gather_load<mode><v_int_container>):
Add alternatives to prefer to avoid same input and output Z register.
(mask_gather_load<mode><v_int_container>): Likewise.
(*mask_gather_load<mode><v_int_container>_<su>xtw_unpacked): Likewise.
(*mask_gather_load<mode><v_int_container>_sxtw): Likewise.
(*mask_gather_load<mode><v_int_container>_uxtw): Likewise.
(@aarch64_gather_load_<ANY_EXTEND:optab><SVE_4HSI:mode><SVE_4BHI:mode>):
Likewise.
(@aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode><SVE_2BHSI:mode>):
Likewise.
(*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
<SVE_2BHSI:mode>_<ANY_EXTEND2:su>xtw_unpacked): Likewise.
(*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
<SVE_2BHSI:mode>_sxtw): Likewise.
(*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
<SVE_2BHSI:mode>_uxtw): Likewise.
(@aarch64_ldff1_gather<mode>): Likewise.
(@aarch64_ldff1_gather<mode>): Likewise.
(*aarch64_ldff1_gather<mode>_sxtw): Likewise.
(*aarch64_ldff1_gather<mode>_uxtw): Likewise.
(@aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx4_WIDE:mode>
<VNx4_NARROW:mode>): Likewise.
(@aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode>
<VNx2_NARROW:mode>): Likewise.
(*aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode>
<VNx2_NARROW:mode>_sxtw): Likewise.
(*aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode>
<VNx2_NARROW:mode>_uxtw): Likewise.
* config/aarch64/aarch64-sve2.md (@aarch64_gather_ldnt<mode>): Likewise.
(@aarch64_gather_ldnt_<ANY_EXTEND:optab><SVE_FULL_SDI:mode>
<SVE_PARTIAL_I:mode>): Likewise.
2023-06-21 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-sve.md (mask_gather_load<mode><v_int_container>):
Convert to compact alternatives syntax.
(mask_gather_load<mode><v_int_container>): Likewise.
(*mask_gather_load<mode><v_int_container>_<su>xtw_unpacked): Likewise.
(*mask_gather_load<mode><v_int_container>_sxtw): Likewise.
(*mask_gather_load<mode><v_int_container>_uxtw): Likewise.
(@aarch64_gather_load_<ANY_EXTEND:optab><SVE_4HSI:mode><SVE_4BHI:mode>):
Likewise.
(@aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode><SVE_2BHSI:mode>):
Likewise.
(*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
<SVE_2BHSI:mode>_<ANY_EXTEND2:su>xtw_unpacked): Likewise.
(*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
<SVE_2BHSI:mode>_sxtw): Likewise.
(*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
<SVE_2BHSI:mode>_uxtw): Likewise.
(@aarch64_ldff1_gather<mode>): Likewise.
(@aarch64_ldff1_gather<mode>): Likewise.
(*aarch64_ldff1_gather<mode>_sxtw): Likewise.
(*aarch64_ldff1_gather<mode>_uxtw): Likewise.
(@aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx4_WIDE:mode>
<VNx4_NARROW:mode>): Likewise.
(@aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode>
<VNx2_NARROW:mode>): Likewise.
(*aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode>
<VNx2_NARROW:mode>_sxtw): Likewise.
(*aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode>
<VNx2_NARROW:mode>_uxtw): Likewise.
* config/aarch64/aarch64-sve2.md (@aarch64_gather_ldnt<mode>): Likewise.
(@aarch64_gather_ldnt_<ANY_EXTEND:optab><SVE_FULL_SDI:mode>
<SVE_PARTIAL_I:mode>): Likewise.
2023-06-21 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Revert:
2023-06-21 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-sve.md (mask_gather_load<mode><v_int_container>):
Convert to compact alternatives syntax.
(mask_gather_load<mode><v_int_container>): Likewise.
(*mask_gather_load<mode><v_int_container>_<su>xtw_unpacked): Likewise.
(*mask_gather_load<mode><v_int_container>_sxtw): Likewise.
(*mask_gather_load<mode><v_int_container>_uxtw): Likewise.
(@aarch64_gather_load_<ANY_EXTEND:optab><SVE_4HSI:mode><SVE_4BHI:mode>):
Likewise.
(@aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode><SVE_2BHSI:mode>):
Likewise.
(*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
<SVE_2BHSI:mode>_<ANY_EXTEND2:su>xtw_unpacked): Likewise.
(*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
<SVE_2BHSI:mode>_sxtw): Likewise.
(*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
<SVE_2BHSI:mode>_uxtw): Likewise.
(@aarch64_ldff1_gather<mode>): Likewise.
(@aarch64_ldff1_gather<mode>): Likewise.
(*aarch64_ldff1_gather<mode>_sxtw): Likewise.
(*aarch64_ldff1_gather<mode>_uxtw): Likewise.
(@aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx4_WIDE:mode>
<VNx4_NARROW:mode>): Likewise.
(@aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode>
<VNx2_NARROW:mode>): Likewise.
(*aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode>
<VNx2_NARROW:mode>_sxtw): Likewise.
(*aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode>
<VNx2_NARROW:mode>_uxtw): Likewise.
* config/aarch64/aarch64-sve2.md (@aarch64_gather_ldnt<mode>): Likewise.
(@aarch64_gather_ldnt_<ANY_EXTEND:optab><SVE_FULL_SDI:mode>
<SVE_PARTIAL_I:mode>): Likewise.
2023-06-21 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* optabs-query.cc (can_vec_mask_load_store_p): Move to optabs-tree.cc.
(get_len_load_store_mode): Ditto.
* optabs-query.h (can_vec_mask_load_store_p): Move to optabs-tree.h.
(get_len_load_store_mode): Ditto.
* optabs-tree.cc (can_vec_mask_load_store_p): New function.
(get_len_load_store_mode): Ditto.
* optabs-tree.h (can_vec_mask_load_store_p): Ditto.
(get_len_load_store_mode): Ditto.
* tree-if-conv.cc: include optabs-tree instead of optabs-query
2023-06-21 Richard Biener <rguenther@suse.de>
* tree-ssa-loop-ivopts.cc (add_iv_candidate_for_use): Use
split_constant_offset for the POINTER_PLUS_EXPR case.
2023-06-21 Richard Biener <rguenther@suse.de>
* tree-ssa-loop-ivopts.cc (record_group_use): Use
split_constant_offset.
2023-06-21 Richard Biener <rguenther@suse.de>
* tree-loop-distribution.cc (classify_builtin_st): Use
split_constant_offset.
* tree-ssa-loop-ivopts.h (strip_offset): Remove.
* tree-ssa-loop-ivopts.cc (strip_offset): Make static.
2023-06-21 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-sve.md (mask_gather_load<mode><v_int_container>):
Convert to compact alternatives syntax.
(mask_gather_load<mode><v_int_container>): Likewise.
(*mask_gather_load<mode><v_int_container>_<su>xtw_unpacked): Likewise.
(*mask_gather_load<mode><v_int_container>_sxtw): Likewise.
(*mask_gather_load<mode><v_int_container>_uxtw): Likewise.
(@aarch64_gather_load_<ANY_EXTEND:optab><SVE_4HSI:mode><SVE_4BHI:mode>):
Likewise.
(@aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode><SVE_2BHSI:mode>):
Likewise.
(*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
<SVE_2BHSI:mode>_<ANY_EXTEND2:su>xtw_unpacked): Likewise.
(*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
<SVE_2BHSI:mode>_sxtw): Likewise.
(*aarch64_gather_load_<ANY_EXTEND:optab><SVE_2HSDI:mode>
<SVE_2BHSI:mode>_uxtw): Likewise.
(@aarch64_ldff1_gather<mode>): Likewise.
(@aarch64_ldff1_gather<mode>): Likewise.
(*aarch64_ldff1_gather<mode>_sxtw): Likewise.
(*aarch64_ldff1_gather<mode>_uxtw): Likewise.
(@aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx4_WIDE:mode>
<VNx4_NARROW:mode>): Likewise.
(@aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode>
<VNx2_NARROW:mode>): Likewise.
(*aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode>
<VNx2_NARROW:mode>_sxtw): Likewise.
(*aarch64_ldff1_gather_<ANY_EXTEND:optab><VNx2_WIDE:mode>
<VNx2_NARROW:mode>_uxtw): Likewise.
* config/aarch64/aarch64-sve2.md (@aarch64_gather_ldnt<mode>): Likewise.
(@aarch64_gather_ldnt_<ANY_EXTEND:optab><SVE_FULL_SDI:mode>
<SVE_PARTIAL_I:mode>): Likewise.
2023-06-21 Tamar Christina <tamar.christina@arm.com>
PR other/110329
* doc/md.texi: Replace backslashchar.
2023-06-21 Richard Biener <rguenther@suse.de>
* config/i386/i386.cc (ix86_vector_costs::finish_cost):
Overload. For masked main loops make sure the vectorization
factor isn't more than double the number of iterations.
2023-06-21 Jan Beulich <jbeulich@suse.com>
* config/i386/i386-expand.cc (ix86_expand_copysign): Request
value duplication by ix86_build_signbit_mask() when AVX512F and
not HFmode.
* config/i386/sse.md (*<avx512>_vternlog<mode>_all): Convert to
2-alternative form. Adjust "mode" attribute. Add "enabled"
attribute.
(*<avx512>_vpternlog<mode>_1): Also permit when TARGET_AVX512F
&& !TARGET_PREFER_AVX256.
(*<avx512>_vpternlog<mode>_2): Likewise.
(*<avx512>_vpternlog<mode>_3): Likewise.
2023-06-21 liuhongt <hongtao.liu@intel.com>
PR target/110018
* tree-vect-stmts.cc (vectorizable_conversion): Use
intermiediate integer type for float_expr/fix_trunc_expr when
direct optab is not existed.
2023-06-20 Tamar Christina <tamar.christina@arm.com>
PR bootstrap/110324
* gensupport.cc (convert_syntax): Explicitly check for RTX code.
2023-06-20 Richard Sandiford <richard.sandiford@arm.com>
* config/aarch64/aarch64.md (stack_tie): Hard-code the first
register operand to the stack pointer. Require the second register
operand to have the number specified in a separate const_int operand.
* config/aarch64/aarch64.cc (aarch64_emit_stack_tie): New function.
(aarch64_allocate_and_probe_stack_space): Use it.
(aarch64_expand_prologue, aarch64_expand_epilogue): Likewise.
(aarch64_expand_epilogue): Likewise.
2023-06-20 Jakub Jelinek <jakub@redhat.com>
PR middle-end/79173
* tree-ssa-math-opts.cc (match_uaddc_usubc): Remember lhs of
IMAGPART_EXPR of arg2/arg3 and use that as arg3 if it has the right
type.
2023-06-20 Uros Bizjak <ubizjak@gmail.com>
* calls.h (setjmp_call_p): Change return type from int to bool.
* calls.cc (struct arg_data): Change "pass_on_stack" to bool.
(store_one_arg): Change return type from int to bool
and adjust function body accordingly. Change "sibcall_failure"
variable to bool.
(finalize_must_preallocate): Ditto. Change *must_preallocate pointer
argument to bool. Change "partial_seen" variable to bool.
(load_register_parameters): Change *sibcall_failure
pointer argument to bool.
(check_sibcall_argument_overlap_1): Change return type from int to bool
and adjust function body accordingly.
(check_sibcall_argument_overlap): Ditto. Change
"mark_stored_args_map" argument to bool.
(emit_call_1): Change "already_popped" variable to bool.
(setjmp_call_p): Change return type from int to bool
and adjust function body accordingly.
(initialize_argument_information): Change *must_preallocate
pointer argument to bool.
(expand_call): Change "pcc_struct_value", "must_preallocate"
and "sibcall_failure" variables to bool.
(emit_library_call_value_1): Change "pcc_struct_value"
variable to bool.
2023-06-20 Martin Jambor <mjambor@suse.cz>
PR ipa/110276
* ipa-sra.cc (struct caller_issues): New field there_is_one.
(check_for_caller_issues): Set it.
(check_all_callers_for_issues): Check it.
2023-06-20 Martin Jambor <mjambor@suse.cz>
* ipa-prop.h (ipa_uid_to_idx_map_elt): New type.
(struct ipcp_transformation): Rearrange members according to
C++ class coding convention, add m_uid_to_idx,
get_param_index and maybe_create_parm_idx_map.
* ipa-cp.cc (ipcp_transformation::get_param_index): New function.
(compare_uids): Likewise.
(ipcp_transformation::maype_create_parm_idx_map): Likewise.
* ipa-prop.cc (ipcp_get_parm_bits): Use get_param_index.
(ipcp_update_bits): Accept TS as a parameter, assume it is not NULL.
(ipcp_update_vr): Likewise.
(ipcp_transform_function): Call, maybe_create_parm_idx_map of TS, bail
out quickly if empty, pass it to ipcp_update_bits and ipcp_update_vr.
2023-06-20 Carl Love <cel@us.ibm.com>
* config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin):
Rename CODE_FOR_xsxsigqp_tf to CODE_FOR_xsxsigqp_tf_ti.
Rename CODE_FOR_xsxsigqp_kf to CODE_FOR_xsxsigqp_kf_ti.
Rename CCDE_FOR_xsxexpqp_tf to CODE_FOR_xsxexpqp_tf_di.
Rename CODE_FOR_xsxexpqp_kf to CODE_FOR_xsxexpqp_kf_di.
(CODE_FOR_xsxexpqp_kf_v2di, CODE_FOR_xsxsigqp_kf_v1ti,
CODE_FOR_xsiexpqp_kf_v2di): Add case statements.
* config/rs6000/rs6000-builtins.def
(__builtin_vsx_scalar_extract_exp_to_vec,
__builtin_vsx_scalar_extract_sig_to_vec,
__builtin_vsx_scalar_insert_exp_vqp): Add new builtin definitions.
Rename xsxexpqp_kf, xsxsigqp_kf, xsiexpqp_kf to xsexpqp_kf_di,
xsxsigqp_kf_ti, xsiexpqp_kf_di respectively.
* config/rs6000/rs6000-c.cc (altivec_resolve_overloaded_builtin):
Update case RS6000_OVLD_VEC_VSIE to handle MODE_VECTOR_INT for new
overloaded instance. Update comments.
* config/rs6000/rs6000-overload.def
(__builtin_vec_scalar_insert_exp): Add new overload definition with
vector arguments.
(scalar_extract_exp_to_vec, scalar_extract_sig_to_vec): New
overloaded definitions.
* config/rs6000/vsx.md (V2DI_DI): New mode iterator.
(DI_to_TI): New mode attribute.
Rename xsxexpqp_<mode> to sxexpqp_<IEEE128:mode>_<V2DI_DI:mode>.
Rename xsxsigqp_<mode> to xsxsigqp_<IEEE128:mode>_<VEC_TI:mode>.
Rename xsiexpqp_<mode> to xsiexpqp_<IEEE128:mode>_<V2DI_DI:mode>.
* doc/extend.texi (scalar_extract_exp_to_vec,
scalar_extract_sig_to_vec): Add documentation for new builtins.
(scalar_insert_exp): Add new overloaded builtin definition.
2023-06-20 Li Xu <xuli1@eswincomputing.com>
* config/riscv/riscv.cc (riscv_regmode_natural_size): set the natural
size of vector mask mode to one rvv register.
2023-06-20 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-v.cc (expand_const_vector): Optimize codegen.
2023-06-20 Lehua Ding <lehua.ding@rivai.ai>
* config/riscv/riscv.cc (riscv_arg_has_vector): Add default
switch handler.
2023-06-20 Richard Biener <rguenther@suse.de>
* tree-ssa-dse.cc (dse_classify_store): When we found
no defs and the basic-block with the original definition
ends in __builtin_unreachable[_trap] the store is dead.
2023-06-20 Richard Biener <rguenther@suse.de>
* tree-ssa-phiprop.cc (phiprop_insert_phi): For simple loads
keep the virtual SSA form up-to-date.
2023-06-20 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-simd.md (*aarch64_addp_same_reg<mode>):
New define_insn_and_split.
2023-06-20 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64.md (*mov<mode>_aarch64): Drop test comment.
2023-06-20 Jan Beulich <jbeulich@suse.com>
* config/i386/sse.md (vec_dupv2di): Correct %vmovddup input
constraint. Add new AVX512F alternative.
2023-06-20 Richard Biener <rguenther@suse.de>
PR debug/110295
* dwarf2out.cc (process_scope_var): Continue processing
the decl after setting a parent in case the existing DIE
was in limbo.
2023-06-20 Lehua Ding <lehua.ding@rivai.ai>
* config/riscv/riscv.cc (riscv_scalable_vector_type_p): Delete.
(riscv_arg_has_vector): Simplify.
(riscv_pass_in_vector_p): Adjust warning message.
2023-06-19 Jin Ma <jinma@linux.alibaba.com>
* config/riscv/riscv.cc (riscv_compute_frame_info): Allocate frame for FCSR.
(riscv_for_each_saved_reg): Save and restore FCSR in interrupt functions.
* config/riscv/riscv.md (riscv_frcsr): New patterns.
(riscv_fscsr): Likewise.
2023-06-19 Toru Kisuki <tkisuki@tachyum.com>
PR rtl-optimization/110305
* simplify-rtx.cc (simplify_context::simplify_binary_operation_1):
Handle HONOR_SNANS for x + 0.0.
2023-06-19 Jan Hubicka <jh@suse.cz>
PR tree-optimization/109811
PR tree-optimization/109849
* passes.def: Add phiprop to early optimization passes.
* tree-ssa-phiprop.cc: Allow clonning.
2023-06-19 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64.md (arches): Add nosimd.
(*mov<mode>_aarch64, *movsi_aarch64, *movdi_aarch64): Rewrite to
compact syntax.
2023-06-19 Tamar Christina <tamar.christina@arm.com>
Omar Tahir <Omar.Tahir2@arm.com>
* gensupport.cc (class conlist, add_constraints, add_attributes,
skip_spaces, expect_char, preprocess_compact_syntax,
parse_section_layout, parse_section, convert_syntax): New.
(process_rtx): Check for conversion.
* genoutput.cc (process_template): Check for unresolved iterators.
(class data): Add compact_syntax_p.
(gen_insn): Use it.
* gensupport.h (compact_syntax): New.
(hash-set.h): Include.
* doc/md.texi: Document it.
2023-06-19 Uros Bizjak <ubizjak@gmail.com>
* recog.h (check_asm_operands): Change return type from int to bool.
(insn_invalid_p): Ditto.
(verify_changes): Ditto.
(apply_change_group): Ditto.
(constrain_operands): Ditto.
(constrain_operands_cached): Ditto.
(validate_replace_rtx_subexp): Ditto.
(validate_replace_rtx): Ditto.
(validate_replace_rtx_part): Ditto.
(validate_replace_rtx_part_nosimplify): Ditto.
(added_clobbers_hard_reg_p): Ditto.
(peep2_regno_dead_p): Ditto.
(peep2_reg_dead_p): Ditto.
(store_data_bypass_p): Ditto.
(if_test_bypass_p): Ditto.
* rtl.h (split_all_insns_noflow): Change
return type from unsigned int to void.
* genemit.cc (output_added_clobbers_hard_reg_p): Change return type
of generated added_clobbers_hard_reg_p from int to bool and adjust
function body accordingly. Change "used" variable type from
int to bool.
* recog.cc (check_asm_operands): Change return type
from int to bool and adjust function body accordingly.
(insn_invalid_p): Ditto. Change "is_asm" variable to bool.
(verify_changes): Change return type from int to bool.
(apply_change_group): Change return type from int to bool
and adjust function body accordingly.
(validate_replace_rtx_subexp): Change return type from int to bool.
(validate_replace_rtx): Ditto.
(validate_replace_rtx_part): Ditto.
(validate_replace_rtx_part_nosimplify): Ditto.
(constrain_operands_cached): Ditto.
(constrain_operands): Ditto. Change "lose" and "win"
variables type from int to bool.
(split_all_insns_noflow): Change return type from unsigned int
to void and adjust function body accordingly.
(peep2_regno_dead_p): Change return type from int to bool.
(peep2_reg_dead_p): Ditto.
(peep2_find_free_register): Change "success"
variable type from int to bool
(store_data_bypass_p_1): Change return type from int to bool.
(store_data_bypass_p): Ditto.
2023-06-19 Li Xu <xuli1@eswincomputing.com>
* config/riscv/vector-iterators.md: zvfh/zvfhmin depends on the
Zve32f extension.
2023-06-19 Pan Li <pan2.li@intel.com>
PR target/110299
* config/riscv/riscv-vector-builtins-bases.cc: Adjust expand for
modes.
* config/riscv/vector-iterators.md: Remove VWLMUL1, VWLMUL1_ZVE64,
VWLMUL1_ZVE32, VI_ZVE64, VI_ZVE32, VWI, VWI_ZVE64, VWI_ZVE32,
VF_ZVE63 and VF_ZVE32.
* config/riscv/vector.md
(@pred_widen_reduc_plus<v_su><mode><vwlmul1>): Removed.
(@pred_widen_reduc_plus<v_su><mode><vwlmul1_zve64>): Ditto.
(@pred_widen_reduc_plus<v_su><mode><vwlmul1_zve32>): Ditto.
(@pred_widen_reduc_plus<order><mode><vwlmul1>): Ditto.
(@pred_widen_reduc_plus<order><mode><vwlmul1_zve64>): Ditto.
(@pred_widen_reduc_plus<v_su><VQI:mode><VHI_LMUL1:mode>): New pattern.
(@pred_widen_reduc_plus<v_su><VHI:mode><VSI_LMUL1:mode>): Ditto.
(@pred_widen_reduc_plus<v_su><VSI:mode><VDI_LMUL1:mode>): Ditto.
(@pred_widen_reduc_plus<order><VHF:mode><VSF_LMUL1:mode>): Ditto.
(@pred_widen_reduc_plus<order><VSF:mode><VDF_LMUL1:mode>): Ditto.
2023-06-19 Pan Li <pan2.li@intel.com>
PR target/110277
* config/riscv/riscv-vector-builtins-bases.cc: Adjust expand for
ret_mode.
* config/riscv/vector-iterators.md: Add VHF, VSF, VDF,
VHF_LMUL1, VSF_LMUL1, VDF_LMUL1, and remove unused attr.
* config/riscv/vector.md (@pred_reduc_<reduc><mode><vlmul1>): Removed.
(@pred_reduc_<reduc><mode><vlmul1_zve64>): Ditto.
(@pred_reduc_<reduc><mode><vlmul1_zve32>): Ditto.
(@pred_reduc_plus<order><mode><vlmul1>): Ditto.
(@pred_reduc_plus<order><mode><vlmul1_zve32>): Ditto.
(@pred_reduc_plus<order><mode><vlmul1_zve64>): Ditto.
(@pred_reduc_<reduc><VHF:mode><VHF_LMUL1:mode>): New pattern.
(@pred_reduc_<reduc><VSF:mode><VSF_LMUL1:mode>): Ditto.
(@pred_reduc_<reduc><VDF:mode><VDF_LMUL1:mode>): Ditto.
(@pred_reduc_plus<order><VHF:mode><VHF_LMUL1:mode>): Ditto.
(@pred_reduc_plus<order><VSF:mode><VSF_LMUL1:mode>): Ditto.
(@pred_reduc_plus<order><VDF:mode><VDF_LMUL1:mode>): Ditto.
2023-06-19 Andrew Stubbs <ams@codesourcery.com>
* config/gcn/gcn.cc (gcn_expand_divmod_libfunc): New function.
(gcn_init_libfuncs): Add div and mod functions for all modes.
Add placeholders for divmod functions.
(TARGET_EXPAND_DIVMOD_LIBFUNC): Define.
2023-06-19 Andrew Stubbs <ams@codesourcery.com>
* tree-vect-generic.cc: Include optabs-libfuncs.h.
(get_compute_type): Check optab_libfunc.
* tree-vect-stmts.cc: Include optabs-libfuncs.h.
(vectorizable_operation): Check optab_libfunc.
2023-06-19 Andrew Stubbs <ams@codesourcery.com>
* config/gcn/gcn-protos.h (vgpr_4reg_mode_p): New function.
* config/gcn/gcn-valu.md (V_4REG, V_4REG_ALT): New iterators.
(V_MOV, V_MOV_ALT): Likewise.
(scalar_mode, SCALAR_MODE): Add TImode.
(vnsi, VnSI, vndi, VnDI): Likewise.
(vec_merge, vec_merge_with_clobber, vec_merge_with_vcc): Use V_MOV.
(mov<mode>, mov<mode>_unspec): Use V_MOV.
(*mov<mode>_4reg): New insn.
(mov<mode>_exec): New 4reg variant.
(mov<mode>_sgprbase): Likewise.
(reload_in<mode>, reload_out<mode>): Use V_MOV.
(vec_set<mode>): Likewise.
(vec_duplicate<mode><exec>): New 4reg variant.
(vec_extract<mode><scalar_mode>): Likewise.
(vec_extract<V_ALL:mode><V_ALL_ALT:mode>): Rename to ...
(vec_extract<V_MOV:mode><V_MOV_ALT:mode>): ... this, and use V_MOV.
(vec_extract<V_4REG:mode><V_4REG_ALT:mode>_nop): New 4reg variant.
(fold_extract_last_<mode>): Use V_MOV.
(vec_init<V_ALL:mode><V_ALL_ALT:mode>): Rename to ...
(vec_init<V_MOV:mode><V_MOV_ALT:mode>): ... this, and use V_MOV.
(gather_load<mode><vnsi>, gather<mode>_expr<exec>,
gather<mode>_insn_1offset<exec>, gather<mode>_insn_1offset_ds<exec>,
gather<mode>_insn_2offsets<exec>): Use V_MOV.
(scatter_store<mode><vnsi>, scatter<mode>_expr<exec_scatter>,
scatter<mode>_insn_1offset<exec_scatter>,
scatter<mode>_insn_1offset_ds<exec_scatter>,
scatter<mode>_insn_2offsets<exec_scatter>): Likewise.
(maskload<mode>di, maskstore<mode>di, mask_gather_load<mode><vnsi>,
mask_scatter_store<mode><vnsi>): Likewise.
* config/gcn/gcn.cc (gcn_class_max_nregs): Use vgpr_4reg_mode_p.
(gcn_hard_regno_mode_ok): Likewise.
(GEN_VNM): Add TImode support.
(USE_TI): New macro. Separate TImode operations from non-TImode ones.
(gcn_vector_mode_supported_p): Add V64TImode, V32TImode, V16TImode,
V8TImode, and V2TImode.
(print_operand): Add 'J' and 'K' print codes.
2023-06-19 Richard Biener <rguenther@suse.de>
PR tree-optimization/110298
* tree-ssa-loop-ivcanon.cc (tree_unroll_loops_completely):
Clear number of iterations info before cleaning up the CFG.
2023-06-19 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* simplify-rtx.cc (simplify_context::simplify_binary_operation_1):
Simplify vec_concat of lowpart subreg and high part vec_select.
2023-06-19 Tobias Burnus <tobias@codesourcery.com>
* doc/invoke.texi (-foffload-options): Remove '-O3' from the examples.
2023-06-19 Richard Sandiford <richard.sandiford@arm.com>
* tree-vect-loop-manip.cc (vect_set_loop_condition_partial_vectors):
Handle null niters_skip.
2023-06-19 Richard Biener <rguenther@suse.de>
* config/aarch64/aarch64.cc
(aarch64_vector_costs::analyze_loop_vinfo): Fix reference
to LOOP_VINFO_MASKS.
2023-06-19 Senthil Kumar Selvaraj <saaadhu@gcc.gnu.org>
PR target/105523
* common/config/avr/avr-common.cc: Remove setting
of OPT_fdelete_null_pointer_checks.
* config/avr/avr.cc (avr_option_override): Clear
flag_delete_null_pointer_checks if zero_address_valid.
(avr_addr_space_zero_address_valid): New function.
(TARGET_ADDR_SPACE_ZERO_ADDRESS_VALID): Provide target
hook.
2023-06-19 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Robin Dapp <rdapp.gcc@gmail.com>
* doc/md.texi: Add len_mask{load,store}.
* genopinit.cc (main): Ditto.
(CMP_NAME): Ditto.
* internal-fn.cc (len_maskload_direct): Ditto.
(len_maskstore_direct): Ditto.
(expand_call_mem_ref): Ditto.
(expand_partial_load_optab_fn): Ditto.
(expand_len_maskload_optab_fn): Ditto.
(expand_partial_store_optab_fn): Ditto.
(expand_len_maskstore_optab_fn): Ditto.
(direct_len_maskload_optab_supported_p): Ditto.
(direct_len_maskstore_optab_supported_p): Ditto.
* internal-fn.def (LEN_MASK_LOAD): Ditto.
(LEN_MASK_STORE): Ditto.
* optabs.def (OPTAB_CD): Ditto.
2023-06-19 Robin Dapp <rdapp@ventanamicro.com>
* config/riscv/autovec.md (<optab><mode>2): Add unop expanders.
2023-06-19 Robin Dapp <rdapp@ventanamicro.com>
* config/riscv/autovec.md (<optab><mode>3): Implement binop
expander.
* config/riscv/riscv-protos.h (emit_vlmax_fp_insn): Declare.
(enum vxrm_field_enum): Rename this...
(enum fixed_point_rounding_mode): ...to this.
(enum frm_field_enum): Rename this...
(enum floating_point_rounding_mode): ...to this.
* config/riscv/riscv-v.cc (emit_vlmax_fp_insn): New function
* config/riscv/riscv.cc (riscv_const_insns): Clarify const
vector handling.
(riscv_libgcc_floating_mode_supported_p): Adjust comment.
(riscv_excess_precision): Do not convert to float for ZVFH.
* config/riscv/vector-iterators.md: Add VF_AUTO iterator.
2023-06-19 Robin Dapp <rdapp@ventanamicro.com>
* config/riscv/vector-iterators.md: Add VI_QH iterator.
* config/riscv/autovec-opt.md
(@pred_extract_first_sextdi<mode>): New vmv.x.s pattern
that includes sign extension.
(@pred_extract_first_sextsi<mode>): Dito for SImode.
2023-06-19 Robin Dapp <rdapp@ventanamicro.com>
* config/riscv/autovec.md (vec_set<mode>): Implement.
(vec_extract<mode><vel>): Implement.
* config/riscv/riscv-protos.h (enum insn_type): Add slide insn.
(emit_vlmax_slide_insn): Declare.
(emit_nonvlmax_slide_tu_insn): Declare.
(emit_scalar_move_insn): Export.
(emit_nonvlmax_integer_move_insn): Export.
* config/riscv/riscv-v.cc (emit_vlmax_slide_insn): New function.
(emit_nonvlmax_slide_tu_insn): New function.
(emit_vlmax_masked_mu_insn): No change.
(emit_vlmax_integer_move_insn): Export.
2023-06-19 Richard Biener <rguenther@suse.de>
* tree-vectorizer.h (enum vect_partial_vector_style): New.
(_loop_vec_info::partial_vector_style): Likewise.
(LOOP_VINFO_PARTIAL_VECTORS_STYLE): Likewise.
(rgroup_controls::compare_type): Add.
(vec_loop_masks): Change from a typedef to auto_vec<>
to a structure.
* tree-vect-loop-manip.cc (vect_set_loop_condition_partial_vectors):
Adjust. Convert niters_skip to compare_type.
(vect_set_loop_condition_partial_vectors_avx512): New function
implementing the AVX512 partial vector codegen.
(vect_set_loop_condition): Dispatch to the correct
vect_set_loop_condition_partial_vectors_* function based on
LOOP_VINFO_PARTIAL_VECTORS_STYLE.
(vect_prepare_for_masked_peels): Compute LOOP_VINFO_MASK_SKIP_NITERS
in the original niter type.
* tree-vect-loop.cc (_loop_vec_info::_loop_vec_info): Initialize
partial_vector_style.
(can_produce_all_loop_masks_p): Adjust.
(vect_verify_full_masking): Produce the rgroup_controls vector
here. Set LOOP_VINFO_PARTIAL_VECTORS_STYLE on success.
(vect_verify_full_masking_avx512): New function implementing
verification of AVX512 style masking.
(vect_verify_loop_lens): Set LOOP_VINFO_PARTIAL_VECTORS_STYLE.
(vect_analyze_loop_2): Also try AVX512 style masking.
Adjust condition.
(vect_estimate_min_profitable_iters): Implement AVX512 style
mask producing cost.
(vect_record_loop_mask): Do not build the rgroup_controls
vector here but record masks in a hash-set.
(vect_get_loop_mask): Implement AVX512 style mask query,
complementing the existing while_ult style.
2023-06-19 Richard Biener <rguenther@suse.de>
* tree-vectorizer.h (vect_get_loop_mask): Add loop_vec_info
argument.
* tree-vect-loop.cc (vect_get_loop_mask): Likewise.
(vectorize_fold_left_reduction): Adjust.
(vect_transform_reduction): Likewise.
(vectorizable_live_operation): Likewise.
* tree-vect-stmts.cc (vectorizable_call): Likewise.
(vectorizable_operation): Likewise.
(vectorizable_store): Likewise.
(vectorizable_load): Likewise.
(vectorizable_condition): Likewise.
2023-06-19 Senthil Kumar Selvaraj <saaadhu@gcc.gnu.org>
PR target/110086
* config/avr/avr.opt (mgas-isr-prologues, mmain-is-OS_task):
Add Optimization option property.
2023-06-19 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.cc (xtensa_constantsynth_2insn):
Add new pattern for the abovementioned case.
2023-06-19 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.cc
(TARGET_MEMORY_MOVE_COST, xtensa_memory_move_cost): Remove.
2023-06-19 Jiufu Guo <guojiufu@linux.ibm.com>
* config/rs6000/rs6000.cc (TARGET_CONST_ANCHOR): New define.
2023-06-19 Jiufu Guo <guojiufu@linux.ibm.com>
* cse.cc (try_const_anchors): Check SCALAR_INT_MODE.
2023-06-19 liuhongt <hongtao.liu@intel.com>
PR target/110235
* config/i386/sse.md (<sse2_avx2>_packsswb<mask_name>):
Substitute with ..
(sse2_packsswb<mask_name>): .. this, ..
(avx2_packsswb<mask_name>): .. this and ..
(avx512bw_packsswb<mask_name>): .. this.
(<sse2_avx2>_packssdw<mask_name>): Substitute with ..
(sse2_packssdw<mask_name>): .. this, ..
(avx2_packssdw<mask_name>): .. this and ..
(avx512bw_packssdw<mask_name>): .. this.
2023-06-19 liuhongt <hongtao.liu@intel.com>
PR target/110235
* config/i386/i386-expand.cc (ix86_split_mmx_pack): Use
UNSPEC_US_TRUNCATE instead of original us_truncate for
packusdw/packuswb.
* config/i386/mmx.md (mmx_pack<s_trunsuffix>swb): Substitute
with ..
(mmx_packsswb): .. this and ..
(mmx_packuswb): .. this.
(mmx_packusdw): Use UNSPEC_US_TRUNCATE instead of original
us_truncate.
(s_trunsuffix): Removed code iterator.
(any_s_truncate): Ditto.
* config/i386/sse.md (<sse2_avx2>_packuswb<mask_name>): Use
UNSPEC_US_TRUNCATE instead of original us_truncate.
(<sse4_1_avx2>_packusdw<mask_name>): Ditto.
* config/i386/i386.md (UNSPEC_US_TRUNCATE): New unspec_c_enum.
2023-06-18 Pan Li <pan2.li@intel.com>
* config/riscv/riscv-vector-builtins-bases.cc: Fix one typo.
2023-06-18 Uros Bizjak <ubizjak@gmail.com>
* rtl.h (*rtx_equal_p_callback_function):
Change return type from int to bool.
(rtx_equal_p): Ditto.
(*hash_rtx_callback_function): Ditto.
* rtl.cc (rtx_equal_p): Change return type from int to bool
and adjust function body accordingly.
* early-remat.cc (scratch_equal): Ditto.
* sel-sched-ir.cc (skip_unspecs_callback): Ditto.
(hash_with_unspec_callback): Ditto.
2023-06-18 Jeff Law <jlaw@ventanamicro.com>
* config/arc/arc.md (movqi_insn): Allow certain constants to
be stored into memory in the pattern's condition.
(movsf_insn): Similarly.
2023-06-18 Honza <jh@ryzen3.suse.cz>
PR tree-optimization/109849
* ipa-fnsummary.cc (evaluate_conditions_for_known_args): Add new parameter
ES; handle ipa_predicate::not_sra_candidate.
(evaluate_properties_for_edge): Pass es to
evaluate_conditions_for_known_args.
(ipa_fn_summary_t::duplicate): Handle sra candidates.
(dump_ipa_call_summary): Dump points_to_possible_sra_candidate.
(load_or_store_of_ptr_parameter): New function.
(points_to_possible_sra_candidate_p): New function.
(analyze_function_body): Initialize points_to_possible_sra_candidate;
determine sra predicates.
(estimate_ipcp_clone_size_and_time): Update call of
evaluate_conditions_for_known_args.
(remap_edge_params): Update points_to_possible_sra_candidate.
(read_ipa_call_summary): Stream points_to_possible_sra_candidate
(write_ipa_call_summary): Likewise.
* ipa-predicate.cc (ipa_predicate::add_clause): Handle not_sra_candidate.
(dump_condition): Dump it.
* ipa-predicate.h (struct inline_param_summary): Add
points_to_possible_sra_candidate.
2023-06-18 Roger Sayle <roger@nextmovesoftware.com>
* config/i386/i386-expand.cc (ix86_expand_carry): New helper
function for setting the carry flag.
(ix86_expand_builtin) <handlecarry>: Use it here.
* config/i386/i386-protos.h (ix86_expand_carry): Prototype here.
* config/i386/i386.md (uaddc<mode>5): Use ix86_expand_carry.
(usubc<mode>5): Likewise.
2023-06-18 Roger Sayle <roger@nextmovesoftware.com>
* config/i386/i386.md (*concat<mode><dwi>3_1): Use QImode
for the immediate constant shift count.
(*concat<mode><dwi>3_2): Likewise.
(*concat<mode><dwi>3_3): Likewise.
(*concat<mode><dwi>3_4): Likewise.
(*concat<mode><dwi>3_5): Likewise.
(*concat<mode><dwi>3_6): Likewise.
2023-06-18 Uros Bizjak <ubizjak@gmail.com>
* cse.cc (hash_rtx_cb): Rename to hash_rtx.
(hash_rtx): Remove.
* early-remat.cc (remat_candidate_hasher::equal): Update
to call rtx_equal_p with rtx_equal_p_callback_function argument.
* rtl.cc (rtx_equal_p_cb): Rename to rtx_equal_p.
(rtx_equal_p): Remove.
* rtl.h (rtx_equal_p): Add rtx_equal_p_callback_function
argument with NULL default value.
(rtx_equal_p_cb): Remove function declaration.
(hash_rtx_cb): Ditto.
(hash_rtx): Add hash_rtx_callback_function argument
with NULL default value.
* sel-sched-ir.cc (free_nop_pool): Update function comment.
(skip_unspecs_callback): Ditto.
(vinsn_init): Update to call hash_rtx with
hash_rtx_callback_function argument.
(vinsn_equal_p): Ditto.
2023-06-18 yulong <shiyulong@iscas.ac.cn>
* config/riscv/genrvv-type-indexer.cc (valid_type): Enable FP16 tuple.
* config/riscv/riscv-modes.def (RVV_TUPLE_MODES): New macro.
(ADJUST_ALIGNMENT): Ditto.
(RVV_TUPLE_PARTIAL_MODES): Ditto.
(ADJUST_NUNITS): Ditto.
* config/riscv/riscv-vector-builtins-types.def (vfloat16mf4x2_t):
New types.
(vfloat16mf4x3_t): Ditto.
(vfloat16mf4x4_t): Ditto.
(vfloat16mf4x5_t): Ditto.
(vfloat16mf4x6_t): Ditto.
(vfloat16mf4x7_t): Ditto.
(vfloat16mf4x8_t): Ditto.
(vfloat16mf2x2_t): Ditto.
(vfloat16mf2x3_t): Ditto.
(vfloat16mf2x4_t): Ditto.
(vfloat16mf2x5_t): Ditto.
(vfloat16mf2x6_t): Ditto.
(vfloat16mf2x7_t): Ditto.
(vfloat16mf2x8_t): Ditto.
(vfloat16m1x2_t): Ditto.
(vfloat16m1x3_t): Ditto.
(vfloat16m1x4_t): Ditto.
(vfloat16m1x5_t): Ditto.
(vfloat16m1x6_t): Ditto.
(vfloat16m1x7_t): Ditto.
(vfloat16m1x8_t): Ditto.
(vfloat16m2x2_t): Ditto.
(vfloat16m2x3_t): Ditto.
(vfloat16m2x4_t): Ditto.
(vfloat16m4x2_t): Ditto.
* config/riscv/riscv-vector-builtins.def (vfloat16mf4x2_t): New macro.
(vfloat16mf4x3_t): Ditto.
(vfloat16mf4x4_t): Ditto.
(vfloat16mf4x5_t): Ditto.
(vfloat16mf4x6_t): Ditto.
(vfloat16mf4x7_t): Ditto.
(vfloat16mf4x8_t): Ditto.
(vfloat16mf2x2_t): Ditto.
(vfloat16mf2x3_t): Ditto.
(vfloat16mf2x4_t): Ditto.
(vfloat16mf2x5_t): Ditto.
(vfloat16mf2x6_t): Ditto.
(vfloat16mf2x7_t): Ditto.
(vfloat16mf2x8_t): Ditto.
(vfloat16m1x2_t): Ditto.
(vfloat16m1x3_t): Ditto.
(vfloat16m1x4_t): Ditto.
(vfloat16m1x5_t): Ditto.
(vfloat16m1x6_t): Ditto.
(vfloat16m1x7_t): Ditto.
(vfloat16m1x8_t): Ditto.
(vfloat16m2x2_t): Ditto.
(vfloat16m2x3_t): Ditto.
(vfloat16m2x4_t): Ditto.
(vfloat16m4x2_t): Ditto.
* config/riscv/riscv-vector-switch.def (TUPLE_ENTRY): New.
* config/riscv/riscv.md: New.
* config/riscv/vector-iterators.md: New.
2023-06-17 Roger Sayle <roger@nextmovesoftware.com>
* config/i386/i386-expand.cc (ix86_expand_move): Check that OP1 is
CONST_WIDE_INT_P before calling ix86_convert_wide_int_to_broadcast.
Generalize special case for converting TImode to V1TImode to handle
all 128-bit vector conversions.
2023-06-17 Costas Argyris <costas.argyris@gmail.com>
* gcc-ar.cc (main): Refactor to slightly reduce code
duplication. Avoid unnecessary elements in nargv.
2023-06-16 Pan Li <pan2.li@intel.com>
PR target/110265
* config/riscv/riscv-vector-builtins-bases.cc: Add ret_mode for
integer reduction expand.
* config/riscv/vector-iterators.md: Add VQI, VHI, VSI and VDI,
and the LMUL1 attr respectively.
* config/riscv/vector.md
(@pred_reduc_<reduc><mode><vlmul1>): Removed.
(@pred_reduc_<reduc><mode><vlmul1_zve64>): Likewise.
(@pred_reduc_<reduc><mode><vlmul1_zve32>): Likewise.
(@pred_reduc_<reduc><VQI:mode><VQI_LMUL1:mode>): New pattern.
(@pred_reduc_<reduc><VHI:mode><VHI_LMUL1:mode>): Likewise.
(@pred_reduc_<reduc><VSI:mode><VSI_LMUL1:mode>): Likewise.
(@pred_reduc_<reduc><VDI:mode><VDI_LMUL1:mode>): Likewise.
2023-06-16 Juzhe-Zhong <juzhe.zhong@rivai.ai>
PR target/110264
* config/riscv/riscv-vsetvl.cc (insert_vsetvl): Fix bug.
2023-06-16 Jakub Jelinek <jakub@redhat.com>
PR middle-end/79173
* builtin-types.def (BT_FN_UINT_UINT_UINT_UINT_UINTPTR,
BT_FN_ULONG_ULONG_ULONG_ULONG_ULONGPTR,
BT_FN_ULONGLONG_ULONGLONG_ULONGLONG_ULONGLONG_ULONGLONGPTR): New
types.
* builtins.def (BUILT_IN_ADDC, BUILT_IN_ADDCL, BUILT_IN_ADDCLL,
BUILT_IN_SUBC, BUILT_IN_SUBCL, BUILT_IN_SUBCLL): New builtins.
* builtins.cc (fold_builtin_addc_subc): New function.
(fold_builtin_varargs): Handle BUILT_IN_{ADD,SUB}C{,L,LL}.
* doc/extend.texi (__builtin_addc, __builtin_subc): Document.
2023-06-16 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/110271
* tree-ssa-math-opts.cc (math_opts_dom_walker::after_dom_children)
<case PLUS_EXPR>: Ignore return value from match_arith_overflow,
instead call match_uaddc_usubc only if gsi_stmt (gsi) is still stmt.
2023-06-16 Martin Jambor <mjambor@suse.cz>
* configure: Regenerate.
2023-06-16 Roger Sayle <roger@nextmovesoftware.com>
Uros Bizjak <ubizjak@gmail.com>
PR target/31985
* config/i386/i386.md (*add<dwi>3_doubleword_concat): New
define_insn_and_split combine *add<dwi>3_doubleword with
a *concat<mode><dwi>3 for more efficient lowering after reload.
2023-06-16 Vladimir N. Makarov <vmakarov@redhat.com>
* ira-lives.cc: Include except.h.
(process_bb_node_lives): Ignore conflicts from cleanup exceptions
when the pseudo does not live at the exception landing pad.
2023-06-16 Alex Coplan <alex.coplan@arm.com>
* doc/invoke.texi: Document -Welaborated-enum-base.
2023-06-16 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-simd-builtins.def (shrn2_n): Rename builtins to...
(ushrn2_n): ... This.
(sqshrn2_n): Rename builtins to...
(ssqshrn2_n): ... This.
(uqshrn2_n): Rename builtins to...
(uqushrn2_n): ... This.
* config/aarch64/arm_neon.h (vqshrn_high_n_s16): Adjust for the above.
(vqshrn_high_n_s32): Likewise.
(vqshrn_high_n_s64): Likewise.
(vqshrn_high_n_u16): Likewise.
(vqshrn_high_n_u32): Likewise.
(vqshrn_high_n_u64): Likewise.
(vshrn_high_n_s16): Likewise.
(vshrn_high_n_s32): Likewise.
(vshrn_high_n_s64): Likewise.
(vshrn_high_n_u16): Likewise.
(vshrn_high_n_u32): Likewise.
(vshrn_high_n_u64): Likewise.
* config/aarch64/aarch64-simd.md (aarch64_<shrn_op>shrn2_n<mode>_insn_le):
Rename to...
(aarch64_<shrn_op><sra_op>shrn2_n<mode>_insn_le): ... This.
Use SHIFTRT iterator and AARCH64_VALID_SHRN_OP check.
(aarch64_<shrn_op>shrn2_n<mode>_insn_be): Rename to...
(aarch64_<shrn_op><sra_op>shrn2_n<mode>_insn_be): ... This.
Use SHIFTRT iterator and AARCH64_VALID_SHRN_OP check.
(aarch64_<shrn_op>shrn2_n<mode>): Rename to...
(aarch64_<shrn_op><sra_op>shrn2_n<mode>): ... This.
Update expander for the above.
2023-06-16 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-simd-builtins.def (shrn2): Rename builtins to...
(shrn2_n): ... This.
(rshrn2): Rename builtins to...
(rshrn2_n): ... This.
* config/aarch64/arm_neon.h (vrshrn_high_n_s16): Adjust for the above.
(vrshrn_high_n_s32): Likewise.
(vrshrn_high_n_s64): Likewise.
(vrshrn_high_n_u16): Likewise.
(vrshrn_high_n_u32): Likewise.
(vrshrn_high_n_u64): Likewise.
(vshrn_high_n_s16): Likewise.
(vshrn_high_n_s32): Likewise.
(vshrn_high_n_s64): Likewise.
(vshrn_high_n_u16): Likewise.
(vshrn_high_n_u32): Likewise.
(vshrn_high_n_u64): Likewise.
* config/aarch64/aarch64-simd.md (*aarch64_<srn_op>shrn<mode>2_vect_le):
Delete.
(*aarch64_<srn_op>shrn<mode>2_vect_be): Likewise.
(aarch64_shrn2<mode>_insn_le): Likewise.
(aarch64_shrn2<mode>_insn_be): Likewise.
(aarch64_shrn2<mode>): Likewise.
(aarch64_rshrn2<mode>_insn_le): Likewise.
(aarch64_rshrn2<mode>_insn_be): Likewise.
(aarch64_rshrn2<mode>): Likewise.
(aarch64_<sur>q<r>shr<u>n2_n<mode>_insn_le): Likewise.
(aarch64_<shrn_op>shrn2_n<mode>_insn_le): New define_insn.
(aarch64_<sur>q<r>shr<u>n2_n<mode>_insn_be): Delete.
(aarch64_<shrn_op>shrn2_n<mode>_insn_be): New define_insn.
(aarch64_<sur>q<r>shr<u>n2_n<mode>): Delete.
(aarch64_<shrn_op>shrn2_n<mode>): New define_expand.
(aarch64_<shrn_op>rshrn2_n<mode>_insn_le): New define_insn.
(aarch64_<shrn_op>rshrn2_n<mode>_insn_be): New define_insn.
(aarch64_<shrn_op>rshrn2_n<mode>): New define_expand.
(aarch64_sqshrun2_n<mode>_insn_le): New define_insn.
(aarch64_sqshrun2_n<mode>_insn_be): New define_insn.
(aarch64_sqshrun2_n<mode>): New define_expand.
(aarch64_sqrshrun2_n<mode>_insn_le): New define_insn.
(aarch64_sqrshrun2_n<mode>_insn_be): New define_insn.
(aarch64_sqrshrun2_n<mode>): New define_expand.
* config/aarch64/iterators.md (UNSPEC_SQSHRUN, UNSPEC_SQRSHRUN,
UNSPEC_SQSHRN, UNSPEC_UQSHRN, UNSPEC_SQRSHRN, UNSPEC_UQRSHRN):
Delete unspec values.
(VQSHRN_N): Delete int iterator.
2023-06-16 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64.h (AARCH64_VALID_SHRN_OP): Define.
* config/aarch64/aarch64-simd.md
(*aarch64_<shrn_op>shrn_n<mode>_insn<vczle><vczbe>): Rename to...
(*aarch64_<shrn_op><shrn_s>shrn_n<mode>_insn<vczle><vczbe>): ... This.
Use SHIFTRT iterator and add AARCH64_VALID_SHRN_OP to condition.
* config/aarch64/iterators.md (shrn_s): New code attribute.
2023-06-16 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-simd.md (aarch64_<sur>q<r>shr<u>n_n<mode>):
Rename to...
(aarch64_<shrn_op>shrn_n<mode>): ... This. Reimplement with RTL codes.
(*aarch64_<shrn_op>rshrn_n<mode>_insn): New define_insn.
(aarch64_sqrshrun_n<mode>_insn): Likewise.
(aarch64_sqshrun_n<mode>_insn): Likewise.
(aarch64_<shrn_op>rshrn_n<mode>): New define_expand.
(aarch64_sqshrun_n<mode>): Likewise.
(aarch64_sqrshrun_n<mode>): Likewise.
* config/aarch64/iterators.md (V2XWIDE): Add HI and SI modes.
2023-06-16 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-simd-builtins.def (shrn): Rename builtins to...
(shrn_n): ... This.
(rshrn): Rename builtins to...
(rshrn_n): ... This.
* config/aarch64/arm_neon.h (vshrn_n_s16): Adjust for the above.
(vshrn_n_s32): Likewise.
(vshrn_n_s64): Likewise.
(vshrn_n_u16): Likewise.
(vshrn_n_u32): Likewise.
(vshrn_n_u64): Likewise.
(vrshrn_n_s16): Likewise.
(vrshrn_n_s32): Likewise.
(vrshrn_n_s64): Likewise.
(vrshrn_n_u16): Likewise.
(vrshrn_n_u32): Likewise.
(vrshrn_n_u64): Likewise.
* config/aarch64/aarch64-simd.md
(*aarch64_<srn_op>shrn<mode><vczle><vczbe>): Delete.
(aarch64_shrn<mode>): Likewise.
(aarch64_rshrn<mode><vczle><vczbe>_insn): Likewise.
(aarch64_rshrn<mode>): Likewise.
(aarch64_<sur>q<r>shr<u>n_n<mode>_insn<vczle><vczbe>): Likewise.
(aarch64_<sur>q<r>shr<u>n_n<mode>): Likewise.
(*aarch64_<shrn_op>shrn_n<mode>_insn<vczle><vczbe>): New define_insn.
(*aarch64_<shrn_op>rshrn_n<mode>_insn<vczle><vczbe>): Likewise.
(*aarch64_sqshrun_n<mode>_insn<vczle><vczbe>): Likewise.
(*aarch64_sqrshrun_n<mode>_insn<vczle><vczbe>): Likewise.
(aarch64_<shrn_op>shrn_n<mode>): New define_expand.
(aarch64_<shrn_op>rshrn_n<mode>): Likewise.
(aarch64_sqshrun_n<mode>): Likewise.
(aarch64_sqrshrun_n<mode>): Likewise.
* config/aarch64/iterators.md (ALL_TRUNC): New code iterator.
(TRUNCEXTEND): New code attribute.
(TRUNC_SHIFT): Likewise.
(shrn_op): Likewise.
* config/aarch64/predicates.md (aarch64_simd_umax_quarter_mode):
New predicate.
2023-06-16 Pan Li <pan2.li@intel.com>
* config/riscv/riscv-vsetvl.cc
(pass_vsetvl::global_eliminate_vsetvl_insn): Initialize var by NULL.
2023-06-16 Richard Biener <rguenther@suse.de>
PR tree-optimization/110278
* match.pd (uns < (typeof uns)(uns != 0) -> false): New.
(x != (typeof x)(x == 0) -> true): Likewise.
2023-06-16 Pali Rohár <pali@kernel.org>
* config/i386/mingw-w64.h (CPP_SPEC): Adjust for -mcrtdll=.
(REAL_LIBGCC_SPEC): New define.
* config/i386/mingw.opt: Add mcrtdll=
* config/i386/mingw32.h (CPP_SPEC): Adjust for -mcrtdll=.
(REAL_LIBGCC_SPEC): Adjust for -mcrtdll=.
(STARTFILE_SPEC): Adjust for -mcrtdll=.
* doc/invoke.texi: Add mcrtdll= documentation.
2023-06-16 Simon Dardis <simon.dardis@imgtec.com>
* config/mips/mips.cc (enum mips_code_readable_setting):New enmu.
(mips_handle_code_readable_attr):New static function.
(mips_get_code_readable_attr):New static enum function.
(mips_set_current_function):Set the code_readable mode.
(mips_option_override):Same as above.
* doc/extend.texi:Document code_readable.
2023-06-16 Richard Biener <rguenther@suse.de>
PR tree-optimization/110269
* fold-const.cc (fold_binary_loc): Merge x != 0 folding
with tree_expr_nonzero_p ...
* match.pd (cmp (convert? addr@0) integer_zerop): With this
pattern.
2023-06-15 Marek Polacek <polacek@redhat.com>
* Makefile.in: Set LD_PICFLAG. Use it. Set enable_host_pie.
Remove NO_PIE_CFLAGS and NO_PIE_FLAG. Pass LD_PICFLAG to
ALL_LINKERFLAGS. Use the "pic" build of libiberty if --enable-host-pie.
* configure.ac (--enable-host-shared): Don't set PICFLAG here.
(--enable-host-pie): New check. Set PICFLAG and LD_PICFLAG after this
check.
* configure: Regenerate.
* doc/install.texi: Document --enable-host-pie.
2023-06-15 Manolis Tsamis <manolis.tsamis@vrull.eu>
* regcprop.cc (maybe_mode_change): Enable stack pointer
propagation.
2023-06-15 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/110266
* gimple-range-fold.cc (adjust_imagpart_expr): Check for integer
complex type.
(adjust_realpart_expr): Ditto.
2023-06-15 Jan Beulich <jbeulich@suse.com>
* config/i386/sse.md (<avx512>_vec_dup<mode><mask_name>): Use
vmovddup.
2023-06-15 Jan Beulich <jbeulich@suse.com>
* config/i386/constraints.md: Mention k and r for B.
2023-06-15 Lulu Cheng <chenglulu@loongson.cn>
Andrew Pinski <apinski@marvell.com>
PR target/110136
* config/loongarch/loongarch.md: Modify the register constraints for template
"jumptable" and "indirect_jump" from "r" to "e".
2023-06-15 Xi Ruoyao <xry111@xry111.site>
* config/loongarch/loongarch-tune.h (loongarch_align): New
struct.
* config/loongarch/loongarch-def.h (loongarch_cpu_align): New
array.
* config/loongarch/loongarch-def.c (loongarch_cpu_align): Define
the array.
* config/loongarch/loongarch.cc
(loongarch_option_override_internal): Set the value of
-falign-functions= if -falign-functions is enabled but no value
is given. Likewise for -falign-labels=.
2023-06-15 Jakub Jelinek <jakub@redhat.com>
PR middle-end/79173
* internal-fn.def (UADDC, USUBC): New internal functions.
* internal-fn.cc (expand_UADDC, expand_USUBC): New functions.
(commutative_ternary_fn_p): Return true also for IFN_UADDC.
* optabs.def (uaddc5_optab, usubc5_optab): New optabs.
* tree-ssa-math-opts.cc (uaddc_cast, uaddc_ne0, uaddc_is_cplxpart,
match_uaddc_usubc): New functions.
(math_opts_dom_walker::after_dom_children): Call match_uaddc_usubc
for PLUS_EXPR, MINUS_EXPR, BIT_IOR_EXPR and BIT_XOR_EXPR unless
other optimizations have been successful for those.
* gimple-fold.cc (gimple_fold_call): Handle IFN_UADDC and IFN_USUBC.
* fold-const-call.cc (fold_const_call): Likewise.
* gimple-range-fold.cc (adjust_imagpart_expr): Likewise.
* tree-ssa-dce.cc (eliminate_unnecessary_stmts): Likewise.
* doc/md.texi (uaddc<mode>5, usubc<mode>5): Document new named
patterns.
* config/i386/i386.md (uaddc<mode>5, usubc<mode>5): New
define_expand patterns.
(*setcc_qi_addqi3_cconly_overflow_1_<mode>, *setccc): Split
into NOTE_INSN_DELETED note rather than nop instruction.
(*setcc_qi_negqi_ccc_1_<mode>, *setcc_qi_negqi_ccc_2_<mode>):
Likewise.
2023-06-15 Jakub Jelinek <jakub@redhat.com>
PR middle-end/79173
* config/i386/i386.md (subborrow<mode>): Add alternative with
memory destination and add for it define_peephole2
TARGET_READ_MODIFY_WRITE/-Os patterns to prefer using memory
destination in these patterns.
2023-06-15 Jakub Jelinek <jakub@redhat.com>
PR middle-end/79173
* config/i386/i386.md (*sub<mode>_3, @add<mode>3_carry,
addcarry<mode>, @sub<mode>3_carry, *add<mode>3_cc_overflow_1): Add
define_peephole2 TARGET_READ_MODIFY_WRITE/-Os patterns to prefer
using memory destination in these patterns.
2023-06-15 Jakub Jelinek <jakub@redhat.com>
* gimple-fold.cc (gimple_fold_call): Move handling of arg0
as well as arg1 INTEGER_CSTs for .UBSAN_CHECK_{ADD,SUB,MUL}
and .{ADD,SUB,MUL}_OVERFLOW calls from here...
* fold-const-call.cc (fold_const_call): ... here.
2023-06-15 Oluwatamilore Adebayo <oluwatamilore.adebayo@arm.com>
* config/aarch64/aarch64-simd.md (aarch64_<su>abd<mode>):
Rename to <su>abd<mode>3.
* config/aarch64/aarch64-sve.md (<su>abd<mode>_3): Rename
to <su>abd<mode>3.
2023-06-15 Oluwatamilore Adebayo <oluwatamilore.adebayo@arm.com>
* doc/md.texi (sabd, uabd): Document them.
* internal-fn.def (ABD): Use new optab.
* optabs.def (sabd_optab, uabd_optab): New optabs,
* tree-vect-patterns.cc (vect_recog_absolute_difference):
Recognize the following idiom abs (a - b).
(vect_recog_sad_pattern): Refactor to use
vect_recog_absolute_difference.
(vect_recog_abd_pattern): Use patterns found by
vect_recog_absolute_difference to build a new ABD
internal call.
2023-06-15 chenxiaolong <chenxl04200420@163.com>
* config/loongarch/loongarch.h (LARCH_CALL_RATIO): Modify the value
of macro LARCH_CALL_RATIO on LoongArch to make it perform optimally.
2023-06-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-v.cc (shuffle_merge_patterns): New pattern.
(expand_vec_perm_const_1): Add merge optmization.
2023-06-15 Lehua Ding <lehua.ding@rivai.ai>
PR target/110119
* config/riscv/riscv.cc (riscv_get_arg_info): Return NULL_RTX for vector mode
(riscv_pass_by_reference): Return true for vector mode
2023-06-15 Pan Li <pan2.li@intel.com>
* config/riscv/autovec-opt.md: Align the predictor sytle.
* config/riscv/autovec.md: Ditto.
2023-06-15 Pan Li <pan2.li@intel.com>
* config/riscv/riscv-v.cc (rvv_builder::get_merge_scalar_mask):
Take elen instead of scalar BITS_PER_WORD.
(expand_vector_init_merge_repeating_sequence): Use inner_bits_size
instead of scaler BITS_PER_WORD.
2023-06-14 Jivan Hakobyan <jivanhakobyan9@gmail.com>
* config/moxie/uclinux.h (MFWRAP_SPEC): Remove
2023-06-14 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-sve-builtins-base.cc (svlast_impl::fold):
Fix signed comparison warning in loop from npats to enelts.
2023-06-14 Thomas Schwinge <thomas@codesourcery.com>
* gcc.cc (driver_handle_option): Forward host '-lgfortran', '-lm'
to offloading compilation.
* config/gcn/mkoffload.cc (main): Adjust.
* config/nvptx/mkoffload.cc (main): Likewise.
* doc/invoke.texi (foffload-options): Update example.
2023-06-14 liuhongt <hongtao.liu@intel.com>
PR target/110227
* config/i386/sse.md (mov<mode>_internal>): Use x instead of v
for alternative 2 since there's no evex version for vpcmpeqd
ymm, ymm, ymm.
2023-06-13 Jeff Law <jlaw@ventanamicro.com>
* gcc.cc (LINK_COMMAND_SPEC): Remove mudflap spec handling.
2023-06-13 Jeff Law <jlaw@ventanamicro.com>
* config/sh/divtab.cc: Remove.
2023-06-13 Jakub Jelinek <jakub@redhat.com>
* config/i386/i386.cc (standard_sse_constant_opcode): Remove
superfluous spaces around \t for vpcmpeqd.
2023-06-13 Roger Sayle <roger@nextmovesoftware.com>
* expr.cc (store_constructor) <case VECTOR_TYPE>: Don't bother
clearing vectors with only a single element. Set CLEARED if the
vector was initialized to zero.
2023-06-13 Lehua Ding <lehua.ding@rivai.ai>
* config/riscv/riscv-v.cc (struct mode_vtype_group): Remove duplicate
#include.
(ENTRY): Undef.
(TUPLE_ENTRY): Undef.
2023-06-13 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-v.cc (rvv_builder::single_step_npatterns_p): Add comment.
(shuffle_generic_patterns): Ditto.
(expand_vec_perm_const_1): Ditto.
2023-06-13 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-v.cc (emit_vlmax_decompress_insn): Fix bug.
(shuffle_decompress_patterns): Ditto.
2023-06-13 Richard Biener <rguenther@suse.de>
* tree-ssa-loop-ch.cc (ch_base::copy_headers): Free loop BBs.
2023-06-13 Yanzhang Wang <yanzhang.wang@intel.com>
Kito Cheng <kito.cheng@sifive.com>
* config/riscv/riscv-protos.h (riscv_init_cumulative_args): Set
warning flag if func is not builtin
* config/riscv/riscv.cc
(riscv_scalable_vector_type_p): Determine whether the type is scalable vector.
(riscv_arg_has_vector): Determine whether the arg is vector type.
(riscv_pass_in_vector_p): Check the vector type param is passed by value.
(riscv_init_cumulative_args): The same as header.
(riscv_get_arg_info): Add the checking.
(riscv_function_value): Check the func return and set warning flag
* config/riscv/riscv.h (INIT_CUMULATIVE_ARGS): Add a flag to
determine whether warning psabi or not.
2023-06-13 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm-opts.h (enum arm_tp_type): Remove TP_CP15.
Add TP_TPIDRURW, TP_TPIDRURO, TP_TPIDRPRW values.
* config/arm/arm-protos.h (arm_output_load_tpidr): Declare prototype.
* config/arm/arm.cc (arm_option_reconfigure_globals): Replace TP_CP15
with TP_TPIDRURO.
(arm_output_load_tpidr): Define.
* config/arm/arm.h (TARGET_HARD_TP): Define in terms of TARGET_SOFT_TP.
* config/arm/arm.md (load_tp_hard): Call arm_output_load_tpidr to output
assembly.
(reload_tp_hard): Likewise.
* config/arm/arm.opt (tpidrurw, tpidruro, tpidrprw): New values for
arm_tp_type.
* doc/invoke.texi (Arm Options, mtp): Document new values.
2023-06-13 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR target/108779
* config/aarch64/aarch64-opts.h (enum aarch64_tp_reg): Add
AARCH64_TPIDRRO_EL0 value.
* config/aarch64/aarch64.cc (aarch64_output_load_tp): Define.
* config/aarch64/aarch64.opt (tpidr_el0, tpidr_el1, tpidr_el2,
tpidr_el3, tpidrro_el3): New accepted values to -mtp=.
* doc/invoke.texi (AArch64 Options): Document new -mtp= options.
2023-06-13 Alexandre Oliva <oliva@adacore.com>
* range-op-float.cc (frange_nextafter): Drop inline.
(frelop_early_resolve): Add static.
(frange_float): Likewise.
2023-06-13 Richard Biener <rguenther@suse.de>
PR middle-end/110232
* fold-const.cc (native_interpret_vector): Use TYPE_SIZE_UNIT
to check whether the buffer covers the whole vector.
2023-06-13 Richard Biener <rguenther@suse.de>
* tree-ssa-alias.cc (ref_maybe_used_by_call_p_1): For
.MASK_LOAD and friends set the size of the access to unknown.
2023-06-13 Tejas Belagod <tbelagod@arm.com>
PR target/96339
* config/aarch64/aarch64-sve-builtins-base.cc (svlast_impl::fold): Fold sve
calls that have a constant input predicate vector.
(svlast_impl::is_lasta): Query to check if intrinsic is svlasta.
(svlast_impl::is_lastb): Query to check if intrinsic is svlastb.
(svlast_impl::vect_all_same): Check if all vector elements are equal.
2023-06-13 Andi Kleen <ak@linux.intel.com>
* config/i386/gcc-auto-profile: Regenerate.
2023-06-13 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/vector-iterators.md: Fix requirement.
2023-06-13 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-v.cc (emit_vlmax_decompress_insn): New function.
(shuffle_decompress_patterns): New function.
(expand_vec_perm_const_1): Add decompress optimization.
2023-06-12 Jeff Law <jlaw@ventanamicro.com>
PR rtl-optimization/101188
* postreload.cc (reload_cse_move2add_invalidate): New function,
extracted from...
(reload_cse_move2add): Call reload_cse_move2add_invalidate.
2023-06-12 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
* config/aarch64/aarch64.cc (aarch64_expand_vector_init): Tweak condition
if (n_var == n_elts && n_elts <= 16) to allow a single constant,
and if maxv == 1, use constant element for duplicating into register.
2023-06-12 Tobias Burnus <tobias@codesourcery.com>
* gimplify.cc (gimplify_adjust_omp_clauses_1): Use
GOMP_MAP_FORCE_PRESENT for 'present alloc' implicit mapping.
(gimplify_adjust_omp_clauses): Change
GOMP_MAP_PRESENT_{TO,TOFROM,FROM,ALLOC} to the equivalent
GOMP_MAP_FORCE_PRESENT.
* omp-low.cc (lower_omp_target): Remove handling of no-longer valid
GOMP_MAP_PRESENT_{TO,TOFROM,FROM,ALLOC}; update map kinds used for
to/from clauses with present modifier.
2023-06-12 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/110205
* range-op-float.cc (range_operator::fold_range): Add default FII
fold routine.
* range-op-mixed.h (class operator_gt): Add missing final overrides.
* range-op.cc (range_op_handler::fold_range): Add RO_FII case.
(operator_lshift ::update_bitmask): Add final override.
(operator_rshift ::update_bitmask): Add final override.
* range-op.h (range_operator::fold_range): Add FII prototype.
2023-06-12 Andrew MacLeod <amacleod@redhat.com>
* gimple-range-op.cc (gimple_range_op_handler::maybe_non_standard):
Use range_op_handler directly.
* range-op.cc (range_op_handler::range_op_handler): Unsigned
param instead of tree-code.
(ptr_op_widen_plus_signed): Delete.
(ptr_op_widen_plus_unsigned): Delete.
(ptr_op_widen_mult_signed): Delete.
(ptr_op_widen_mult_unsigned): Delete.
(range_op_table::initialize_integral_ops): Add new opcodes.
* range-op.h (range_op_handler): Use unsigned.
(OP_WIDEN_MULT_SIGNED): New.
(OP_WIDEN_MULT_UNSIGNED): New.
(OP_WIDEN_PLUS_SIGNED): New.
(OP_WIDEN_PLUS_UNSIGNED): New.
(RANGE_OP_TABLE_SIZE): New.
(range_op_table::operator []): Use unsigned.
(range_op_table::set): Use unsigned.
(m_range_tree): Make unsigned.
(ptr_op_widen_mult_signed): Remove.
(ptr_op_widen_mult_unsigned): Remove.
(ptr_op_widen_plus_signed): Remove.
(ptr_op_widen_plus_unsigned): Remove.
2023-06-12 Andrew MacLeod <amacleod@redhat.com>
* gimple-range-op.cc (gimple_range_op_handler): Set m_operator
manually as there is no access to the default operator.
(cfn_copysign::fold_range): Don't check for validity.
(cfn_ubsan::fold_range): Ditto.
(gimple_range_op_handler::maybe_builtin_call): Don't set to NULL.
* range-op.cc (default_operator): New.
(range_op_handler::range_op_handler): Use default_operator
instead of NULL.
(range_op_handler::operator bool): Move from header, compare
against default operator.
(range_op_handler::range_op): New.
* range-op.h (range_op_handler::operator bool): Move.
2023-06-12 Andrew MacLeod <amacleod@redhat.com>
* range-op.cc (unified_table): Delete.
(range_op_table operator_table): Instantiate.
(range_op_table::range_op_table): Rename from unified_table.
(range_op_handler::range_op_handler): Use range_op_table.
* range-op.h (range_op_table::operator []): Inline.
(range_op_table::set): Inline.
2023-06-12 Andrew MacLeod <amacleod@redhat.com>
* gimple-range-gori.cc (gori_compute::condexpr_adjust): Do not
pass type.
* gimple-range-op.cc (get_code): Rename from get_code_and_type
and simplify.
(gimple_range_op_handler::supported_p): No need for type.
(gimple_range_op_handler::gimple_range_op_handler): Ditto.
(cfn_copysign::fold_range): Ditto.
(cfn_ubsan::fold_range): Ditto.
* ipa-cp.cc (ipa_vr_operation_and_type_effects): Ditto.
* ipa-fnsummary.cc (evaluate_conditions_for_known_args): Ditto.
* range-op-float.cc (operator_plus::op1_range): Ditto.
(operator_mult::op1_range): Ditto.
(range_op_float_tests): Ditto.
* range-op.cc (get_op_handler): Remove.
(range_op_handler::set_op_handler): Remove.
(operator_plus::op1_range): No need for type.
(operator_minus::op1_range): Ditto.
(operator_mult::op1_range): Ditto.
(operator_exact_divide::op1_range): Ditto.
(operator_cast::op1_range): Ditto.
(perator_bitwise_not::fold_range): Ditto.
(operator_negate::fold_range): Ditto.
* range-op.h (range_op_handler::range_op_handler): Remove type param.
(range_cast): No need for type.
(range_op_table::operator[]): Check for enum_code >= 0.
* tree-data-ref.cc (compute_distributive_range): No need for type.
* tree-ssa-loop-unswitch.cc (unswitch_predicate): Ditto.
* value-query.cc (range_query::get_tree_range): Ditto.
* value-relation.cc (relation_oracle::validate_relation): Ditto.
* vr-values.cc (range_of_var_in_loop): Ditto.
(simplify_using_ranges::fold_cond_with_ops): Ditto.
2023-06-12 Andrew MacLeod <amacleod@redhat.com>
* range-op-mixed.h (operator_max): Remove final.
* range-op-ptr.cc (pointer_table::pointer_table): Remove MAX_EXPR.
(pointer_table::pointer_table): Remove.
(class hybrid_max_operator): New.
(range_op_table::initialize_pointer_ops): Add hybrid_max_operator.
* range-op.cc (pointer_tree_table): Remove.
(unified_table::unified_table): Comment out MAX_EXPR.
(get_op_handler): Remove check of pointer table.
* range-op.h (class pointer_table): Remove.
2023-06-12 Andrew MacLeod <amacleod@redhat.com>
* range-op-mixed.h (operator_min): Remove final.
* range-op-ptr.cc (pointer_table::pointer_table): Remove MIN_EXPR.
(class hybrid_min_operator): New.
(range_op_table::initialize_pointer_ops): Add hybrid_min_operator.
* range-op.cc (unified_table::unified_table): Comment out MIN_EXPR.
2023-06-12 Andrew MacLeod <amacleod@redhat.com>
* range-op-mixed.h (operator_bitwise_or): Remove final.
* range-op-ptr.cc (pointer_table::pointer_table): Remove BIT_IOR_EXPR.
(class hybrid_or_operator): New.
(range_op_table::initialize_pointer_ops): Add hybrid_or_operator.
* range-op.cc (unified_table::unified_table): Comment out BIT_IOR_EXPR.
2023-06-12 Andrew MacLeod <amacleod@redhat.com>
* range-op-mixed.h (operator_bitwise_and): Remove final.
* range-op-ptr.cc (pointer_table::pointer_table): Remove BIT_AND_EXPR.
(class hybrid_and_operator): New.
(range_op_table::initialize_pointer_ops): Add hybrid_and_operator.
* range-op.cc (unified_table::unified_table): Comment out BIT_AND_EXPR.
2023-06-12 Andrew MacLeod <amacleod@redhat.com>
* Makefile.in (OBJS): Add range-op-ptr.o.
* range-op-mixed.h (update_known_bitmask): Move prototype here.
(minus_op1_op2_relation_effect): Move prototype here.
(wi_includes_zero_p): Move function to here.
(wi_zero_p): Ditto.
* range-op.cc (update_known_bitmask): Remove static.
(wi_includes_zero_p): Move to header.
(wi_zero_p): Move to header.
(minus_op1_op2_relation_effect): Remove static.
(operator_pointer_diff): Move class and routines to range-op-ptr.cc.
(pointer_plus_operator): Ditto.
(pointer_min_max_operator): Ditto.
(pointer_and_operator): Ditto.
(pointer_or_operator): Ditto.
(pointer_table): Ditto.
(range_op_table::initialize_pointer_ops): Ditto.
* range-op-ptr.cc: New.
2023-06-12 Andrew MacLeod <amacleod@redhat.com>
* range-op-mixed.h (class operator_max): Move from...
* range-op.cc (unified_table::unified_table): Add MAX_EXPR.
(get_op_handler): Remove the integral table.
(class operator_max): Move from here.
(integral_table::integral_table): Delete.
* range-op.h (class integral_table): Delete.
2023-06-12 Andrew MacLeod <amacleod@redhat.com>
* range-op-mixed.h (class operator_min): Move from...
* range-op.cc (unified_table::unified_table): Add MIN_EXPR.
(class operator_min): Move from here.
(integral_table::integral_table): Remove MIN_EXPR.
2023-06-12 Andrew MacLeod <amacleod@redhat.com>
* range-op-mixed.h (class operator_bitwise_or): Move from...
* range-op.cc (unified_table::unified_table): Add BIT_IOR_EXPR.
(class operator_bitwise_or): Move from here.
(integral_table::integral_table): Remove BIT_IOR_EXPR.
2023-06-12 Andrew MacLeod <amacleod@redhat.com>
* range-op-mixed.h (class operator_bitwise_and): Move from...
* range-op.cc (unified_table::unified_table): Add BIT_AND_EXPR.
(get_op_handler): Check for a pointer table entry first.
(class operator_bitwise_and): Move from here.
(integral_table::integral_table): Remove BIT_AND_EXPR.
2023-06-12 Andrew MacLeod <amacleod@redhat.com>
* range-op-mixed.h (class operator_bitwise_xor): Move from...
* range-op.cc (unified_table::unified_table): Add BIT_XOR_EXPR.
(class operator_bitwise_xor): Move from here.
(integral_table::integral_table): Remove BIT_XOR_EXPR.
(pointer_table::pointer_table): Remove BIT_XOR_EXPR.
2023-06-12 Andrew MacLeod <amacleod@redhat.com>
* range-op-mixed.h (class operator_bitwise_not): Move from...
* range-op.cc (unified_table::unified_table): Add BIT_NOT_EXPR.
(class operator_bitwise_not): Move from here.
(integral_table::integral_table): Remove BIT_NOT_EXPR.
(pointer_table::pointer_table): Remove BIT_NOT_EXPR.
2023-06-12 Andrew MacLeod <amacleod@redhat.com>
* range-op-mixed.h (class operator_addr_expr): Move from...
* range-op.cc (unified_table::unified_table): Add ADDR_EXPR.
(class operator_addr_expr): Move from here.
(integral_table::integral_table): Remove ADDR_EXPR.
(pointer_table::pointer_table): Remove ADDR_EXPR.
2023-06-12 Pan Li <pan2.li@intel.com>
* config/riscv/riscv-vector-builtins-types.def
(vfloat16m1_t): Add type to lmul1 ops.
(vfloat16m2_t): Likewise.
(vfloat16m4_t): Likewise.
2023-06-12 Richard Biener <rguenther@suse.de>
* tree-ssa-alias.cc (call_may_clobber_ref_p_1): For
.MASK_STORE and friend set the size of the access to
unknown.
2023-06-12 Tamar Christina <tamar.christina@arm.com>
* config.in: Regenerate.
* configure: Regenerate.
* configure.ac: Remove DEFAULT_MATCHPD_PARTITIONS.
2023-06-12 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/autovec-opt.md
(*v<any_shiftrt:optab><any_extend:optab>trunc<mode>): New pattern.
(*<any_shiftrt:optab>trunc<mode>): Ditto.
* config/riscv/autovec.md (<optab><mode>3): Change to
define_insn_and_split.
(v<optab><mode>3): Ditto.
(trunc<mode><v_double_trunc>2): Ditto.
2023-06-12 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* simplify-rtx.cc (simplify_const_unary_operation):
Handle US_TRUNCATE, SS_TRUNCATE.
2023-06-12 Eric Botcazou <ebotcazou@adacore.com>
PR modula2/109952
* doc/gm2.texi (Standard procedures): Fix Next link.
2023-06-12 Tamar Christina <tamar.christina@arm.com>
* config.in: Regenerate.
2023-06-12 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR middle-end/110142
* tree-vect-patterns.cc (vect_recog_widen_op_pattern): Don't pass
subtype to vect_widened_op_tree and remove subtype parameter, also
remove superfluous overloaded function definition.
(vect_recog_widen_plus_pattern): Remove subtype parameter and dont pass
to call to vect_recog_widen_op_pattern.
(vect_recog_widen_minus_pattern): Likewise.
2023-06-12 liuhongt <hongtao.liu@intel.com>
* config/i386/sse.md (vec_pack<floatprefix>_float_<mode>): New expander.
(vec_unpack_<fixprefix>fix_trunc_lo_<mode>): Ditto.
(vec_unpack_<fixprefix>fix_trunc_hi_<mode>): Ditto.
(vec_unpacks_lo_<mode>): Ditto.
(vec_unpacks_hi_<mode>): Ditto.
(sse_movlhps_<mode>): New define_insn.
(ssse3_palignr<mode>_perm): Extend to V_128H.
(V_128H): New mode iterator.
(ssepackPHmode): New mode attribute.
(vunpck_extract_mode): Ditto.
(vpckfloat_concat_mode): Extend to VxSI/VxSF for _Float16.
(vpckfloat_temp_mode): Ditto.
(vpckfloat_op_mode): Ditto.
(vunpckfixt_mode): Extend to VxHF.
(vunpckfixt_model): Ditto.
(vunpckfixt_extract_mode): Ditto.
2023-06-12 Richard Biener <rguenther@suse.de>
PR middle-end/110200
* genmatch.cc (expr::gen_transform): Put braces around
the if arm for the (convert ...) short-cut.
2023-06-12 Kewen Lin <linkw@linux.ibm.com>
PR target/109932
* config/rs6000/rs6000-builtins.def (__builtin_pack_vector_int128,
__builtin_unpack_vector_int128): Move from stanza power7 to vsx.
2023-06-12 Kewen Lin <linkw@linux.ibm.com>
PR target/110011
* config/rs6000/rs6000.cc (output_toc): Use the mode of the 128-bit
floating constant itself for real_to_target call.
2023-06-12 Pan Li <pan2.li@intel.com>
* config/riscv/riscv-vector-builtins-types.def
(vfloat16mf4_t): Add type to X2/X4/X8/X16/X32 vlmul ext ops.
(vfloat16mf2_t): Ditto.
(vfloat16m1_t): Ditto.
(vfloat16m2_t): Ditto.
(vfloat16m4_t): Ditto.
2023-06-12 David Edelsohn <dje.gcc@gmail.com>
* config/rs6000/rs6000-logue.cc (rs6000_stack_info):
Do not require a stack frame when debugging is enabled for AIX.
2023-06-11 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr.md (adjust_len) [insv_notbit_0, insv_notbit_7]:
Remove attribute values.
(insv_notbit): New post-reload insn.
(*insv.not-shiftrt_split, *insv.xor1-bit.0_split)
(*insv.not-bit.0_split, *insv.not-bit.7_split)
(*insv.xor-extract_split): Split to insv_notbit.
(*insv.not-shiftrt, *insv.xor1-bit.0, *insv.not-bit.0, *insv.not-bit.7)
(*insv.xor-extract): Remove post-reload insns.
* config/avr/avr.cc (avr_out_insert_notbit) [bitno]: Remove parameter.
(avr_adjust_insn_length): Adjust call of avr_out_insert_notbit.
[ADJUST_LEN_INSV_NOTBIT_0, ADJUST_LEN_INSV_NOTBIT_7]: Remove cases.
* config/avr/avr-protos.h (avr_out_insert_notbit): Adjust prototype.
2023-06-11 Georg-Johann Lay <avr@gjlay.de>
PR target/109907
* config/avr/avr.md (adjust_len) [extr, extr_not]: New elements.
(MSB, SIZE): New mode attributes.
(any_shift): New code iterator.
(*lshr<mode>3_split, *lshr<mode>3, lshr<mode>3)
(*lshr<mode>3_const_split): Add constraint alternative for
the case of shift-offset = MSB. Ditch "length" attribute.
(extzv<mode): New. replaces extzv. Adjust following patterns.
Use avr_out_extr, avr_out_extr_not to print asm.
(*extzv.subreg.<mode>, *extzv.<mode>.subreg, *extzv.xor)
(*extzv<mode>.ge, *neg.ashiftrt<mode>.msb, *extzv.io.lsr7): New.
* config/avr/constraints.md (C15, C23, C31, Yil): New
* config/avr/predicates.md (reg_or_low_io_operand)
(const7_operand, reg_or_low_io_operand)
(const15_operand, const_0_to_15_operand)
(const23_operand, const_0_to_23_operand)
(const31_operand, const_0_to_31_operand): New.
* config/avr/avr-protos.h (avr_out_extr, avr_out_extr_not): New.
* config/avr/avr.cc (avr_out_extr, avr_out_extr_not): New funcs.
(lshrqi3_out, lshrhi3_out, lshrpsi3_out, lshrsi3_out): Adjust
MSB case to new insn constraint "r" for operands[1].
(avr_adjust_insn_length) [ADJUST_LEN_EXTR_NOT, ADJUST_LEN_EXTR]:
Handle these cases.
(avr_rtx_costs_1): Adjust cost for a new pattern.
2023-06-11 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vsetvl.cc (available_occurrence_p): Enhance user vsetvl optimization.
(vector_insn_info::parse_insn): Add rtx_insn parse.
(pass_vsetvl::local_eliminate_vsetvl_insn): Enhance user vsetvl optimization.
(get_first_vsetvl): New function.
(pass_vsetvl::global_eliminate_vsetvl_insn): Ditto.
(pass_vsetvl::cleanup_insns): Remove it.
(pass_vsetvl::ssa_post_optimization): New function.
(has_no_uses): Ditto.
(pass_vsetvl::propagate_avl): Remove it.
(pass_vsetvl::df_post_optimization): New function.
(pass_vsetvl::lazy_vsetvl): Rework Phase 5 && Phase 6.
* config/riscv/riscv-vsetvl.h: Adapt declaration.
2023-06-10 Aldy Hernandez <aldyh@redhat.com>
* ipa-cp.cc (ipcp_vr_lattice::init): Take type argument.
(ipcp_vr_lattice::print): Call dump method.
(ipcp_vr_lattice::meet_with): Adjust for m_vr being a
Value_Range.
(ipcp_vr_lattice::meet_with_1): Make argument a reference.
(ipcp_vr_lattice::set_to_bottom): Set varying for an unsupported
range.
(initialize_node_lattices): Pass type when appropriate.
(ipa_vr_operation_and_type_effects): Make type agnostic.
(ipa_value_range_from_jfunc): Same.
(propagate_vr_across_jump_function): Same.
* ipa-fnsummary.cc (evaluate_conditions_for_known_args): Same.
(evaluate_properties_for_edge): Same.
* ipa-prop.cc (ipa_vr::get_vrange): Same.
(ipcp_update_vr): Same.
* ipa-prop.h (ipa_value_range_from_jfunc): Same.
(ipa_range_set_and_normalize): Same.
2023-06-10 Georg-Johann Lay <avr@gjlay.de>
PR target/109650
PR target/92729
* config/avr/avr-passes.def (avr_pass_ifelse): Insert new pass.
* config/avr/avr.cc (avr_pass_ifelse): New RTL pass.
(avr_pass_data_ifelse): New pass_data for it.
(make_avr_pass_ifelse, avr_redundant_compare, avr_cbranch_cost)
(avr_canonicalize_comparison, avr_out_plus_set_ZN)
(avr_out_cmp_ext): New functions.
(compare_condtition): Make sure REG_CC dies in the branch insn.
(avr_rtx_costs_1): Add computation of cbranch costs.
(avr_adjust_insn_length) [ADJUST_LEN_ADD_SET_ZN, ADJUST_LEN_CMP_ZEXT]:
[ADJUST_LEN_CMP_SEXT]Handle them.
(TARGET_CANONICALIZE_COMPARISON): New define.
(avr_simplify_comparison_p, compare_diff_p, avr_compare_pattern)
(avr_reorg_remove_redundant_compare, avr_reorg): Remove functions.
(TARGET_MACHINE_DEPENDENT_REORG): Remove define.
* config/avr/avr-protos.h (avr_simplify_comparison_p): Remove proto.
(make_avr_pass_ifelse, avr_out_plus_set_ZN, cc_reg_rtx)
(avr_out_cmp_zext): New Protos
* config/avr/avr.md (branch, difficult_branch): Don't split insns.
(*cbranchhi.zero-extend.0", *cbranchhi.zero-extend.1")
(*swapped_tst<mode>, *add.for.eqne.<mode>): New insns.
(*cbranch<mode>4): Rename to cbranch<mode>4_insn.
(define_peephole): Add dead_or_set_regno_p(insn,REG_CC) as needed.
(define_deephole2): Add peep2_regno_dead_p(*,REG_CC) as needed.
Add new RTL peepholes for decrement-and-branch and *swapped_tst<mode>.
Rework signtest-and-branch peepholes for *sbrx_branch<mode>.
(adjust_len) [add_set_ZN, cmp_zext]: New.
(QIPSI): New mode iterator.
(ALLs1, ALLs2, ALLs4, ALLs234): New mode iterators.
(gelt): New code iterator.
(gelt_eqne): New code attribute.
(rvbranch, *rvbranch, difficult_rvbranch, *difficult_rvbranch)
(branch_unspec, *negated_tst<mode>, *reversed_tst<mode>)
(*cmpqi_sign_extend): Remove insns.
(define_c_enum "unspec") [UNSPEC_IDENTITY]: Remove.
* config/avr/avr-dimode.md (cbranch<mode>4): Canonicalize comparisons.
* config/avr/predicates.md (scratch_or_d_register_operand): New.
* config/avr/constraints.md (Yxx): New constraint.
2023-06-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/autovec.md (select_vl<mode>): New pattern.
* config/riscv/riscv-protos.h (expand_select_vl): New function.
* config/riscv/riscv-v.cc (expand_select_vl): Ditto.
2023-06-10 Andrew MacLeod <amacleod@redhat.com>
* range-op-float.cc (foperator_mult_div_base): Delete.
(foperator_mult_div_base::find_range): Make static local function.
(foperator_mult): Remove. Move prototypes to range-op-mixed.h
(operator_mult::op1_range): Rename from foperator_mult.
(operator_mult::op2_range): Ditto.
(operator_mult::rv_fold): Ditto.
(float_table::float_table): Remove MULT_EXPR.
(class foperator_div): Inherit from range_operator.
(float_table::float_table): Delete.
* range-op-mixed.h (class operator_mult): Combined from integer
and float files.
* range-op.cc (float_tree_table): Delete.
(op_mult): New object.
(unified_table::unified_table): Add MULT_EXPR.
(get_op_handler): Do not check float table any longer.
(class cross_product_operator): Move to range-op-mixed.h.
(class operator_mult): Move to range-op-mixed.h.
(integral_table::integral_table): Remove MULT_EXPR.
(pointer_table::pointer_table): Remove MULT_EXPR.
* range-op.h (float_table): Remove.
2023-06-10 Andrew MacLeod <amacleod@redhat.com>
* range-op-float.cc (foperator_negate): Remove. Move prototypes
to range-op-mixed.h
(operator_negate::fold_range): Rename from foperator_negate.
(operator_negate::op1_range): Ditto.
(float_table::float_table): Remove NEGATE_EXPR.
* range-op-mixed.h (class operator_negate): Combined from integer
and float files.
* range-op.cc (op_negate): New object.
(unified_table::unified_table): Add NEGATE_EXPR.
(class operator_negate): Move to range-op-mixed.h.
(integral_table::integral_table): Remove NEGATE_EXPR.
(pointer_table::pointer_table): Remove NEGATE_EXPR.
2023-06-10 Andrew MacLeod <amacleod@redhat.com>
* range-op-float.cc (foperator_minus): Remove. Move prototypes
to range-op-mixed.h
(operator_minus::fold_range): Rename from foperator_minus.
(operator_minus::op1_range): Ditto.
(operator_minus::op2_range): Ditto.
(operator_minus::rv_fold): Ditto.
(float_table::float_table): Remove MINUS_EXPR.
* range-op-mixed.h (class operator_minus): Combined from integer
and float files.
* range-op.cc (op_minus): New object.
(unified_table::unified_table): Add MINUS_EXPR.
(class operator_minus): Move to range-op-mixed.h.
(integral_table::integral_table): Remove MINUS_EXPR.
(pointer_table::pointer_table): Remove MINUS_EXPR.
2023-06-10 Andrew MacLeod <amacleod@redhat.com>
* range-op-float.cc (foperator_abs): Remove. Move prototypes
to range-op-mixed.h
(operator_abs::fold_range): Rename from foperator_abs.
(operator_abs::op1_range): Ditto.
(float_table::float_table): Remove ABS_EXPR.
* range-op-mixed.h (class operator_abs): Combined from integer
and float files.
* range-op.cc (op_abs): New object.
(unified_table::unified_table): Add ABS_EXPR.
(class operator_abs): Move to range-op-mixed.h.
(integral_table::integral_table): Remove ABS_EXPR.
(pointer_table::pointer_table): Remove ABS_EXPR.
2023-06-10 Andrew MacLeod <amacleod@redhat.com>
* range-op-float.cc (foperator_plus): Remove. Move prototypes
to range-op-mixed.h
(operator_plus::fold_range): Rename from foperator_plus.
(operator_plus::op1_range): Ditto.
(operator_plus::op2_range): Ditto.
(operator_plus::rv_fold): Ditto.
(float_table::float_table): Remove PLUS_EXPR.
* range-op-mixed.h (class operator_plus): Combined from integer
and float files.
* range-op.cc (op_plus): New object.
(unified_table::unified_table): Add PLUS_EXPR.
(class operator_plus): Move to range-op-mixed.h.
(integral_table::integral_table): Remove PLUS_EXPR.
(pointer_table::pointer_table): Remove PLUS_EXPR.
2023-06-10 Andrew MacLeod <amacleod@redhat.com>
* range-op-mixed.h (class operator_cast): Combined from integer
and float files.
* range-op.cc (op_cast): New object.
(unified_table::unified_table): Add op_cast
(class operator_cast): Move to range-op-mixed.h.
(integral_table::integral_table): Remove op_cast
(pointer_table::pointer_table): Remove op_cast.
2023-06-10 Andrew MacLeod <amacleod@redhat.com>
* range-op-float.cc (operator_cst::fold_range): New.
* range-op-mixed.h (class operator_cst): Move from integer file.
* range-op.cc (op_cst): New object.
(unified_table::unified_table): Add op_cst. Also use for REAL_CST.
(class operator_cst): Move to range-op-mixed.h.
(integral_table::integral_table): Remove op_cst.
(pointer_table::pointer_table): Remove op_cst.
2023-06-10 Andrew MacLeod <amacleod@redhat.com>
* range-op-float.cc (foperator_identity): Remove. Move prototypes
to range-op-mixed.h
(operator_identity::fold_range): Rename from foperator_identity.
(operator_identity::op1_range): Ditto.
(float_table::float_table): Remove fop_identity.
* range-op-mixed.h (class operator_identity): Combined from integer
and float files.
* range-op.cc (op_identity): New object.
(unified_table::unified_table): Add op_identity.
(class operator_identity): Move to range-op-mixed.h.
(integral_table::integral_table): Remove identity.
(pointer_table::pointer_table): Remove identity.
2023-06-10 Andrew MacLeod <amacleod@redhat.com>
* range-op-float.cc (foperator_ge): Remove. Move prototypes
to range-op-mixed.h
(operator_ge::fold_range): Rename from foperator_ge.
(operator_ge::op1_range): Ditto.
(float_table::float_table): Remove GE_EXPR.
* range-op-mixed.h (class operator_ge): Combined from integer
and float files.
* range-op.cc (op_ge): New object.
(unified_table::unified_table): Add GE_EXPR.
(class operator_ge): Move to range-op-mixed.h.
(ge_op1_op2_relation): Fold into
operator_ge::op1_op2_relation.
(integral_table::integral_table): Remove GE_EXPR.
(pointer_table::pointer_table): Remove GE_EXPR.
* range-op.h (ge_op1_op2_relation): Delete.
2023-06-10 Andrew MacLeod <amacleod@redhat.com>
* range-op-float.cc (foperator_gt): Remove. Move prototypes
to range-op-mixed.h
(operator_gt::fold_range): Rename from foperator_gt.
(operator_gt::op1_range): Ditto.
(float_table::float_table): Remove GT_EXPR.
* range-op-mixed.h (class operator_gt): Combined from integer
and float files.
* range-op.cc (op_gt): New object.
(unified_table::unified_table): Add GT_EXPR.
(class operator_gt): Move to range-op-mixed.h.
(gt_op1_op2_relation): Fold into
operator_gt::op1_op2_relation.
(integral_table::integral_table): Remove GT_EXPR.
(pointer_table::pointer_table): Remove GT_EXPR.
* range-op.h (gt_op1_op2_relation): Delete.
2023-06-10 Andrew MacLeod <amacleod@redhat.com>
* range-op-float.cc (foperator_le): Remove. Move prototypes
to range-op-mixed.h
(operator_le::fold_range): Rename from foperator_le.
(operator_le::op1_range): Ditto.
(float_table::float_table): Remove LE_EXPR.
* range-op-mixed.h (class operator_le): Combined from integer
and float files.
* range-op.cc (op_le): New object.
(unified_table::unified_table): Add LE_EXPR.
(class operator_le): Move to range-op-mixed.h.
(le_op1_op2_relation): Fold into
operator_le::op1_op2_relation.
(integral_table::integral_table): Remove LE_EXPR.
(pointer_table::pointer_table): Remove LE_EXPR.
* range-op.h (le_op1_op2_relation): Delete.
2023-06-10 Andrew MacLeod <amacleod@redhat.com>
* range-op-float.cc (foperator_lt): Remove. Move prototypes
to range-op-mixed.h
(operator_lt::fold_range): Rename from foperator_lt.
(operator_lt::op1_range): Ditto.
(float_table::float_table): Remove LT_EXPR.
* range-op-mixed.h (class operator_lt): Combined from integer
and float files.
* range-op.cc (op_lt): New object.
(unified_table::unified_table): Add LT_EXPR.
(class operator_lt): Move to range-op-mixed.h.
(lt_op1_op2_relation): Fold into
operator_lt::op1_op2_relation.
(integral_table::integral_table): Remove LT_EXPR.
(pointer_table::pointer_table): Remove LT_EXPR.
* range-op.h (lt_op1_op2_relation): Delete.
2023-06-10 Andrew MacLeod <amacleod@redhat.com>
* range-op-float.cc (foperator_not_equal): Remove. Move prototypes
to range-op-mixed.h
(operator_equal::fold_range): Rename from foperator_not_equal.
(operator_equal::op1_range): Ditto.
(float_table::float_table): Remove NE_EXPR.
* range-op-mixed.h (class operator_not_equal): Combined from integer
and float files.
* range-op.cc (op_equal): New object.
(unified_table::unified_table): Add NE_EXPR.
(class operator_not_equal): Move to range-op-mixed.h.
(not_equal_op1_op2_relation): Fold into
operator_not_equal::op1_op2_relation.
(integral_table::integral_table): Remove NE_EXPR.
(pointer_table::pointer_table): Remove NE_EXPR.
* range-op.h (not_equal_op1_op2_relation): Delete.
2023-06-10 Andrew MacLeod <amacleod@redhat.com>
* range-op-float.cc (foperator_equal): Remove. Move prototypes
to range-op-mixed.h
(operator_equal::fold_range): Rename from foperator_equal.
(operator_equal::op1_range): Ditto.
(float_table::float_table): Remove EQ_EXPR.
* range-op-mixed.h (class operator_equal): Combined from integer
and float files.
* range-op.cc (op_equal): New object.
(unified_table::unified_table): Add EQ_EXPR.
(class operator_equal): Move to range-op-mixed.h.
(equal_op1_op2_relation): Fold into
operator_equal::op1_op2_relation.
(integral_table::integral_table): Remove EQ_EXPR.
(pointer_table::pointer_table): Remove EQ_EXPR.
* range-op.h (equal_op1_op2_relation): Delete.
2023-06-10 Andrew MacLeod <amacleod@redhat.com>
* range-op-float.cc (class float_table): Move to header.
(float_table::float_table): Move float only operators to...
(range_op_table::initialize_float_ops): Here.
* range-op-mixed.h: New.
* range-op.cc (integral_tree_table, pointer_tree_table): Moved
to top of file.
(float_tree_table): Moved from range-op-float.cc.
(unified_tree_table): New.
(unified_table::unified_table): New. Call initialize routines.
(get_op_handler): Check unified table first.
(range_op_handler::range_op_handler): Handle no type constructor.
(integral_table::integral_table): Move integral only operators to...
(range_op_table::initialize_integral_ops): Here.
(pointer_table::pointer_table): Move pointer only operators to...
(range_op_table::initialize_pointer_ops): Here.
* range-op.h (enum bool_range_state): Move to range-op-mixed.h.
(get_bool_state): Ditto.
(empty_range_varying): Ditto.
(relop_early_resolve): Ditto.
(class range_op_table): Add new init methods for range types.
(class integral_table): Move declaration to here.
(class pointer_table): Move declaration to here.
(class float_table): Move declaration to here.
2023-06-09 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Richard Sandiford <richard.sandiford@arm.com>
Richard Biener <rguenther@suse.de>
* doc/md.texi: Add SELECT_VL support.
* internal-fn.def (SELECT_VL): Ditto.
* optabs.def (OPTAB_D): Ditto.
* tree-vect-loop-manip.cc (vect_set_loop_controls_directly): Ditto.
* tree-vect-loop.cc (_loop_vec_info::_loop_vec_info): Ditto.
* tree-vect-stmts.cc (get_select_vl_data_ref_ptr): Ditto.
(vectorizable_store): Ditto.
(vectorizable_load): Ditto.
* tree-vectorizer.h (LOOP_VINFO_USING_SELECT_VL_P): Ditto.
2023-06-09 Andrew MacLeod <amacleod@redhat.com>
PR ipa/109886
* ipa-prop.cc (ipa_compute_jump_functions_for_edge): Check param
type as well.
2023-06-09 Andrew MacLeod <amacleod@redhat.com>
* range-op.cc (range_cast): Move to...
* range-op.h (range_cast): Here and add generic a version.
2023-06-09 Marek Polacek <polacek@redhat.com>
PR c/39589
PR c++/96868
* doc/invoke.texi: Clarify that -Wmissing-field-initializers doesn't
warn about designated initializers in C only.
2023-06-09 Andrew Pinski <apinski@marvell.com>
PR tree-optimization/97711
PR tree-optimization/110155
* match.pd ((zero_one == 0) ? y : z <op> y): Add plus to the op.
((zero_one != 0) ? z <op> y : y): Likewise.
2023-06-09 Andrew Pinski <apinski@marvell.com>
* match.pd ((zero_one ==/!= 0) ? y : z <op> y): Use
multiply rather than negation/bit_and.
2023-06-09 Andrew Pinski <apinski@marvell.com>
* match.pd (`X & -Y -> X * Y`): Allow for truncation
and the same type for unsigned types.
2023-06-09 Andrew Pinski <apinski@marvell.com>
PR tree-optimization/110165
PR tree-optimization/110166
* match.pd (zero_one_valued_p): Don't accept
signed 1-bit integers.
2023-06-09 Richard Biener <rguenther@suse.de>
* match.pd (two conversions in a row): Use element_precision
to DTRT for VECTOR_TYPE.
2023-06-09 Pan Li <pan2.li@intel.com>
* config/riscv/riscv.md (enabled): Move to another place, and
add fp_vector_disabled to the cond.
(fp_vector_disabled): New attr defined for disabling fp.
* config/riscv/vector-iterators.md: Fix V_WHOLE and V_FRACT.
2023-06-09 Pan Li <pan2.li@intel.com>
* config/riscv/riscv-protos.h (enum frm_field_enum): Adjust
literal to int.
2023-06-09 liuhongt <hongtao.liu@intel.com>
PR target/110108
* config/i386/i386.cc (ix86_gimple_fold_builtin): Explicitly
view_convert_expr mask to signed type when folding pblendvb
builtins.
2023-06-09 liuhongt <hongtao.liu@intel.com>
PR target/110108
* config/i386/i386.cc (ix86_gimple_fold_builtin): Fold
_mm{,256,512}_abs_{epi8,epi16,epi32,epi64} into gimple
ABSU_EXPR + VCE, don't fold _mm_abs_{pi8,pi16,pi32} w/o
TARGET_64BIT.
* config/i386/i386-builtin.def: Replace CODE_FOR_nothing with
real codename for __builtin_ia32_pabs{b,w,d}.
2023-06-08 Andrew MacLeod <amacleod@redhat.com>
* gimple-range-op.cc
(gimple_range_op_handler::gimple_range_op_handler): Adjust.
(gimple_range_op_handler::maybe_builtin_call): Adjust.
* gimple-range-op.h (operand1, operand2): Use m_operator.
* range-op.cc (integral_table, pointer_table): Relocate.
(get_op_handler): Rename from get_handler and handle all types.
(range_op_handler::range_op_handler): Relocate.
(range_op_handler::set_op_handler): Relocate and adjust.
(range_op_handler::range_op_handler): Relocate.
(dispatch_trio): New.
(RO_III, RO_IFI, RO_IFF, RO_FFF, RO_FIF, RO_FII): New consts.
(range_op_handler::dispatch_kind): New.
(range_op_handler::fold_range): Relocate and Use new dispatch value.
(range_op_handler::op1_range): Ditto.
(range_op_handler::op2_range): Ditto.
(range_op_handler::lhs_op1_relation): Ditto.
(range_op_handler::lhs_op2_relation): Ditto.
(range_op_handler::op1_op2_relation): Ditto.
(range_op_handler::set_op_handler): Use m_operator member.
* range-op.h (range_op_handler::operator bool): Use m_operator.
(range_op_handler::dispatch_kind): New.
(range_op_handler::m_valid): Delete.
(range_op_handler::m_int): Delete
(range_op_handler::m_float): Delete
(range_op_handler::m_operator): New.
(range_op_table::operator[]): Relocate from .cc file.
(range_op_table::set): Ditto.
* value-range.h (class vrange): Make range_op_handler a friend.
2023-06-08 Andrew MacLeod <amacleod@redhat.com>
* gimple-range-op.cc (cfn_constant_float_p): Change base class.
(cfn_pass_through_arg1): Adjust using statemenmt.
(cfn_signbit): Change base class, adjust using statement.
(cfn_copysign): Ditto.
(cfn_sqrt): Ditto.
(cfn_sincos): Ditto.
* range-op-float.cc (fold_range): Change class to range_operator.
(rv_fold): Ditto.
(op1_range): Ditto
(op2_range): Ditto
(lhs_op1_relation): Ditto.
(lhs_op2_relation): Ditto.
(op1_op2_relation): Ditto.
(foperator_*): Ditto.
(class float_table): New. Inherit from range_op_table.
(floating_tree_table) Change to range_op_table pointer.
(class floating_op_table): Delete.
* range-op.cc (operator_equal): Adjust using statement.
(operator_not_equal): Ditto.
(operator_lt, operator_le, operator_gt, operator_ge): Ditto.
(operator_minus, operator_cast): Ditto.
(operator_bitwise_and, pointer_plus_operator): Ditto.
(get_float_handle): Change return type.
* range-op.h (range_operator_float): Delete. Relocate all methods
into class range_operator.
(range_op_handler::m_float): Change type to range_operator.
(floating_op_table): Delete.
(floating_tree_table): Change type.
2023-06-08 Andrew MacLeod <amacleod@redhat.com>
* range-op.cc (range_operator::fold_range): Call virtual routine.
(range_operator::update_bitmask): New.
(operator_equal::update_bitmask): New.
(operator_not_equal::update_bitmask): New.
(operator_lt::update_bitmask): New.
(operator_le::update_bitmask): New.
(operator_gt::update_bitmask): New.
(operator_ge::update_bitmask): New.
(operator_ge::update_bitmask): New.
(operator_plus::update_bitmask): New.
(operator_minus::update_bitmask): New.
(operator_pointer_diff::update_bitmask): New.
(operator_min::update_bitmask): New.
(operator_max::update_bitmask): New.
(operator_mult::update_bitmask): New.
(operator_div:operator_div):New.
(operator_div::update_bitmask): New.
(operator_div::m_code): New member.
(operator_exact_divide::operator_exact_divide): New constructor.
(operator_lshift::update_bitmask): New.
(operator_rshift::update_bitmask): New.
(operator_bitwise_and::update_bitmask): New.
(operator_bitwise_or::update_bitmask): New.
(operator_bitwise_xor::update_bitmask): New.
(operator_trunc_mod::update_bitmask): New.
(op_ident, op_unknown, op_ptr_min_max): New.
(op_nop, op_convert): Delete.
(op_ssa, op_paren, op_obj_type): Delete.
(op_realpart, op_imagpart): Delete.
(op_ptr_min, op_ptr_max): Delete.
(pointer_plus_operator:update_bitmask): New.
(range_op_table::set): Do not use m_code.
(integral_table::integral_table): Adjust to single instances.
* range-op.h (range_operator::range_operator): Delete.
(range_operator::m_code): Delete.
(range_operator::update_bitmask): New.
2023-06-08 Andrew MacLeod <amacleod@redhat.com>
* range-op-float.cc (range_operator_float::fold_range): Return
NAN of the result type.
2023-06-08 Jakub Jelinek <jakub@redhat.com>
* optabs.cc (expand_ffs): Add forward declaration.
(expand_doubleword_clz): Rename to ...
(expand_doubleword_clz_ctz_ffs): ... this. Add UNOPTAB argument,
handle also doubleword CTZ and FFS in addition to CLZ.
(expand_unop): Adjust caller. Also call it for doubleword
ctz_optab and ffs_optab.
2023-06-08 Jakub Jelinek <jakub@redhat.com>
PR target/110152
* config/i386/i386-expand.cc (ix86_expand_vector_init_general): For
n_words == 2 recurse with mmx_ok as first argument rather than false.
2023-06-07 Roger Sayle <roger@nextmovesoftware.com>
* wide-int.cc (wi::bitreverse_large): Use HOST_WIDE_INT_1U to
avoid sign extension/undefined behaviour when setting each bit.
2023-06-07 Roger Sayle <roger@nextmovesoftware.com>
Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386-expand.cc (ix86_expand_builtin) <handlecarry>:
Use new x86_stc instruction when the carry flag must be set.
* config/i386/i386.cc (ix86_cc_mode): Use CCCmode for *x86_cmc.
(ix86_rtx_costs): Provide accurate rtx_costs for *x86_cmc.
* config/i386/i386.h (TARGET_SLOW_STC): New define.
* config/i386/i386.md (UNSPEC_STC): New UNSPEC for stc.
(x86_stc): New define_insn.
(define_peephole2): Convert x86_stc into alternate implementation
on pentium4 without -Os when a QImode register is available.
(*x86_cmc): New define_insn.
(define_peephole2): Convert *x86_cmc into alternate implementation
on pentium4 without -Os when a QImode register is available.
(*setccc): New define_insn_and_split for a no-op CCCmode move.
(*setcc_qi_negqi_ccc_1_<mode>): New define_insn_and_split to
recognize (and eliminate) the carry flag being copied to itself.
(*setcc_qi_negqi_ccc_2_<mode>): Likewise.
* config/i386/x86-tune.def (X86_TUNE_SLOW_STC): New tuning flag.
2023-06-07 Andrew Pinski <apinski@marvell.com>
* match.pd: Fix comment for the
`(zero_one ==/!= 0) ? y : z <op> y` patterns.
2023-06-07 Jeff Law <jlaw@ventanamicro.com>
Jeff Law <jlaw@ventanamicro.com>
* config/riscv/bitmanip.md (rotrdi3, rotrsi3, rotlsi3): New expanders.
(rotrsi3_sext): Expose generator.
(rotlsi3 pattern): Hide generator.
* config/riscv/riscv-protos.h (riscv_emit_binary): New function
declaration.
* config/riscv/riscv.cc (riscv_emit_binary): Removed static
* config/riscv/riscv.md (addsi3, subsi3, negsi2): Hide generator.
(mulsi3, <optab>si3): Likewise.
(addsi3, subsi3, negsi2, mulsi3, <optab>si3): New expanders.
(addv<mode>4, subv<mode>4, mulv<mode>4): Use riscv_emit_binary.
(<u>mulsidi3): Likewise.
(addsi3_extended, subsi3_extended, negsi2_extended): Expose generator.
(mulsi3_extended, <optab>si3_extended): Likewise.
(splitter for shadd feeding divison): Update RTL pattern to account
for changes in how 32 bit ops are expanded for TARGET_64BIT.
* loop-iv.cc (get_biv_step_1): Process src of extension when it PLUS.
2023-06-07 Dimitar Dimitrov <dimitar@dinux.eu>
PR target/109725
* config/riscv/riscv.cc (riscv_print_operand): Calculate
memmodel only when it is valid.
2023-06-07 Dimitar Dimitrov <dimitar@dinux.eu>
* config/riscv/riscv.cc (riscv_const_insns): Recursively call
for constant element of a vector.
2023-06-07 Jakub Jelinek <jakub@redhat.com>
* match.pd (zero_one_valued_p): Don't handle integer_zerop specially,
instead compare tree_nonzero_bits <= 1U rather than just == 1.
2023-06-07 Alex Coplan <alex.coplan@arm.com>
PR target/110132
* config/aarch64/aarch64-builtins.cc (aarch64_general_simulate_builtin):
New. Use it ...
(aarch64_init_ls64_builtins): ... here. Switch to declaring public ACLE
names for builtins.
(aarch64_general_init_builtins): Ensure we invoke the arm_acle.h
setup if in_lto_p, just like we do for SVE.
* config/aarch64/arm_acle.h: (__arm_ld64b): Delete.
(__arm_st64b): Delete.
(__arm_st64bv): Delete.
(__arm_st64bv0): Delete.
2023-06-07 Alex Coplan <alex.coplan@arm.com>
PR target/110100
* config/aarch64/aarch64-builtins.cc (aarch64_expand_builtin_ls64):
Use input operand for the destination address.
* config/aarch64/aarch64.md (st64b): Fix constraint on address
operand.
2023-06-07 Alex Coplan <alex.coplan@arm.com>
PR target/110100
* config/aarch64/aarch64-builtins.cc (aarch64_init_ls64_builtins_types):
Replace eight consecutive spaces with tabs.
(aarch64_init_ls64_builtins): Likewise.
(aarch64_expand_builtin_ls64): Likewise.
* config/aarch64/aarch64.md (ld64b): Likewise.
(st64b): Likewise.
(st64bv): Likewise
(st64bv0): Likewise.
2023-06-07 Vladimir N. Makarov <vmakarov@redhat.com>
* ira-costs.cc: (find_costs_and_classes): Constrain classes of pic
offset table pseudo to a general reg subset.
2023-06-07 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-simd.md (aarch64_sqmovun<mode><vczle><vczbe>):
Rename to...
(*aarch64_sqmovun<mode>_insn<vczle><vczbe>): ... This. Reimplement
with RTL codes.
(aarch64_sqmovun<mode> [SD_HSDI]): Reimplement with RTL codes.
(aarch64_sqxtun2<mode>_le): Likewise.
(aarch64_sqxtun2<mode>_be): Likewise.
(aarch64_sqxtun2<mode>): Adjust for the above.
(aarch64_sqmovun<mode>): New define_expand.
* config/aarch64/iterators.md (UNSPEC_SQXTUN): Delete.
(half_mask): New mode attribute.
* config/aarch64/predicates.md (aarch64_simd_umax_half_mode):
New predicate.
2023-06-07 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-simd.md (aarch64_addp<mode><vczle><vczbe>):
Reimplement as...
(aarch64_addp<mode>_insn): ... This...
(aarch64_addp<mode><vczle><vczbe>_insn): ... And this.
(aarch64_addp<mode>): New define_expand.
2023-06-07 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-protos.h (expand_vec_perm_const): New function.
* config/riscv/riscv-v.cc
(rvv_builder::can_duplicate_repeating_sequence_p): Support POLY
handling.
(rvv_builder::single_step_npatterns_p): New function.
(rvv_builder::npatterns_all_equal_p): Ditto.
(const_vec_all_in_range_p): Support POLY handling.
(gen_const_vector_dup): Ditto.
(emit_vlmax_gather_insn): Add vrgatherei16.
(emit_vlmax_masked_gather_mu_insn): Ditto.
(expand_const_vector): Add VLA SLP const vector support.
(expand_vec_perm): Support POLY.
(struct expand_vec_perm_d): New struct.
(shuffle_generic_patterns): New function.
(expand_vec_perm_const_1): Ditto.
(expand_vec_perm_const): Ditto.
* config/riscv/riscv.cc (riscv_vectorize_vec_perm_const): Ditto.
(TARGET_VECTORIZE_VEC_PERM_CONST): New targethook.
2023-06-07 Andrew Pinski <apinski@marvell.com>
PR middle-end/110117
* expr.cc (expand_single_bit_test): Handle
const_int from expand_expr.
2023-06-07 Andrew Pinski <apinski@marvell.com>
* expr.cc (do_store_flag): Rearrange the
TER code so that it overrides the nonzero bits
info if we had `a & POW2`.
2023-06-07 Andrew Pinski <apinski@marvell.com>
PR tree-optimization/110134
* match.pd (-A CMP -B -> B CMP A): Allow EQ/NE for all integer
types.
(-A CMP CST -> B CMP (-CST)): Likewise.
2023-06-07 Andrew Pinski <apinski@marvell.com>
PR tree-optimization/89263
PR tree-optimization/99069
PR tree-optimization/20083
PR tree-optimization/94898
* match.pd: Add patterns to optimize `a ? onezero : onezero` with
one of the operands are constant.
2023-06-07 Andrew Pinski <apinski@marvell.com>
* match.pd (zero_one_valued_p): Match 0 integer constant
too.
2023-06-07 Pan Li <pan2.li@intel.com>
* config/riscv/riscv-vector-builtins-types.def
(vfloat32mf2_t): Take RVV_REQUIRE_ELEN_FP_16 as requirement.
(vfloat32m1_t): Ditto.
(vfloat32m2_t): Ditto.
(vfloat32m4_t): Ditto.
(vfloat32m8_t): Ditto.
(vint16mf4_t): Ditto.
(vint16mf2_t): Ditto.
(vint16m1_t): Ditto.
(vint16m2_t): Ditto.
(vint16m4_t): Ditto.
(vint16m8_t): Ditto.
(vuint16mf4_t): Ditto.
(vuint16mf2_t): Ditto.
(vuint16m1_t): Ditto.
(vuint16m2_t): Ditto.
(vuint16m4_t): Ditto.
(vuint16m8_t): Ditto.
(vint32mf2_t): Ditto.
(vint32m1_t): Ditto.
(vint32m2_t): Ditto.
(vint32m4_t): Ditto.
(vint32m8_t): Ditto.
(vuint32mf2_t): Ditto.
(vuint32m1_t): Ditto.
(vuint32m2_t): Ditto.
(vuint32m4_t): Ditto.
(vuint32m8_t): Ditto.
2023-06-07 Jason Merrill <jason@redhat.com>
PR c++/58487
* doc/invoke.texi: Document it.
2023-06-06 Roger Sayle <roger@nextmovesoftware.com>
* doc/rtl.texi (bitreverse, copysign): Document new RTX codes.
* rtl.def (BITREVERSE, COPYSIGN): Define new RTX codes.
* simplify-rtx.cc (simplify_unary_operation_1): Optimize
NOT (BITREVERSE x) as BITREVERSE (NOT x).
Optimize POPCOUNT (BITREVERSE x) as POPCOUNT x.
Optimize PARITY (BITREVERSE x) as PARITY x.
Optimize BITREVERSE (BITREVERSE x) as x.
(simplify_const_unary_operation) <case BITREVERSE>: Evaluate
BITREVERSE of a constant integer at compile-time.
(simplify_binary_operation_1) <case COPYSIGN>: Optimize
COPY_SIGN (x, x) as x. Optimize COPYSIGN (x, C) as ABS x
or NEG (ABS x) for constant C. Optimize COPYSIGN (ABS x, y)
and COPYSIGN (NEG x, y) as COPYSIGN (x, y).
Optimize COPYSIGN (x, ABS y) as ABS x.
Optimize COPYSIGN (COPYSIGN (x, y), z) as COPYSIGN (x, z).
Optimize COPYSIGN (x, COPYSIGN (y, z)) as COPYSIGN (x, z).
(simplify_const_binary_operation): Evaluate COPYSIGN of constant
arguments at compile-time.
2023-06-06 Uros Bizjak <ubizjak@gmail.com>
* rtl.h (function_invariant_p): Change return type from int to bool.
* reload1.cc (function_invariant_p): Change return type from
int to bool and adjust function body accordingly.
2023-06-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/autovec-opt.md (*<optab>_fma<mode>): New pattern.
(*single_<optab>mult_plus<mode>): Ditto.
(*double_<optab>mult_plus<mode>): Ditto.
(*sign_zero_extend_fma): Ditto.
(*zero_sign_extend_fma): Ditto.
* config/riscv/riscv-protos.h (enum insn_type): New enum.
2023-06-06 Kwok Cheung Yeung <kcy@codesourcery.com>
Tobias Burnus <tobias@codesourcery.com>
* gimplify.cc (omp_notice_variable): Apply GOVD_MAP_ALLOC_ONLY flag
and defaultmap flags if the defaultmap has GOVD_MAP_FORCE_PRESENT flag
set.
(omp_get_attachment): Handle map clauses with 'present' modifier.
(omp_group_base): Likewise.
(gimplify_scan_omp_clauses): Reorder present maps to come first.
Set GOVD flags for present defaultmaps.
(gimplify_adjust_omp_clauses_1): Set map kind for present defaultmaps.
* omp-low.cc (scan_sharing_clauses): Handle 'always, present' map
clauses.
(lower_omp_target): Handle map clauses with 'present' modifier.
Handle 'to' and 'from' clauses with 'present'.
* tree-core.h (enum omp_clause_defaultmap_kind): Add
OMP_CLAUSE_DEFAULTMAP_PRESENT defaultmap kind.
* tree-pretty-print.cc (dump_omp_clause): Handle 'map', 'to' and
'from' clauses with 'present' modifier. Handle present defaultmap.
* tree.h (OMP_CLAUSE_MOTION_PRESENT): New #define.
2023-06-06 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/genfusion.pl: Delete some dead code.
2023-06-06 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/genfusion.pl (gen_ld_cmpi_p10_one): New, rewritten and
split out from...
(gen_ld_cmpi_p10): ... this.
2023-06-06 Jeevitha Palanisamy <jeevitha@linux.ibm.com>
PR target/106907
* config/rs6000/rs6000.cc (vec_const_128bit_to_bytes): Remove
duplicate expression.
2023-06-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-builtins.cc (aarch64_general_gimple_fold_builtin):
Handle unsigned reduc_plus_scal_ builtins.
* config/aarch64/aarch64-simd-builtins.def (addp): Delete DImode instances.
* config/aarch64/aarch64-simd.md (aarch64_addpdi): Delete.
* config/aarch64/arm_neon.h (vpaddd_s64): Reimplement with
__builtin_aarch64_reduc_plus_scal_v2di.
(vpaddd_u64): Reimplement with __builtin_aarch64_reduc_plus_scal_v2di_uu.
2023-06-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-simd.md (aarch64_<sur>shr_n<mode>): Delete.
(aarch64_<sra_op>rshr_n<mode><vczle><vczbe>_insn): New define_insn.
(aarch64_<sra_op>rshr_n<mode>): New define_expand.
2023-06-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-simd.md (aarch64_shrn<mode>_insn_le): Delete.
(aarch64_shrn<mode>_insn_be): Delete.
(*aarch64_<srn_op>shrn<mode>_vect): Rename to...
(*aarch64_<srn_op>shrn<mode><vczle><vczbe>): ... This.
(aarch64_shrn<mode>): Remove reference to the above deleted patterns.
(aarch64_rshrn<mode>_insn_le): Delete.
(aarch64_rshrn<mode>_insn_be): Delete.
(aarch64_rshrn<mode><vczle><vczbe>_insn): New define_insn.
(aarch64_rshrn<mode>): Remove references to the above deleted patterns.
2023-06-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-protos.h (aarch64_parallel_select_half_p):
Define prototype.
(aarch64_pars_overlap_p): Likewise.
* config/aarch64/aarch64-simd.md (aarch64_<su>addlv<mode>):
Express in terms of UNSPEC_ADDV.
(*aarch64_<su>addlv<VDQV_L:mode>_ze<GPI:mode>): Likewise.
(*aarch64_<su>addlv<mode>_reduction): Define.
(*aarch64_uaddlv<mode>_reduction_2): Likewise.
* config/aarch64/aarch64.cc (aarch64_parallel_select_half_p): Define.
(aarch64_pars_overlap_p): Likewise.
* config/aarch64/iterators.md (UNSPEC_SADDLV, UNSPEC_UADDLV): Delete.
(VQUADW): New mode attribute.
(VWIDE2X_S): Likewise.
(USADDLV): Delete.
(su): Delete handling of UNSPEC_SADDLV, UNSPEC_UADDLV.
* config/aarch64/predicates.md (vect_par_cnst_select_half): Define.
2023-06-06 Richard Biener <rguenther@suse.de>
PR middle-end/110055
* gimplify.cc (gimplify_target_expr): Do not emit
CLOBBERs for variables which have static storage duration
after gimplifying their initializers.
2023-06-06 Richard Biener <rguenther@suse.de>
PR tree-optimization/109143
* tree-ssa-structalias.cc (solution_set_expand): Avoid
one bitmap iteration and optimize bit range setting.
2023-06-06 Hans-Peter Nilsson <hp@axis.com>
PR bootstrap/110120
* postreload.cc (reload_cse_move2add, move2add_use_add2_insn): Use
XVECEXP, not XEXP, to access first item of a PARALLEL.
2023-06-06 Pan Li <pan2.li@intel.com>
* config/riscv/riscv-vector-builtins-types.def
(vfloat16mf4_t): Add vfloat16mf4_t to WF operations.
(vfloat16mf2_t): Likewise.
(vfloat16m1_t): Likewise.
(vfloat16m2_t): Likewise.
(vfloat16m4_t): Likewise.
(vfloat16m8_t): Likewise.
* config/riscv/vector-iterators.md: Add FP=16 to VWF, VWF_ZVE64,
VWLMUL1, VWLMUL1_ZVE64, vwlmul1 and vwlmul1_zve64.
2023-06-06 Fei Gao <gaofei@eswincomputing.com>
* config/riscv/riscv.cc (riscv_adjust_libcall_cfi_prologue): Use Pmode
for cfi reg/mem machmode
(riscv_adjust_libcall_cfi_epilogue): Use Pmode for cfi reg machmode
2023-06-06 Li Xu <xuli1@eswincomputing.com>
* config/riscv/vector-iterators.md:
Fix 'REQUIREMENT' for machine_mode 'MODE'.
* config/riscv/vector.md (@pred_indexed_<order>store<VNX16_QHS:mode>
<VNX16_QHSI:mode>): change VNX16_QHSI to VNX16_QHSDI.
(@pred_indexed_<order>store<VNX16_QHS:mode><VNX16_QHSDI:mode>): Ditto.
2023-06-06 Pan Li <pan2.li@intel.com>
* config/riscv/vector-iterators.md: Fix typo in mode attr.
2023-06-05 Andre Vieira <andre.simoesdiasvieira@arm.com>
Joel Hutton <joel.hutton@arm.com>
* doc/generic.texi: Remove old tree codes.
* expr.cc (expand_expr_real_2): Remove old tree code cases.
* gimple-pretty-print.cc (dump_binary_rhs): Likewise.
* optabs-tree.cc (optab_for_tree_code): Likewise.
(supportable_half_widening_operation): Likewise.
* tree-cfg.cc (verify_gimple_assign_binary): Likewise.
* tree-inline.cc (estimate_operator_cost): Likewise.
(op_symbol_code): Likewise.
* tree-vect-data-refs.cc (vect_get_smallest_scalar_type): Likewise.
(vect_analyze_data_ref_accesses): Likewise.
* tree-vect-generic.cc (expand_vector_operations_1): Likewise.
* cfgexpand.cc (expand_debug_expr): Likewise.
* tree-vect-stmts.cc (vectorizable_conversion): Likewise.
(supportable_widening_operation): Likewise.
* gimple-range-op.cc (gimple_range_op_handler::maybe_non_standard):
Likewise.
* optabs.def (vec_widen_ssubl_hi_optab, vec_widen_ssubl_lo_optab,
vec_widen_saddl_hi_optab, vec_widen_saddl_lo_optab,
vec_widen_usubl_hi_optab, vec_widen_usubl_lo_optab,
vec_widen_uaddl_hi_optab, vec_widen_uaddl_lo_optab): Remove optabs.
* tree-pretty-print.cc (dump_generic_node): Remove tree code definition.
* tree.def (WIDEN_PLUS_EXPR, WIDEN_MINUS_EXPR, VEC_WIDEN_PLUS_HI_EXPR,
VEC_WIDEN_PLUS_LO_EXPR, VEC_WIDEN_MINUS_HI_EXPR,
VEC_WIDEN_MINUS_LO_EXPR): Likewise.
2023-06-05 Andre Vieira <andre.simoesdiasvieira@arm.com>
Joel Hutton <joel.hutton@arm.com>
Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64-simd.md (vec_widen_<su>addl_lo_<mode>): Rename
this ...
(vec_widen_<su>add_lo_<mode>): ... to this.
(vec_widen_<su>addl_hi_<mode>): Rename this ...
(vec_widen_<su>add_hi_<mode>): ... to this.
(vec_widen_<su>subl_lo_<mode>): Rename this ...
(vec_widen_<su>sub_lo_<mode>): ... to this.
(vec_widen_<su>subl_hi_<mode>): Rename this ...
(vec_widen_<su>sub_hi_<mode>): ...to this.
* doc/generic.texi: Document new IFN codes.
* internal-fn.cc (lookup_hilo_internal_fn): Add lookup function.
(commutative_binary_fn_p): Add widen_plus fn's.
(widening_fn_p): New function.
(narrowing_fn_p): New function.
(direct_internal_fn_optab): Change visibility.
* internal-fn.def (DEF_INTERNAL_WIDENING_OPTAB_FN): Macro to define an
internal_fn that expands into multiple internal_fns for widening.
(IFN_VEC_WIDEN_PLUS, IFN_VEC_WIDEN_PLUS_HI, IFN_VEC_WIDEN_PLUS_LO,
IFN_VEC_WIDEN_PLUS_EVEN, IFN_VEC_WIDEN_PLUS_ODD,
IFN_VEC_WIDEN_MINUS, IFN_VEC_WIDEN_MINUS_HI,
IFN_VEC_WIDEN_MINUS_LO, IFN_VEC_WIDEN_MINUS_ODD,
IFN_VEC_WIDEN_MINUS_EVEN): Define widening plus,minus functions.
* internal-fn.h (direct_internal_fn_optab): Declare new prototype.
(lookup_hilo_internal_fn): Likewise.
(widening_fn_p): Likewise.
(Narrowing_fn_p): Likewise.
* optabs.cc (commutative_optab_p): Add widening plus optabs.
* optabs.def (OPTAB_D): Define widen add, sub optabs.
* tree-vect-patterns.cc (vect_recog_widen_op_pattern): Support
patterns with a hi/lo or even/odd split.
(vect_recog_sad_pattern): Refactor to use new IFN codes.
(vect_recog_widen_plus_pattern): Likewise.
(vect_recog_widen_minus_pattern): Likewise.
(vect_recog_average_pattern): Likewise.
* tree-vect-stmts.cc (vectorizable_conversion): Add support for
_HILO IFNs.
(supportable_widening_operation): Likewise.
* tree.def (WIDEN_SUM_EXPR): Update example to use new IFNs.
2023-06-05 Andre Vieira <andre.simoesdiasvieira@arm.com>
Joel Hutton <joel.hutton@arm.com>
* tree-vect-patterns.cc: Add include for gimple-iterator.
(vect_recog_widen_op_pattern): Refactor to use code_helper.
(vect_gimple_build): New function.
* tree-vect-stmts.cc (simple_integer_narrowing): Refactor to use
code_helper.
(vectorizable_call): Likewise.
(vect_gen_widened_results_half): Likewise.
(vect_create_vectorized_demotion_stmts): Likewise.
(vect_create_vectorized_promotion_stmts): Likewise.
(vect_create_half_widening_stmts): Likewise.
(vectorizable_conversion): Likewise.
(supportable_widening_operation): Likewise.
(supportable_narrowing_operation): Likewise.
* tree-vectorizer.h (supportable_widening_operation): Change
prototype to use code_helper.
(supportable_narrowing_operation): Likewise.
(vect_gimple_build): New function prototype.
* tree.h (code_helper::safe_as_tree_code): New function.
(code_helper::safe_as_fn_code): New function.
2023-06-05 Roger Sayle <roger@nextmovesoftware.com>
* wide-int.cc (wi::bitreverse_large): New function implementing
bit reversal of an integer.
* wide-int.h (wi::bitreverse): New (template) function prototype.
(bitreverse_large): Prototype helper function/implementation.
(wi::bitreverse): New template wrapper around bitreverse_large.
2023-06-05 Uros Bizjak <ubizjak@gmail.com>
* rtl.h (print_rtl_single): Change return type from int to void.
(print_rtl_single_with_indent): Ditto.
* print-rtl.h (class rtx_writer): Ditto. Change m_sawclose to bool.
* print-rtl.cc (rtx_writer::rtx_writer): Update for m_sawclose change.
(rtx_writer::print_rtx_operand_code_0): Ditto.
(rtx_writer::print_rtx_operand_codes_E_and_V): Ditto.
(rtx_writer::print_rtx_operand_code_i): Ditto.
(rtx_writer::print_rtx_operand_code_u): Ditto.
(rtx_writer::print_rtx_operand): Ditto.
(rtx_writer::print_rtx): Ditto.
(rtx_writer::finish_directive): Ditto.
(print_rtl_single): Change return type from int to void
and adjust function body accordingly.
(rtx_writer::print_rtl_single_with_indent): Ditto.
2023-06-05 Uros Bizjak <ubizjak@gmail.com>
* rtl.h (reg_classes_intersect_p): Change return type from int to bool.
(reg_class_subset_p): Ditto.
* reginfo.cc (reg_classes_intersect_p): Ditto.
(reg_class_subset_p): Ditto.
2023-06-05 Pan Li <pan2.li@intel.com>
* config/riscv/riscv-vector-builtins-types.def
(vfloat32mf2_t): New type for DEF_RVV_WEXTF_OPS.
(vfloat32m1_t): Ditto.
(vfloat32m2_t): Ditto.
(vfloat32m4_t): Ditto.
(vfloat32m8_t): Ditto.
(vint16mf4_t): New type for DEF_RVV_CONVERT_I_OPS.
(vint16mf2_t): Ditto.
(vint16m1_t): Ditto.
(vint16m2_t): Ditto.
(vint16m4_t): Ditto.
(vint16m8_t): Ditto.
(vuint16mf4_t): New type for DEF_RVV_CONVERT_U_OPS.
(vuint16mf2_t): Ditto.
(vuint16m1_t): Ditto.
(vuint16m2_t): Ditto.
(vuint16m4_t): Ditto.
(vuint16m8_t): Ditto.
(vint32mf2_t): New type for DEF_RVV_WCONVERT_I_OPS.
(vint32m1_t): Ditto.
(vint32m2_t): Ditto.
(vint32m4_t): Ditto.
(vint32m8_t): Ditto.
(vuint32mf2_t): New type for DEF_RVV_WCONVERT_U_OPS.
(vuint32m1_t): Ditto.
(vuint32m2_t): Ditto.
(vuint32m4_t): Ditto.
(vuint32m8_t): Ditto.
* config/riscv/vector-iterators.md: Add FP=16 support for V,
VWCONVERTI, VCONVERT, VNCONVERT, VMUL1 and vlmul1.
2023-06-05 Andrew Pinski <apinski@marvell.com>
PR bootstrap/110085
* Makefile.in (clean): Remove the removing of
MULTILIB_DIR/MULTILIB_OPTIONS directories.
2023-06-05 YunQiang Su <yunqiang.su@cipunited.com>
* config/mips/mips-protos.h (mips_emit_speculation_barrier): New
prototype.
* config/mips/mips.cc (speculation_barrier_libfunc): New static
variable.
(mips_init_libfuncs): Initialize it.
(mips_emit_speculation_barrier): New function.
* config/mips/mips.md (speculation_barrier): Call
mips_emit_speculation_barrier.
2023-06-05 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-v.cc (class rvv_builder): Reorganize functions.
(rvv_builder::can_duplicate_repeating_sequence_p): Ditto.
(rvv_builder::repeating_sequence_use_merge_profitable_p): Ditto.
(rvv_builder::get_merged_repeating_sequence): Ditto.
(rvv_builder::get_merge_scalar_mask): Ditto.
(emit_scalar_move_insn): Ditto.
(emit_vlmax_integer_move_insn): Ditto.
(emit_nonvlmax_integer_move_insn): Ditto.
(emit_vlmax_gather_insn): Ditto.
(emit_vlmax_masked_gather_mu_insn): Ditto.
(get_repeating_sequence_dup_machine_mode): Ditto.
2023-06-05 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/autovec.md: Split arguments.
* config/riscv/riscv-protos.h (expand_vec_perm): Ditto.
* config/riscv/riscv-v.cc (expand_vec_perm): Ditto.
2023-06-04 Andrew Pinski <apinski@marvell.com>
* expr.cc (do_store_flag): Improve for single bit testing
not against zero but against that single bit.
2023-06-04 Andrew Pinski <apinski@marvell.com>
* expr.cc (do_store_flag): Extend the one bit checking case
to handle the case where we don't have an and but rather still
one bit is known to be non-zero.
2023-06-04 Jeff Law <jlaw@ventanamicro.com>
* config/h8300/constraints.md (Zz): Make this a normal
constraint.
* config/h8300/h8300.cc (TARGET_LRA_P): Remove.
* config/h8300/logical.md (H8/SX bit patterns): Remove.
2023-06-04 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.md (*btrue_INT_MIN, *eqne_INT_MIN):
New insn_and_split patterns.
2023-06-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
PR target/110109
* config/riscv/riscv-vector-builtins-bases.cc: Change expand approach.
* config/riscv/vector.md (@vlmul_extx2<mode>): Remove it.
(@vlmul_extx4<mode>): Ditto.
(@vlmul_extx8<mode>): Ditto.
(@vlmul_extx16<mode>): Ditto.
(@vlmul_extx32<mode>): Ditto.
(@vlmul_extx64<mode>): Ditto.
(*vlmul_extx2<mode>): Ditto.
(*vlmul_extx4<mode>): Ditto.
(*vlmul_extx8<mode>): Ditto.
(*vlmul_extx16<mode>): Ditto.
(*vlmul_extx32<mode>): Ditto.
(*vlmul_extx64<mode>): Ditto.
2023-06-04 Pan Li <pan2.li@intel.com>
* config/riscv/riscv-vector-builtins-types.def
(vfloat32mf2_t): Add vfloat32mf2_t type to vfncvt.f.f.w operations.
(vfloat32m1_t): Likewise.
(vfloat32m2_t): Likewise.
(vfloat32m4_t): Likewise.
(vfloat32m8_t): Likewise.
* config/riscv/riscv-vector-builtins.def: Fix typo in comments.
* config/riscv/vector-iterators.md: Add single to half machine
mode conversion.
2023-06-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/autovec-opt.md (*<optab>not<mode>): Move to autovec-opt.md.
(*n<optab><mode>): Ditto.
* config/riscv/autovec.md (*<optab>not<mode>): Ditto.
(*n<optab><mode>): Ditto.
* config/riscv/vector.md: Ditto.
2023-06-04 Roger Sayle <roger@nextmovesoftware.com>
PR target/110083
* config/i386/i386-features.cc (scalar_chain::convert_compare):
Update or delete REG_EQUAL notes, converting CONST_INT and
CONST_WIDE_INT immediate operands to a suitable CONST_VECTOR.
2023-06-04 Jason Merrill <jason@redhat.com>
PR c++/97720
* tree-eh.cc (lower_resx): Pass the exception pointer to the
failure_decl.
* except.h: Tweak comment.
2023-06-04 Hans-Peter Nilsson <hp@axis.com>
* postreload.cc (move2add_use_add2_insn): Handle
trivial single_sets. Rename variable PAT to SET.
(move2add_use_add3_insn, reload_cse_move2add): Similar.
2023-06-04 Pan Li <pan2.li@intel.com>
* config/riscv/riscv-vector-builtins-types.def
(vfloat16mf4_t): Add the float16 type to DEF_RVV_F_OPS.
(vfloat16mf2_t): Likewise.
(vfloat16m1_t): Likewise.
(vfloat16m2_t): Likewise.
(vfloat16m4_t): Likewise.
(vfloat16m8_t): Likewise.
* config/riscv/riscv.md: Add vfloat16*_t to attr mode.
* config/riscv/vector-iterators.md: Add vfloat16*_t machine mode
to V, V_WHOLE, V_FRACT, VINDEX, VM, VEL and sew.
* config/riscv/vector.md: Add vfloat16*_t machine mode to sew,
vlmul and ratio.
2023-06-03 Fei Gao <gaofei@eswincomputing.com>
* config/riscv/riscv.cc (riscv_expand_epilogue): fix cfi issue with
correct offset.
2023-06-03 Die Li <lidie@eswincomputing.com>
* config/riscv/thead.md (*th_cond_gpr_mov<GPR:mode><GPR2:mode>): Delete.
2023-06-03 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/predicates.md: Change INTVAL into UINTVAL.
2023-06-03 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/vector.md: Add vector-opt.md.
* config/riscv/autovec-opt.md: New file.
2023-06-03 liuhongt <hongtao.liu@intel.com>
PR tree-optimization/110067
* gimple-ssa-store-merging.cc (find_bswap_or_nop): Don't try
bswap + rotate when TYPE_PRECISION(n->type) > n->range.
2023-06-03 liuhongt <hongtao.liu@intel.com>
PR target/92658
* config/i386/mmx.md (truncv2hiv2qi2): New define_insn.
(truncv2si<mode>2): Ditto.
2023-06-02 Andrew Pinski <apinski@marvell.com>
PR rtl-optimization/102733
* dse.cc (store_info): Add addrspace field.
(record_store): Record the address space
and check to make sure they are the same.
2023-06-02 Andrew Pinski <apinski@marvell.com>
PR rtl-optimization/110042
* ifcvt.cc (bbs_ok_for_cmove_arith): Allow paradoxical subregs.
(bb_valid_for_noce_process_p): Strip the subreg for the SET_DEST.
2023-06-02 Iain Sandoe <iain@sandoe.co.uk>
PR target/110044
* config/rs6000/rs6000.cc (darwin_rs6000_special_round_type_align):
Make sure that we do not have a cap on field alignment before altering
the struct layout based on the type alignment of the first entry.
2023-06-02 David Faust <david.faust@oracle.com>
PR debug/110073
* btfout.cc (btf_absolute_func_id): New function.
(btf_asm_func_type): Call it here. Change index parameter from
size_t to ctf_id_t. Use PRIu64 formatter.
2023-06-02 Alex Coplan <alex.coplan@arm.com>
* btfout.cc (btf_asm_type): Use PRIu64 instead of %lu for uint64_t.
(btf_asm_datasec_type): Likewise.
2023-06-02 Carl Love <cel@us.ibm.com>
* config/rs6000/rs6000-builtins.def (__builtin_altivec_tr_stxvrhx,
__builtin_altivec_tr_stxvrwx): Fix type of third argument.
2023-06-02 Jason Merrill <jason@redhat.com>
PR c++/110070
PR c++/105838
* tree.h (DECL_MERGEABLE): New.
* tree-core.h (struct tree_decl_common): Mention it.
* gimplify.cc (gimplify_init_constructor): Check it.
* cgraph.cc (symtab_node::address_can_be_compared_p): Likewise.
* varasm.cc (categorize_decl_for_section): Likewise.
2023-06-02 Uros Bizjak <ubizjak@gmail.com>
* rtl.h (stack_regs_mentioned): Change return type from int to bool.
* reg-stack.cc (struct_block_info_def): Change "done" to bool.
(stack_regs_mentioned_p): Change return type from int to bool
and adjust function body accordingly.
(stack_regs_mentioned): Ditto.
(check_asm_stack_operands): Ditto. Change "malformed_asm"
variable to bool.
(move_for_stack_reg): Recode handling of control_flow_insn_deleted.
(swap_rtx_condition_1): Change return type from int to bool
and adjust function body accordingly. Change "r" variable to bool.
(swap_rtx_condition): Change return type from int to bool
and adjust function body accordingly.
(subst_stack_regs_pat): Recode handling of control_flow_insn_deleted.
(subst_stack_regs): Ditto.
(convert_regs_entry): Change return type from int to bool and adjust
function body accordingly. Change "inserted" variable to bool.
(convert_regs_1): Recode handling of control_flow_insn_deleted.
(convert_regs_2): Recode handling of cfg_altered.
(convert_regs): Ditto. Change "inserted" variable to bool.
2023-06-02 Jason Merrill <jason@redhat.com>
PR c++/95226
* varasm.cc (output_constant) [REAL_TYPE]: Check that sizes match.
(initializer_constant_valid_p_1): Compare float precision.
2023-06-02 Alexander Monakov <amonakov@ispras.ru>
* doc/extend.texi (Vector Extensions): Clarify bitwise shift
semantics.
2023-06-02 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* tree-vect-loop-manip.cc (vect_set_loop_controls_directly): Change decrement IV flow.
(vect_set_loop_condition_partial_vectors): Ditto.
2023-06-02 Georg-Johann Lay <avr@gjlay.de>
PR target/110088
* config/avr/avr.md: Add an RTL peephole to optimize operations on
non-LD_REGS after a move from LD_REGS.
(piaop): New code iterator.
2023-06-02 Thomas Schwinge <thomas@codesourcery.com>
PR testsuite/66005
* doc/install.texi: Document (optional) Perl usage for parallel
testing of libgomp.
2023-06-02 Thomas Schwinge <thomas@codesourcery.com>
PR bootstrap/82856
* doc/install.texi (Perl): Back to requiring "Perl version 5.6.1 (or
later)".
2023-06-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
KuanLin Chen <best124612@gmail.com>
* config/riscv/riscv-vector-builtins-bases.cc: Add _mu overloaded intrinsics.
* config/riscv/riscv-vector-builtins-shapes.cc (struct fault_load_def): Ditto.
2023-06-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-v.cc (expand_vec_series): Optimize reverse series index vector.
2023-06-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/predicates.md: Change INTVAL into UINTVAL.
2023-06-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_VXRM_ENUM): Add
__RISCV_ prefix.
(DEF_RVV_FRM_ENUM): Ditto.
2023-06-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vector-builtins-bases.cc: Change vwadd.wv/vwsub.wv
intrinsic API expander
* config/riscv/vector.md
(@pred_single_widen_<plus_minus:optab><any_extend:su><mode>): Remove it.
(@pred_single_widen_sub<any_extend:su><mode>): New pattern.
(@pred_single_widen_add<any_extend:su><mode>): New pattern.
2023-06-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/autovec.md (vec_perm<mode>): New pattern.
* config/riscv/predicates.md (vector_perm_operand): New predicate.
* config/riscv/riscv-protos.h (enum insn_type): New enum.
(expand_vec_perm): New function.
* config/riscv/riscv-v.cc (const_vec_all_in_range_p): Ditto.
(gen_const_vector_dup): Ditto.
(emit_vlmax_gather_insn): Ditto.
(emit_vlmax_masked_gather_mu_insn): Ditto.
(expand_vec_perm): Ditto.
2023-06-01 Jason Merrill <jason@redhat.com>
* doc/invoke.texi (-Wpedantic): Improve clarity.
2023-06-01 Uros Bizjak <ubizjak@gmail.com>
* rtl.h (exp_equiv_p): Change return type from int to bool.
* cse.cc (mention_regs): Change return type from int to bool
and adjust function body accordingly.
(exp_equiv_p): Ditto.
(insert_regs): Ditto. Change "modified" function argument to bool
and update usage accordingly.
(record_jump_cond): Remove always zero "reversed_nonequality"
function argument and update usage accordingly.
(fold_rtx): Change "changed" variable to bool.
(record_jump_equiv): Remove unneeded "reversed_nonequality" variable.
(is_dead_reg): Change return type from int to bool.
2023-06-01 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.md (adddi3, subdi3):
New RTL generation patterns implemented according to the instruc-
tion idioms described in the Xtensa ISA reference manual (p. 600).
2023-06-01 Roger Sayle <roger@nextmovesoftware.com>
Uros Bizjak <ubizjak@gmail.com>
PR target/109973
* config/i386/i386-builtin.def (__builtin_ia32_ptestz128): Use new
CODE_for_sse4_1_ptestzv2di.
(__builtin_ia32_ptestc128): Use new CODE_for_sse4_1_ptestcv2di.
(__builtin_ia32_ptestz256): Use new CODE_for_avx_ptestzv4di.
(__builtin_ia32_ptestc256): Use new CODE_for_avx_ptestcv4di.
* config/i386/i386-expand.cc (ix86_expand_branch): Use CCZmode
when expanding UNSPEC_PTEST to compare against zero.
* config/i386/i386-features.cc (scalar_chain::convert_compare):
Likewise generate CCZmode UNSPEC_PTESTs when converting comparisons.
(general_scalar_chain::convert_insn): Use CCZmode for COMPARE result.
(timode_scalar_chain::convert_insn): Use CCZmode for COMPARE result.
* config/i386/i386-protos.h (ix86_match_ptest_ccmode): Prototype.
* config/i386/i386.cc (ix86_match_ptest_ccmode): New predicate to
check for suitable matching modes for the UNSPEC_PTEST pattern.
* config/i386/sse.md (define_split): When splitting UNSPEC_MOVMSK
to UNSPEC_PTEST, preserve the FLAG_REG mode as CCZ.
(*<sse4_1>_ptest<mode>): Add asterisk to hide define_insn. Remove
":CC" mode of FLAGS_REG, instead use ix86_match_ptest_ccmode.
(<sse4_1>_ptestz<mode>): New define_expand to specify CCZ.
(<sse4_1>_ptestc<mode>): New define_expand to specify CCC.
(<sse4_1>_ptest<mode>): A define_expand using CC to preserve the
current behavior.
(*ptest<mode>_and): Specify CCZ to only perform this optimization
when only the Z flag is required.
2023-06-01 Jonathan Wakely <jwakely@redhat.com>
PR target/109954
* doc/invoke.texi (x86 Options): Fix description of -m32 option.
2023-06-01 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-simd.md (*aarch64_simd_mov<VDMOV:mode>):
Add =r,m and =r,m alternatives.
(load_pair<DREG:mode><DREG2:mode>): Likewise.
(vec_store_pair<DREG:mode><DREG2:mode>): Likewise.
2023-06-01 Pan Li <pan2.li@intel.com>
* common/config/riscv/riscv-common.cc: Add FP_16 mask to zvfhmin
and zvfh.
* config/riscv/genrvv-type-indexer.cc (valid_type): Allow FP16.
(main): Disable FP16 tuple.
* config/riscv/riscv-opts.h (MASK_VECTOR_ELEN_FP_16): New macro.
(TARGET_VECTOR_ELEN_FP_16): Ditto.
* config/riscv/riscv-vector-builtins.cc (check_required_extensions):
Add FP16.
* config/riscv/riscv-vector-builtins.def (vfloat16mf4_t): New type.
(vfloat16mf2_t): Ditto.
(vfloat16m1_t): Ditto.
(vfloat16m2_t): Ditto.
(vfloat16m4_t): Ditto.
(vfloat16m8_t): Ditto.
* config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_ELEN_FP_16):
New macro.
* config/riscv/riscv-vector-switch.def (ENTRY): Allow FP16
machine mode based on TARGET_VECTOR_ELEN_FP_16.
2023-06-01 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vector-builtins.cc (register_frm): New function.
(DEF_RVV_FRM_ENUM): New macro.
(handle_pragma_vector): Add FRM enum
* config/riscv/riscv-vector-builtins.def (DEF_RVV_FRM_ENUM): New macro.
(RNE): Ditto.
(RTZ): Ditto.
(RDN): Ditto.
(RUP): Ditto.
(RMM): Ditto.
2023-05-31 Roger Sayle <roger@nextmovesoftware.com>
Richard Sandiford <richard.sandiford@arm.com>
* fold-const-call.cc (fold_const_call_ss) <CFN_BUILT_IN_BSWAP*>:
Update call to wi::bswap.
* simplify-rtx.cc (simplify_const_unary_operation) <case BSWAP>:
Update call to wi::bswap.
* tree-ssa-ccp.cc (evaluate_stmt) <case BUILT_IN_BSWAP*>:
Update calls to wi::bswap.
* wide-int.cc (wide_int_storage::bswap): Remove/rename to...
(wi::bswap_large): New function, with revised API.
* wide-int.h (wi::bswap): New (template) function prototype.
(wide_int_storage::bswap): Remove method.
(sext_large, zext_large): Consistent indentation/line wrapping.
(bswap_large): Prototype helper function containing implementation.
(wi::bswap): New template wrapper around bswap_large.
2023-05-31 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR target/99195
* config/aarch64/aarch64-simd.md (<sur>dot_prod<vsi2qi>): Rename to...
(<sur>dot_prod<vsi2qi><vczle><vczbe>): ... This.
(usdot_prod<vsi2qi>): Rename to...
(usdot_prod<vsi2qi><vczle><vczbe>): ... This.
(aarch64_<sur>dot_lane<vsi2qi>): Rename to...
(aarch64_<sur>dot_lane<vsi2qi><vczle><vczbe>): ... This.
(aarch64_<sur>dot_laneq<vsi2qi>): Rename to...
(aarch64_<sur>dot_laneq<vsi2qi><vczle><vczbe>): ... This.
(aarch64_<DOTPROD_I8MM:sur>dot_lane<VB:isquadop><VS:vsi2qi>): Rename to...
(aarch64_<DOTPROD_I8MM:sur>dot_lane<VB:isquadop><VS:vsi2qi><vczle><vczbe>):
... This.
2023-05-31 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR target/99195
* config/aarch64/aarch64-simd.md (aarch64_sq<r>dmulh<mode>): Rename to...
(aarch64_sq<r>dmulh<mode><vczle><vczbe>): ... This.
(aarch64_sq<r>dmulh_n<mode>): Rename to...
(aarch64_sq<r>dmulh_n<mode><vczle><vczbe>): ... This.
(aarch64_sq<r>dmulh_lane<mode>): Rename to...
(aarch64_sq<r>dmulh_lane<mode><vczle><vczbe>): ... This.
(aarch64_sq<r>dmulh_laneq<mode>): Rename to...
(aarch64_sq<r>dmulh_laneq<mode><vczle><vczbe>): ... This.
(aarch64_sqrdml<SQRDMLH_AS:rdma_as>h<mode>): Rename to...
(aarch64_sqrdml<SQRDMLH_AS:rdma_as>h<mode><vczle><vczbe>): ... This.
(aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>): Rename to...
(aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode><vczle><vczbe>): ... This.
(aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>): Rename to...
(aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode><vczle><vczbe>): ... This.
2023-05-31 David Faust <david.faust@oracle.com>
* btfout.cc (btf_kind_names): New.
(btf_kind_name): New.
(btf_absolute_var_id): New utility function.
(btf_relative_var_id): Likewise.
(btf_relative_func_id): Likewise.
(btf_absolute_datasec_id): Likewise.
(btf_asm_type_ref): New.
(btf_asm_type): Update asm comments and use btf_asm_type_ref ().
(btf_asm_array): Likewise. Accept ctf_container_ref parameter.
(btf_asm_varent): Likewise.
(btf_asm_func_arg): Likewise.
(btf_asm_datasec_entry): Likewise.
(btf_asm_datasec_type): Likewise.
(btf_asm_func_type): Likewise. Add index parameter.
(btf_asm_enum_const): Likewise.
(btf_asm_sou_member): Likewise.
(output_btf_vars): Update btf_asm_* call accordingly.
(output_asm_btf_sou_fields): Likewise.
(output_asm_btf_enum_list): Likewise.
(output_asm_btf_func_args_list): Likewise.
(output_asm_btf_vlen_bytes): Likewise.
(output_btf_func_types): Add ctf_container_ref parameter.
Pass it to btf_asm_func_type.
(output_btf_datasec_types): Update btf_asm_datsec_type call similarly.
(btf_output): Update output_btf_func_types call similarly.
2023-05-31 David Faust <david.faust@oracle.com>
* btfout.cc (btf_asm_type): Add dedicated cases for BTF_KIND_ARRAY
and BTF_KIND_FWD which do not use the size/type field at all.
2023-05-31 Uros Bizjak <ubizjak@gmail.com>
* rtl.h (subreg_lowpart_p): Change return type from int to bool.
(active_insn_p): Ditto.
(in_sequence_p): Ditto.
(unshare_all_rtl): Change return type from int to void.
* emit-rtl.h (mem_expr_equal_p): Change return type from int to bool.
* emit-rtl.cc (subreg_lowpart_p): Change return type from int to bool
and adjust function body accordingly.
(mem_expr_equal_p): Ditto.
(unshare_all_rtl): Change return type from int to void
and adjust function body accordingly.
(verify_rtx_sharing): Remove unneeded return.
(active_insn_p): Change return type from int to bool
and adjust function body accordingly.
(in_sequence_p): Ditto.
2023-05-31 Uros Bizjak <ubizjak@gmail.com>
* rtl.h (true_dependence): Change return type from int to bool.
(canon_true_dependence): Ditto.
(read_dependence): Ditto.
(anti_dependence): Ditto.
(canon_anti_dependence): Ditto.
(output_dependence): Ditto.
(canon_output_dependence): Ditto.
(may_alias_p): Ditto.
* alias.h (alias_sets_conflict_p): Ditto.
(alias_sets_must_conflict_p): Ditto.
(objects_must_conflict_p): Ditto.
(nonoverlapping_memrefs_p): Ditto.
* alias.cc (rtx_equal_for_memref_p): Remove forward declaration.
(record_set): Ditto.
(base_alias_check): Ditto.
(find_base_value): Ditto.
(mems_in_disjoint_alias_sets_p): Ditto.
(get_alias_set_entry): Ditto.
(decl_for_component_ref): Ditto.
(write_dependence_p): Ditto.
(memory_modified_1): Ditto.
(mems_in_disjoint_alias_set_p): Change return type from int to bool
and adjust function body accordingly.
(alias_sets_conflict_p): Ditto.
(alias_sets_must_conflict_p): Ditto.
(objects_must_conflict_p): Ditto.
(rtx_equal_for_memref_p): Ditto.
(base_alias_check): Ditto.
(read_dependence): Ditto.
(nonoverlapping_memrefs_p): Ditto.
(true_dependence_1): Ditto.
(true_dependence): Ditto.
(canon_true_dependence): Ditto.
(write_dependence_p): Ditto.
(anti_dependence): Ditto.
(canon_anti_dependence): Ditto.
(output_dependence): Ditto.
(canon_output_dependence): Ditto.
(may_alias_p): Ditto.
(init_alias_analysis): Change "changed" variable to bool.
2023-05-31 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/autovec.md (<optab><v_double_trunc><mode>2): Change
expand into define_insn_and_split.
2023-05-31 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/vector.md: Remove FRM.
2023-05-31 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/vector.md: Remove FRM.
2023-05-31 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/vector.md: Remove FRM.
2023-05-31 Christophe Lyon <christophe.lyon@linaro.org>
PR target/110039
* config/aarch64/aarch64.md (aarch64_rev16si2_alt3): New
pattern.
2023-05-31 Richard Biener <rguenther@suse.de>
PR ipa/109983
PR tree-optimization/109143
* tree-ssa-structalias.cc (struct topo_info): Remove.
(init_topo_info): Likewise.
(free_topo_info): Likewise.
(compute_topo_order): Simplify API, put the component
with ESCAPED last so it's processed first.
(topo_visit): Adjust.
(solve_graph): Likewise.
2023-05-31 Richard Biener <rguenther@suse.de>
* tree-ssa-structalias.cc (constraint_stats::num_avoided_edges):
New.
(add_graph_edge): Count redundant edges we avoid to create.
(dump_sa_stats): Dump them.
(ipa_pta_execute): Do not dump generating constraints when
we are not dumping them.
2023-05-31 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-simd.md (*aarch64_simd_mov<VDMOV:mode>): Rewrite
output template to avoid explicit switch on which_alternative.
(*aarch64_simd_mov<VQMOV:mode>): Likewise.
(and<mode>3): Likewise.
(ior<mode>3): Likewise.
* config/aarch64/aarch64.md (*mov<mode>_aarch64): Likewise.
2023-05-31 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/predicates.md (xtensa_bit_join_operator):
New predicate.
* config/xtensa/xtensa.md (ior_op): Remove.
(*shlrd_reg): Rename from "*shlrd_reg_<code>", and add the
insn_and_split pattern of the same name to express and capture
the bit-combining operation with both sides swapped.
In addition, replace use of code iterator with new operator
predicate.
(*shlrd_const, *shlrd_per_byte):
Likewise regarding the code iterator.
2023-05-31 Cui, Lili <lili.cui@intel.com>
PR tree-optimization/110038
* params.opt: Add a limit on tree-reassoc-width.
* tree-ssa-reassoc.cc
(rewrite_expr_tree_parallel): Add width limit.
2023-05-31 Pan Li <pan2.li@intel.com>
* common/config/riscv/riscv-common.cc:
(riscv_implied_info): Add zvfh item.
(riscv_ext_version_table): Ditto.
(riscv_ext_flag_table): Ditto.
* config/riscv/riscv-opts.h (MASK_ZVFH): New macro.
(TARGET_ZVFH): Ditto.
2023-05-30 liuhongt <hongtao.liu@intel.com>
PR tree-optimization/108804
* tree-vect-patterns.cc (vect_get_range_info): Remove static.
* tree-vect-stmts.cc (vect_create_vectorized_demotion_stmts):
Add new parameter narrow_src_p.
(vectorizable_conversion): Enhance NARROW FLOAT_EXPR
vectorization by truncating to lower precision.
* tree-vectorizer.h (vect_get_range_info): New declare.
2023-05-30 Vladimir N. Makarov <vmakarov@redhat.com>
* lra-int.h (lra_update_sp_offset): Add the prototype.
* lra.cc (setup_sp_offset): Change the return type. Use
lra_update_sp_offset.
* lra-eliminations.cc (lra_update_sp_offset): New function.
(lra_process_new_insns): Push the current insn to reprocess if the
input reload changes sp offset.
2023-05-30 Uros Bizjak <ubizjak@gmail.com>
PR target/110041
* config/i386/i386-expand.cc (ix86_expand_vecop_qihi2):
Fix misleading identation.
2023-05-30 Uros Bizjak <ubizjak@gmail.com>
* rtl.h (comparison_dominates_p): Change return type from int to bool.
(condjump_p): Ditto.
(any_condjump_p): Ditto.
(any_uncondjump_p): Ditto.
(simplejump_p): Ditto.
(returnjump_p): Ditto.
(eh_returnjump_p): Ditto.
(onlyjump_p): Ditto.
(invert_jump_1): Ditto.
(invert_jump): Ditto.
(rtx_renumbered_equal_p): Ditto.
(redirect_jump_1): Ditto.
(redirect_jump): Ditto.
(condjump_in_parallel_p): Ditto.
* jump.cc (invert_exp_1): Adjust forward declaration.
(comparison_dominates_p): Change return type from int to bool
and adjust function body accordingly.
(simplejump_p): Ditto.
(condjump_p): Ditto.
(condjump_in_parallel_p): Ditto.
(any_uncondjump_p): Ditto.
(any_condjump_p): Ditto.
(returnjump_p): Ditto.
(eh_returnjump_p): Ditto.
(onlyjump_p): Ditto.
(redirect_jump_1): Ditto.
(redirect_jump): Ditto.
(invert_exp_1): Ditto.
(invert_jump_1): Ditto.
(invert_jump): Ditto.
(rtx_renumbered_equal_p): Ditto.
2023-05-30 Andrew Pinski <apinski@marvell.com>
* fold-const.cc (minmax_from_comparison): Add support for NE_EXPR.
* match.pd ((cond (cmp (convert1? x) c1) (convert2? x) c2) pattern):
Add ne as a possible cmp.
((a CMP b) ? minmax<a, c> : minmax<b, c> pattern): Likewise.
2023-05-30 Andrew Pinski <apinski@marvell.com>
* match.pd (`(a CMP CST1) ? max<a,CST2> : a`): New
pattern.
2023-05-30 Roger Sayle <roger@nextmovesoftware.com>
* simplify-rtx.cc (simplify_binary_operation_1) <AND>: Use wide-int
instead of HWI_COMPUTABLE_MODE_P and UINTVAL in transformation of
(and (extend X) C) as (zero_extend (and X C)), to also optimize
modes wider than HOST_WIDE_INT.
2023-05-30 Roger Sayle <roger@nextmovesoftware.com>
PR target/107172
* simplify-rtx.cc (simplify_const_relational_operation): Return
early if we have a MODE_CC comparison that isn't a COMPARE against
const0_rtx.
2023-05-30 Robin Dapp <rdapp@ventanamicro.com>
* config/riscv/riscv.cc (riscv_const_insns): Allow
const_vec_duplicates.
2023-05-30 liuhongt <hongtao.liu@intel.com>
PR middle-end/108938
* gimple-ssa-store-merging.cc (is_bswap_or_nop_p): New
function, cut from original find_bswap_or_nop function.
(find_bswap_or_nop): Add a new parameter, detect bswap +
rotate and save rotate result in the new parameter.
(bswap_replace): Add a new parameter to indicate rotate and
generate rotate stmt if needed.
(maybe_optimize_vector_constructor): Adjust for new rotate
parameter in the upper 2 functions.
(pass_optimize_bswap::execute): Ditto.
(imm_store_chain_info::output_merged_store): Ditto.
2023-05-30 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-simd.md (aarch64_<sur>adalp<mode>): Delete.
(aarch64_<su>adalp<mode>): New define_expand.
(*aarch64_<su>adalp<mode><vczle><vczbe>_insn): New define_insn.
(aarch64_<su>addlp<mode>): Convert to define_expand.
(*aarch64_<su>addlp<mode><vczle><vczbe>_insn): New define_insn.
* config/aarch64/iterators.md (UNSPEC_SADDLP, UNSPEC_UADDLP): Delete.
(ADALP): Likewise.
(USADDLP): Likewise.
* config/aarch64/predicates.md (vect_par_cnst_even_or_odd_half): Define.
2023-05-30 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-builtins.cc (VAR1): Move to after inclusion of
aarch64-builtin-iterators.h. Add definition to remap shadd, uhadd,
srhadd, urhadd builtin codes for standard optab ones.
* config/aarch64/aarch64-simd.md (<u>avg<mode>3_floor): Rename to...
(<su_optab>avg<mode>3_floor): ... This. Expand to RTL codes rather than
unspec.
(<u>avg<mode>3_ceil): Rename to...
(<su_optab>avg<mode>3_ceil): ... This. Expand to RTL codes rather than
unspec.
(aarch64_<su>hsub<mode>): New define_expand.
(aarch64_<sur>h<addsub><mode><vczle><vczbe>): Split into...
(*aarch64_<su>h<ADDSUB:optab><mode><vczle><vczbe>_insn): ... This...
(*aarch64_<su>rhadd<mode><vczle><vczbe>_insn): ... And this.
2023-05-30 Andreas Schwab <schwab@suse.de>
PR target/110036
* config/riscv/riscv.cc (riscv_asan_shadow_offset): Update to
match libsanitizer.
2023-05-30 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-modes.def (V16HI, V8SI, V4DI, V2TI): New modes.
* config/aarch64/aarch64-protos.h (aarch64_const_vec_rnd_cst_p):
Declare prototype.
(aarch64_const_vec_rsra_rnd_imm_p): Likewise.
* config/aarch64/aarch64-simd.md (*aarch64_simd_sra<mode>): Rename to...
(aarch64_<sra_op>sra_n<mode>_insn): ... This.
(aarch64_<sra_op>rsra_n<mode>_insn): New define_insn.
(aarch64_<sra_op>sra_n<mode>): New define_expand.
(aarch64_<sra_op>rsra_n<mode>): Likewise.
(aarch64_<sur>sra_n<mode>): Rename to...
(aarch64_<sur>sra_ndi): ... This.
* config/aarch64/aarch64.cc (aarch64_classify_vector_mode): Add
any_target_p argument.
(aarch64_extract_vec_duplicate_wide_int): Define.
(aarch64_const_vec_rsra_rnd_imm_p): Likewise.
(aarch64_const_vec_rnd_cst_p): Likewise.
(aarch64_vector_mode_supported_any_target_p): Likewise.
(TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
* config/aarch64/iterators.md (UNSPEC_SRSRA, UNSPEC_URSRA): Delete.
(VSRA): Adjust for the above.
(sur): Likewise.
(V2XWIDE): New mode_attr.
(vec_or_offset): Likewise.
(SHIFTEXTEND): Likewise.
* config/aarch64/predicates.md (aarch64_simd_rsra_rnd_imm_vec): New
predicate.
* doc/tm.texi (TARGET_VECTOR_MODE_SUPPORTED_P): Adjust description to
clarify that it applies to current target options.
(TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Document.
* doc/tm.texi.in: Regenerate.
* stor-layout.cc (mode_for_vector): Check
vector_mode_supported_any_target_p when iterating through vector modes.
* target.def (TARGET_VECTOR_MODE_SUPPORTED_P): Adjust description to
clarify that it applies to current target options.
(TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Define.
2023-05-30 Lili Cui <lili.cui@intel.com>
PR tree-optimization/98350
* tree-ssa-reassoc.cc
(rewrite_expr_tree_parallel): Rewrite this function.
(rank_ops_for_fma): New.
(reassociate_bb): Handle new function.
2023-05-30 Uros Bizjak <ubizjak@gmail.com>
* rtl.h (rtx_addr_can_trap_p): Change return type from int to bool.
(rtx_unstable_p): Ditto.
(reg_mentioned_p): Ditto.
(reg_referenced_p): Ditto.
(reg_used_between_p): Ditto.
(reg_set_between_p): Ditto.
(modified_between_p): Ditto.
(no_labels_between_p): Ditto.
(modified_in_p): Ditto.
(reg_set_p): Ditto.
(multiple_sets): Ditto.
(set_noop_p): Ditto.
(noop_move_p): Ditto.
(reg_overlap_mentioned_p): Ditto.
(dead_or_set_p): Ditto.
(dead_or_set_regno_p): Ditto.
(find_reg_fusage): Ditto.
(find_regno_fusage): Ditto.
(side_effects_p): Ditto.
(volatile_refs_p): Ditto.
(volatile_insn_p): Ditto.
(may_trap_p_1): Ditto.
(may_trap_p): Ditto.
(may_trap_or_fault_p): Ditto.
(computed_jump_p): Ditto.
(auto_inc_p): Ditto.
(loc_mentioned_in_p): Ditto.
* rtlanal.cc (computed_jump_p_1): Adjust forward declaration.
(rtx_unstable_p): Change return type from int to bool
and adjust function body accordingly.
(rtx_addr_can_trap_p): Ditto.
(reg_mentioned_p): Ditto.
(no_labels_between_p): Ditto.
(reg_used_between_p): Ditto.
(reg_referenced_p): Ditto.
(reg_set_between_p): Ditto.
(reg_set_p): Ditto.
(modified_between_p): Ditto.
(modified_in_p): Ditto.
(multiple_sets): Ditto.
(set_noop_p): Ditto.
(noop_move_p): Ditto.
(reg_overlap_mentioned_p): Ditto.
(dead_or_set_p): Ditto.
(dead_or_set_regno_p): Ditto.
(find_reg_fusage): Ditto.
(find_regno_fusage): Ditto.
(remove_node_from_insn_list): Ditto.
(volatile_insn_p): Ditto.
(volatile_refs_p): Ditto.
(side_effects_p): Ditto.
(may_trap_p_1): Ditto.
(may_trap_p): Ditto.
(may_trap_or_fault_p): Ditto.
(computed_jump_p): Ditto.
(auto_inc_p): Ditto.
(loc_mentioned_in_p): Ditto.
* combine.cc (can_combine_p): Update indirect function.
2023-05-30 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/autovec.md (<optab><mode><vconvert>2): New pattern.
* config/riscv/iterators.md: New attribute.
* config/riscv/vector-iterators.md: New attribute.
2023-05-30 From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv.md: Fix signed and unsigned comparison
warning.
2023-05-30 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/autovec.md (fnma<mode>4): New pattern.
(*fnma<mode>): Ditto.
2023-05-29 Die Li <lidie@eswincomputing.com>
* config/riscv/riscv.cc (riscv_expand_conditional_move_onesided):
Delete.
(riscv_expand_conditional_move): Reuse the TARGET_SFB_ALU expand
process for TARGET_XTHEADCONDMOV
2023-05-29 Uros Bizjak <ubizjak@gmail.com>
PR target/110021
* config/i386/i386-expand.cc (ix86_expand_vecop_qihi2): Also require
TARGET_AVX512BW to generate truncv16hiv16qi2.
2023-05-29 Jivan Hakobyan <jivanhakobyan9@gmail.com>
* config/riscv/riscv.md (and<mode>3): New expander.
(*and<mode>3) New pattern.
* config/riscv/predicates.md (arith_operand_or_mode_mask): New
predicate.
2023-05-29 Pan Li <pan2.li@intel.com>
* config/riscv/riscv-v.cc (emit_vlmax_insn): Remove unnecessary
comments and rename local variables.
(emit_nonvlmax_insn): Diito.
(emit_vlmax_merge_insn): Ditto.
(emit_vlmax_cmp_insn): Ditto.
(emit_vlmax_cmp_mu_insn): Ditto.
(emit_scalar_move_insn): Ditto.
2023-05-29 Pan Li <pan2.li@intel.com>
* config/riscv/riscv-v.cc (emit_vlmax_insn): Eliminate the
magic number.
(emit_nonvlmax_insn): Ditto.
(emit_vlmax_merge_insn): Ditto.
(emit_vlmax_cmp_insn): Ditto.
(emit_vlmax_cmp_mu_insn): Ditto.
(expand_vec_series): Ditto.
2023-05-29 Pan Li <pan2.li@intel.com>
* config/riscv/riscv-protos.h (enum insn_type): New type.
* config/riscv/riscv-v.cc (RVV_INSN_OPERANDS_MAX): New macro.
(rvv_builder::can_duplicate_repeating_sequence_p): Align the referenced
class member.
(rvv_builder::get_merged_repeating_sequence): Ditto.
(rvv_builder::repeating_sequence_use_merge_profitable_p): New function
to evaluate the optimization cost.
(rvv_builder::get_merge_scalar_mask): New function to get the merge
mask.
(emit_scalar_move_insn): New function to emit vmv.s.x.
(emit_vlmax_integer_move_insn): New function to emit vlmax vmv.v.x.
(emit_nonvlmax_integer_move_insn): New function to emit nonvlmax
vmv.v.x.
(get_repeating_sequence_dup_machine_mode): New function to get the dup
machine mode.
(expand_vector_init_merge_repeating_sequence): New function to perform
the optimization.
(expand_vec_init): Add this vector init optimization.
* config/riscv/riscv.h (BITS_PER_WORD): New macro.
2023-05-29 Eric Botcazou <ebotcazou@adacore.com>
* tree-ssa-loop-manip.cc (create_iv): Try harder to find a SLOC to
put onto the increment when it is inserted after the position.
2023-05-29 Eric Botcazou <ebotcazou@adacore.com>
* match.pd ((T)P - (T)(P + A) -> -(T) A): Avoid artificial overflow
on constants.
2023-05-29 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vsetvl.cc (source_equal_p): Fix ICE.
2023-05-29 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/autovec.md (fma<mode>4): New pattern.
(*fma<mode>): Ditto.
* config/riscv/riscv-protos.h (enum insn_type): New enum.
(emit_vlmax_ternary_insn): New function.
* config/riscv/riscv-v.cc (emit_vlmax_ternary_insn): Ditto.
2023-05-29 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/vector.md: Fix vimuladd instruction bug.
2023-05-29 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv.cc (global_state_unknown_p): New function.
(riscv_mode_after): Fix incorrect VXM.
2023-05-29 Pan Li <pan2.li@intel.com>
* common/config/riscv/riscv-common.cc:
(riscv_implied_info): Add zvfhmin item.
(riscv_ext_version_table): Ditto.
(riscv_ext_flag_table): Ditto.
* config/riscv/riscv-opts.h (MASK_ZVFHMIN): New macro.
(TARGET_ZFHMIN): Align indent.
(TARGET_ZFH): Ditto.
(TARGET_ZVFHMIN): New macro.
2023-05-27 liuhongt <hongtao.liu@intel.com>
PR target/100711
* config/i386/sse.md (*andnot<mode>3): Extend below splitter
to VI_AVX2 to cover more modes.
2023-05-27 liuhongt <hongtao.liu@intel.com>
* config/i386/x86-tune.def (X86_TUNE_AVOID_FALSE_DEP_FOR_BMI):
Remove ATOM and ICELAKE(and later) core processors.
2023-05-26 Robin Dapp <rdapp@ventanamicro.com>
* config/riscv/autovec.md (<optab><mode>2): Add vneg/vnot.
(abs<mode>2): Add.
* config/riscv/riscv-protos.h (emit_vlmax_masked_mu_insn):
Declare.
* config/riscv/riscv-v.cc (emit_vlmax_masked_mu_insn): New
function.
2023-05-26 Robin Dapp <rdapp@ventanamicro.com>
Juzhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/autovec.md (<optab><v_double_trunc><mode>2): New
expander.
(<optab><v_quad_trunc><mode>2): Dito.
(<optab><v_oct_trunc><mode>2): Dito.
(trunc<mode><v_double_trunc>2): Dito.
(trunc<mode><v_quad_trunc>2): Dito.
(trunc<mode><v_oct_trunc>2): Dito.
* config/riscv/riscv-protos.h (vectorize_related_mode): Define.
(autovectorize_vector_modes): Define.
* config/riscv/riscv-v.cc (vectorize_related_mode): Implement
hook.
(autovectorize_vector_modes): Implement hook.
* config/riscv/riscv.cc (riscv_autovectorize_vector_modes):
Implement target hook.
(riscv_vectorize_related_mode): Implement target hook.
(TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES): Define.
(TARGET_VECTORIZE_RELATED_MODE): Define.
* config/riscv/vector-iterators.md: Add lowercase versions of
mode_attr iterators.
2023-05-26 Andrew Stubbs <ams@codesourcery.com>
Tobias Burnus <tobias@codesourcery.com>
* config/gcn/gcn-hsa.h (XNACKOPT): New macro.
(ASM_SPEC): Use XNACKOPT.
* config/gcn/gcn-opts.h (enum sram_ecc_type): Rename to ...
(enum hsaco_attr_type): ... this, and generalize the names.
(TARGET_XNACK): New macro.
* config/gcn/gcn.cc (gcn_option_override): Update to sorry for all
but -mxnack=off.
(output_file_start): Update xnack handling.
(gcn_hsa_declare_function_name): Use TARGET_XNACK.
* config/gcn/gcn.opt (-mxnack): Add the "on/off/any" syntax.
(sram_ecc_type): Rename to ...
(hsaco_attr_type: ... this.)
* config/gcn/mkoffload.cc (SET_XNACK_ANY): New macro.
(TEST_XNACK): Delete.
(TEST_XNACK_ANY): New macro.
(TEST_XNACK_ON): New macro.
(main): Support the new -mxnack=on/off/any syntax.
* doc/invoke.texi (-mxnack): Update for new syntax.
2023-05-26 Andrew Pinski <apinski@marvell.com>
* genmatch.cc (emit_debug_printf): New function.
(dt_simplify::gen_1): Emit printf into the code
before the `return true` or returning the folded result
instead of emitting it always.
2023-05-26 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa-protos.h
(xtensa_expand_block_set_unrolled_loop,
xtensa_expand_block_set_small_loop): Remove.
(xtensa_expand_block_set): New prototype.
* config/xtensa/xtensa.cc
(xtensa_expand_block_set_libcall): New subfunction.
(xtensa_expand_block_set_unrolled_loop,
xtensa_expand_block_set_small_loop): Rewrite as subfunctions.
(xtensa_expand_block_set): New function that calls the above
subfunctions.
* config/xtensa/xtensa.md (memsetsi): Change to invoke only
xtensa_expand_block_set().
2023-05-26 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa-protos.h (xtensa_m1_or_1_thru_15):
New prototype.
* config/xtensa/xtensa.cc (xtensa_m1_or_1_thru_15):
New function.
* config/xtensa/constraints.md (O):
Change to use the above function.
* config/xtensa/xtensa.md (*subsi3_from_const):
New insn_and_split pattern.
2023-05-26 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.md (*extzvsi-1bit_ashlsi3):
Retract excessive line folding, and correct the value of
the "length" insn attribute related to TARGET_DENSITY.
(*extzvsi-1bit_addsubx): Ditto.
2023-05-26 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386-expand.cc (ix86_expand_vecop_qihi):
Do not disable call to ix86_expand_vecop_qihi2.
2023-05-26 liuhongt <hongtao.liu@intel.com>
PR target/109610
PR target/109858
* ira-costs.cc (scan_one_insn): Only use NO_REGS in cost
calculation when !hard_regno_mode_ok for GENERAL_REGS and
mode, otherwise still use GENERAL_REGS.
2023-05-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv.cc (vector_zero_call_used_regs): Add
explict VL and drop VL in ops.
2023-05-25 Jin Ma <jinma@linux.alibaba.com>
* sched-deps.cc (sched_macro_fuse_insns): Insns should not be fusion
in different BB blocks.
2023-05-25 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386-expand.cc (ix86_expand_vecop_qihi2):
Rewrite to expand to 2x-wider (e.g. V16QI -> V16HImode)
instructions when available. Emulate truncation via
ix86_expand_vec_perm_const_1 when native truncate insn
is not available.
(ix86_expand_vecop_qihi_partial) <case MULT>: Use pmovzx
when available. Trivially rename some variables.
(ix86_expand_vecop_qihi): Unconditionally call ix86_expand_vecop_qihi2.
* config/i386/i386.cc (ix86_multiplication_cost): Rewrite cost
calculation of V*QImode emulations to account for generation of
2x-wider mode instructions.
(ix86_shift_rotate_cost): Update cost calculation of V*QImode
emulations to account for generation of 2x-wider mode instructions.
2023-05-25 Georg-Johann Lay <avr@gjlay.de>
PR target/104327
* config/avr/avr.cc (avr_can_inline_p): New static function.
(TARGET_CAN_INLINE_P): Define to that function.
2023-05-25 Georg-Johann Lay <avr@gjlay.de>
PR target/82931
* config/avr/avr.md (*movbitqi.0): Rename to *movbit<mode>.0-6.
Handle any bit position and use mode QISI.
* config/avr/avr.cc (avr_rtx_costs_1) [IOR]: Return a cost
of 2 insns for bit-transfer of respective style.
2023-05-25 Christophe Lyon <christophe.lyon@linaro.org>
* config/arm/iterators.md (MVE_6): Remove.
* config/arm/mve.md: Replace MVE_6 with MVE_5.
2023-05-25 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Richard Sandiford <richard.sandiford@arm.com>
* tree-vect-loop-manip.cc (vect_adjust_loop_lens_control): New
function.
(vect_set_loop_controls_directly): Add decrement IV support.
(vect_set_loop_condition_partial_vectors): Ditto.
* tree-vect-loop.cc (_loop_vec_info::_loop_vec_info): New
variable.
* tree-vectorizer.h (LOOP_VINFO_USING_DECREMENTING_IV_P): New
macro.
2023-05-25 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR target/99195
* config/aarch64/aarch64-simd.md (aarch64_fcadd<rot><mode>): Rename to...
(aarch64_fcadd<rot><mode><vczle><vczbe>): ... This.
Fix canonicalization of PLUS operands.
(aarch64_fcmla<rot><mode>): Rename to...
(aarch64_fcmla<rot><mode><vczle><vczbe>): ... This.
Fix canonicalization of PLUS operands.
(aarch64_fcmla_lane<rot><mode>): Rename to...
(aarch64_fcmla_lane<rot><mode><vczle><vczbe>): ... This.
Fix canonicalization of PLUS operands.
(aarch64_fcmla_laneq<rot>v4hf): Rename to...
(aarch64_fcmla_laneq<rot>v4hf<vczle><vczbe>): ... This.
Fix canonicalization of PLUS operands.
(aarch64_fcmlaq_lane<rot><mode>): Fix canonicalization of PLUS operands.
2023-05-25 Chris Sidebottom <chris.sidebottom@arm.com>
* config/arm/arm.md (rbitsi2): Rename to...
(arm_rbit): ... This.
(ctzsi2): Adjust for the above.
(arm_rev16si2): Convert to define_expand.
(arm_rev16si2_alt1): New pattern.
(arm_rev16si2_alt): Rename to...
(*arm_rev16si2_alt2): ... This.
* config/arm/arm_acle.h (__ror, __rorl, __rorll, __clz, __clzl, __clzll,
__cls, __clsl, __clsll, __revsh, __rev, __revl, __revll, __rev16,
__rev16l, __rev16ll, __rbit, __rbitl, __rbitll): Define intrinsics.
* config/arm/arm_acle_builtins.def (rbit, rev16si2): Define builtins.
2023-05-25 Alex Coplan <alex.coplan@arm.com>
PR target/109800
* config/arm/arm.md (movdf): Generate temporary pseudo in DImode
instead of DFmode.
* config/arm/vfp.md (no_literal_pool_df_immediate): Rather than punning an
lvalue DFmode pseudo into DImode, use a DImode pseudo and pun it into
DFmode as an rvalue.
2023-05-25 Richard Biener <rguenther@suse.de>
PR target/109955
* tree-vect-stmts.cc (vectorizable_condition): For
embedded comparisons also handle the case when the target
only provides vec_cmp and vcond_mask.
2023-05-25 Claudiu Zissulescu <claziss@gmail.com>
* config/arc/arc.cc (arc_call_tls_get_addr): Simplify access using
TLS Local Dynamic.
2023-05-25 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
* config/aarch64/aarch64.cc (scalar_move_insn_p): New function.
(seq_cost_ignoring_scalar_moves): Likewise.
(aarch64_expand_vector_init): Call seq_cost_ignoring_scalar_moves.
2023-05-25 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/arm_neon.h (vcage_f64): Reimplement with builtins.
(vcage_f32): Likewise.
(vcages_f32): Likewise.
(vcageq_f32): Likewise.
(vcaged_f64): Likewise.
(vcageq_f64): Likewise.
(vcagts_f32): Likewise.
(vcagt_f32): Likewise.
(vcagt_f64): Likewise.
(vcagtq_f32): Likewise.
(vcagtd_f64): Likewise.
(vcagtq_f64): Likewise.
(vcale_f32): Likewise.
(vcale_f64): Likewise.
(vcaled_f64): Likewise.
(vcales_f32): Likewise.
(vcaleq_f32): Likewise.
(vcaleq_f64): Likewise.
(vcalt_f32): Likewise.
(vcalt_f64): Likewise.
(vcaltd_f64): Likewise.
(vcaltq_f32): Likewise.
(vcaltq_f64): Likewise.
(vcalts_f32): Likewise.
2023-05-25 Hu, Lin1 <lin1.hu@intel.com>
PR target/109173
PR target/109174
* config/i386/avx512bwintrin.h (_mm512_srli_epi16): Change type from
int to const int or const int to const unsigned int.
(_mm512_mask_srli_epi16): Ditto.
(_mm512_slli_epi16): Ditto.
(_mm512_mask_slli_epi16): Ditto.
(_mm512_maskz_slli_epi16): Ditto.
(_mm512_srai_epi16): Ditto.
(_mm512_mask_srai_epi16): Ditto.
(_mm512_maskz_srai_epi16): Ditto.
* config/i386/avx512fintrin.h (_mm512_slli_epi64): Ditto.
(_mm512_mask_slli_epi64): Ditto.
(_mm512_maskz_slli_epi64): Ditto.
(_mm512_srli_epi64): Ditto.
(_mm512_mask_srli_epi64): Ditto.
(_mm512_maskz_srli_epi64): Ditto.
(_mm512_srai_epi64): Ditto.
(_mm512_mask_srai_epi64): Ditto.
(_mm512_maskz_srai_epi64): Ditto.
(_mm512_slli_epi32): Ditto.
(_mm512_mask_slli_epi32): Ditto.
(_mm512_maskz_slli_epi32): Ditto.
(_mm512_srli_epi32): Ditto.
(_mm512_mask_srli_epi32): Ditto.
(_mm512_maskz_srli_epi32): Ditto.
(_mm512_srai_epi32): Ditto.
(_mm512_mask_srai_epi32): Ditto.
(_mm512_maskz_srai_epi32): Ditto.
* config/i386/avx512vlbwintrin.h (_mm256_mask_srai_epi16): Ditto.
(_mm256_maskz_srai_epi16): Ditto.
(_mm_mask_srai_epi16): Ditto.
(_mm_maskz_srai_epi16): Ditto.
(_mm256_mask_slli_epi16): Ditto.
(_mm256_maskz_slli_epi16): Ditto.
(_mm_mask_slli_epi16): Ditto.
(_mm_maskz_slli_epi16): Ditto.
(_mm_maskz_srli_epi16): Ditto.
* config/i386/avx512vlintrin.h (_mm256_mask_srli_epi32): Ditto.
(_mm256_maskz_srli_epi32): Ditto.
(_mm_mask_srli_epi32): Ditto.
(_mm_maskz_srli_epi32): Ditto.
(_mm256_mask_srli_epi64): Ditto.
(_mm256_maskz_srli_epi64): Ditto.
(_mm_mask_srli_epi64): Ditto.
(_mm_maskz_srli_epi64): Ditto.
(_mm256_mask_srai_epi32): Ditto.
(_mm256_maskz_srai_epi32): Ditto.
(_mm_mask_srai_epi32): Ditto.
(_mm_maskz_srai_epi32): Ditto.
(_mm256_srai_epi64): Ditto.
(_mm256_mask_srai_epi64): Ditto.
(_mm256_maskz_srai_epi64): Ditto.
(_mm_srai_epi64): Ditto.
(_mm_mask_srai_epi64): Ditto.
(_mm_maskz_srai_epi64): Ditto.
(_mm_mask_slli_epi32): Ditto.
(_mm_maskz_slli_epi32): Ditto.
(_mm_mask_slli_epi64): Ditto.
(_mm_maskz_slli_epi64): Ditto.
(_mm256_mask_slli_epi32): Ditto.
(_mm256_maskz_slli_epi32): Ditto.
(_mm256_mask_slli_epi64): Ditto.
(_mm256_maskz_slli_epi64): Ditto.
2023-05-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/vector.md: Remove FRM_REGNUM dependency in rtz
instructions.
2023-05-25 Aldy Hernandez <aldyh@redhat.com>
* data-streamer-in.cc (streamer_read_value_range): Handle NANs.
* data-streamer-out.cc (streamer_write_vrange): Same.
* value-range.h (class vrange): Make streamer_write_vrange a friend.
2023-05-25 Aldy Hernandez <aldyh@redhat.com>
* value-query.cc (range_query::get_tree_range): Set NAN directly
if necessary.
* value-range.cc (frange::set): Assert that bounds are not NAN.
2023-05-25 Aldy Hernandez <aldyh@redhat.com>
* value-range.cc (add_vrange): Handle known NANs.
2023-05-25 Aldy Hernandez <aldyh@redhat.com>
* value-range.h (frange::set_nan): New.
2023-05-25 Alexandre Oliva <oliva@adacore.com>
PR target/100106
* emit-rtl.cc (validate_subreg): Reject a SUBREG of a MEM that
requires stricter alignment than MEM's.
2023-05-24 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/107822
PR tree-optimization/107986
* Makefile.in (OBJS): Add gimple-range-phi.o.
* gimple-range-cache.h (ranger_cache::m_estimate): New
phi_analyzer pointer member.
* gimple-range-fold.cc (fold_using_range::range_of_phi): Use
phi_analyzer if no loop info is available.
* gimple-range-phi.cc: New file.
* gimple-range-phi.h: New file.
* tree-vrp.cc (execute_ranger_vrp): Utililze a phi_analyzer.
2023-05-24 Andrew MacLeod <amacleod@redhat.com>
* gimple-range-fold.cc (fur_list::fur_list): Add range_query param
to contructors.
(fold_range): Add range_query parameter.
(fur_relation::fur_relation): New.
(fur_relation::trio): New.
(fur_relation::register_relation): New.
(fold_relations): New.
* gimple-range-fold.h (fold_range): Adjust prototypes.
(fold_relations): New.
2023-05-24 Andrew MacLeod <amacleod@redhat.com>
* gimple-range-cache.cc (ssa_cache::range_of_expr): New.
* gimple-range-cache.h (class ssa_cache): Inherit from range_query.
(ranger_cache::const_query): New.
* gimple-range.cc (gimple_ranger::const_query): New.
* gimple-range.h (gimple_ranger::const_query): New prototype.
2023-05-24 Andrew MacLeod <amacleod@redhat.com>
* gimple-range-cache.cc (ssa_cache::dump): Use get_range.
(ssa_cache::dump_range_query): Delete.
(ssa_lazy_cache::dump_range_query): Delete.
(ssa_lazy_cache::get_range): Move from header file.
(ssa_lazy_cache::clear_range): ditto.
(ssa_lazy_cache::clear): Ditto.
* gimple-range-cache.h (class ssa_cache): Virtualize.
(class ssa_lazy_cache): Inherit and virtualize.
2023-05-24 Aldy Hernandez <aldyh@redhat.com>
* value-range.h (vrange::kind): Remove.
2023-05-24 Roger Sayle <roger@nextmovesoftware.com>
PR middle-end/109840
* match.pd <popcount optimizations>: Preserve zero-extension when
optimizing popcount((T)bswap(x)) and popcount((T)rotate(x,y)) as
popcount((T)x), so the popcount's argument keeps the same type.
<parity optimizations>: Likewise preserve extensions when
simplifying parity((T)bswap(x)) and parity((T)rotate(x,y)) as
parity((T)x), so that the parity's argument type is the same.
2023-05-24 Aldy Hernandez <aldyh@redhat.com>
* ipa-cp.cc (ipa_value_range_from_jfunc): Use new ipa_vr API.
(ipcp_store_vr_results): Same.
* ipa-prop.cc (ipa_vr::ipa_vr): New.
(ipa_vr::get_vrange): New.
(ipa_vr::set_unknown): New.
(ipa_vr::streamer_read): New.
(ipa_vr::streamer_write): New.
(write_ipcp_transformation_info): Use new ipa_vr API.
(read_ipcp_transformation_info): Same.
(ipa_vr::nonzero_p): Delete.
(ipcp_update_vr): Use new ipa_vr API.
* ipa-prop.h (class ipa_vr): Provide an API and hide internals.
* ipa-sra.cc (zap_useless_ipcp_results): Use new ipa_vr API.
2023-05-24 Jan-Benedict Glaw <jbglaw@lug-owl.de>
* config/mcore/mcore.cc (output_inline_const) Make buffer smaller to
silence overflow warnings later on.
2023-05-24 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386-expand.cc (ix86_expand_vecop_qihi2):
Remove handling of V8QImode.
* config/i386/mmx.md (v<insn>v8qi3): Move from sse.md.
Call ix86_expand_vecop_qihi_partial. Enable for TARGET_MMX_WITH_SSE.
(v<insn>v4qi3): Ditto.
* config/i386/sse.md (v<insn>v8qi3): Remove.
2023-05-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR target/99195
* config/aarch64/aarch64-simd.md (aarch64_simd_lshr<mode>): Rename to...
(aarch64_simd_lshr<mode><vczle><vczbe>): ... This.
(aarch64_simd_ashr<mode>): Rename to...
(aarch64_simd_ashr<mode><vczle><vczbe>): ... This.
(aarch64_simd_imm_shl<mode>): Rename to...
(aarch64_simd_imm_shl<mode><vczle><vczbe>): ... This.
(aarch64_simd_reg_sshl<mode>): Rename to...
(aarch64_simd_reg_sshl<mode><vczle><vczbe>): ... This.
(aarch64_simd_reg_shl<mode>_unsigned): Rename to...
(aarch64_simd_reg_shl<mode>_unsigned<vczle><vczbe>): ... This.
(aarch64_simd_reg_shl<mode>_signed): Rename to...
(aarch64_simd_reg_shl<mode>_signed<vczle><vczbe>): ... This.
(vec_shr_<mode>): Rename to...
(vec_shr_<mode><vczle><vczbe>): ... This.
(aarch64_<sur>shl<mode>): Rename to...
(aarch64_<sur>shl<mode><vczle><vczbe>): ... This.
(aarch64_<sur>q<r>shl<mode>): Rename to...
(aarch64_<sur>q<r>shl<mode><vczle><vczbe>): ... This.
2023-05-24 Richard Biener <rguenther@suse.de>
PR target/109944
* config/i386/i386-expand.cc (ix86_expand_vector_init_general):
Perform final vector composition using
ix86_expand_vector_init_general instead of setting
the highpart and lowpart which causes spilling.
2023-05-24 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/109695
* gimple-range-cache.cc (ranger_cache::get_global_range): Add
changed param.
* gimple-range-cache.h (ranger_cache::get_global_range): Ditto.
* gimple-range.cc (gimple_ranger::range_of_stmt): Pass changed
flag to set_global_range.
(gimple_ranger::prefill_stmt_dependencies): Ditto.
2023-05-24 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/109695
* gimple-range-cache.cc (temporal_cache::temporal_value): Return
a positive int.
(temporal_cache::current_p): Check always_current method.
(temporal_cache::set_always_current): Add param and set value
appropriately.
(temporal_cache::always_current_p): New.
(ranger_cache::get_global_range): Adjust.
(ranger_cache::set_global_range): set always current first.
2023-05-24 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/109695
* gimple-range-cache.cc (ranger_cache::get_global_range): Call
fold_range with global query to choose an initial value.
2023-05-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-protos.h (enum frm_field_enum): Add FRM_
prefix.
2023-05-24 Richard Biener <rguenther@suse.de>
PR tree-optimization/109849
* tree-ssa-pre.cc (do_hoist_insertion): Do not intersect
expressions but take the first sets.
2023-05-24 Gaius Mulley <gaiusmod2@gmail.com>
PR modula2/109952
* doc/gm2.texi (High procedure function): New node.
(Using): New menu entry for High procedure function.
2023-05-24 Richard Sandiford <richard.sandiford@arm.com>
PR rtl-optimization/109940
* early-remat.cc (postorder_index): Rename to...
(rpo_index): ...this.
(compare_candidates): Sort by decreasing rpo_index rather than
increasing postorder_index.
(early_remat::sort_candidates): Calculate the forward RPO from
DF_FORWARD.
(early_remat::local_phase): Follow forward RPO using DF_FORWARD,
rather than DF_BACKWARD in reverse.
2023-05-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR target/109939
* config/arm/arm-builtins.cc (SAT_BINOP_UNSIGNED_IMM_QUALIFIERS): Use
qualifier_none for the return operand.
2023-05-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/autovec.md (<optab><mode>3): New pattern.
(one_cmpl<mode>2): Ditto.
(*<optab>not<mode>): Ditto.
(*n<optab><mode>): Ditto.
* config/riscv/riscv-v.cc (expand_vec_cmp_float): Change to
one_cmpl.
2023-05-24 Kewen Lin <linkw@linux.ibm.com>
* tree-vect-slp.cc (vect_transform_slp_perm_load_1): Adjust the
calculation on n_perms by considering nvectors_per_build.
2023-05-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
Richard Sandiford <richard.sandiford@arm.com>
* config/riscv/autovec.md (@vcond_mask_<mode><vm>): New pattern.
(vec_cmp<mode><vm>): New pattern.
(vec_cmpu<mode><vm>): New pattern.
(vcond<V:mode><VI:mode>): New pattern.
(vcondu<V:mode><VI:mode>): New pattern.
* config/riscv/riscv-protos.h (enum insn_type): Add new enum.
(emit_vlmax_merge_insn): New function.
(emit_vlmax_cmp_insn): Ditto.
(emit_vlmax_cmp_mu_insn): Ditto.
(expand_vec_cmp): Ditto.
(expand_vec_cmp_float): Ditto.
(expand_vcond): Ditto.
* config/riscv/riscv-v.cc (emit_vlmax_merge_insn): Ditto.
(emit_vlmax_cmp_insn): Ditto.
(emit_vlmax_cmp_mu_insn): Ditto.
(get_cmp_insn_code): Ditto.
(expand_vec_cmp): Ditto.
(expand_vec_cmp_float): Ditto.
(expand_vcond): Ditto.
2023-05-24 Pan Li <pan2.li@intel.com>
* config/riscv/genrvv-type-indexer.cc (main): Add
unsigned_eew*_lmul1_interpret for indexer.
* config/riscv/riscv-vector-builtins-functions.def (vreinterpret):
Register vuint*m1_t interpret function.
* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_UNSIGNED_EEW8_LMUL1_INTERPRET_OPS):
New macro for vuint8m1_t.
(DEF_RVV_UNSIGNED_EEW16_LMUL1_INTERPRET_OPS): Likewise.
(DEF_RVV_UNSIGNED_EEW32_LMUL1_INTERPRET_OPS): Likewise.
(DEF_RVV_UNSIGNED_EEW64_LMUL1_INTERPRET_OPS): Likewise.
(vbool1_t): Add to unsigned_eew*_interpret_ops.
(vbool2_t): Likewise.
(vbool4_t): Likewise.
(vbool8_t): Likewise.
(vbool16_t): Likewise.
(vbool32_t): Likewise.
(vbool64_t): Likewise.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_UNSIGNED_EEW8_LMUL1_INTERPRET_OPS):
New macro for vuint*m1_t.
(DEF_RVV_UNSIGNED_EEW16_LMUL1_INTERPRET_OPS): Likewise.
(DEF_RVV_UNSIGNED_EEW32_LMUL1_INTERPRET_OPS): Likewise.
(DEF_RVV_UNSIGNED_EEW64_LMUL1_INTERPRET_OPS): Likewise.
(required_extensions_p): Add vuint*m1_t interpret case.
* config/riscv/riscv-vector-builtins.def (unsigned_eew8_lmul1_interpret):
Add vuint*m1_t interpret to base type.
(unsigned_eew16_lmul1_interpret): Likewise.
(unsigned_eew32_lmul1_interpret): Likewise.
(unsigned_eew64_lmul1_interpret): Likewise.
2023-05-24 Pan Li <pan2.li@intel.com>
* config/riscv/genrvv-type-indexer.cc (EEW_SIZE_LIST): New macro
for the eew size list.
(LMUL1_LOG2): New macro for the log2 value of lmul=1.
(main): Add signed_eew*_lmul1_interpret for indexer.
* config/riscv/riscv-vector-builtins-functions.def (vreinterpret):
Register vint*m1_t interpret function.
* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_SIGNED_EEW8_LMUL1_INTERPRET_OPS):
New macro for vint8m1_t.
(DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS): Likewise.
(DEF_RVV_SIGNED_EEW32_LMUL1_INTERPRET_OPS): Likewise.
(DEF_RVV_SIGNED_EEW64_LMUL1_INTERPRET_OPS): Likewise.
(vbool1_t): Add to signed_eew*_interpret_ops.
(vbool2_t): Likewise.
(vbool4_t): Likewise.
(vbool8_t): Likewise.
(vbool16_t): Likewise.
(vbool32_t): Likewise.
(vbool64_t): Likewise.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_SIGNED_EEW8_LMUL1_INTERPRET_OPS):
New macro for vint*m1_t.
(DEF_RVV_SIGNED_EEW16_LMUL1_INTERPRET_OPS): Likewise.
(DEF_RVV_SIGNED_EEW32_LMUL1_INTERPRET_OPS): Likewise.
(DEF_RVV_SIGNED_EEW64_LMUL1_INTERPRET_OPS): Likewise.
(required_extensions_p): Add vint8m1_t interpret case.
* config/riscv/riscv-vector-builtins.def (signed_eew8_lmul1_interpret):
Add vint*m1_t interpret to base type.
(signed_eew16_lmul1_interpret): Likewise.
(signed_eew32_lmul1_interpret): Likewise.
(signed_eew64_lmul1_interpret): Likewise.
2023-05-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/autovec.md: Adjust for new interface.
* config/riscv/riscv-protos.h (emit_vlmax_insn): Add VL operand.
(emit_nonvlmax_insn): Add AVL operand.
* config/riscv/riscv-v.cc (emit_vlmax_insn): Add VL operand.
(emit_nonvlmax_insn): Add AVL operand.
(sew64_scalar_helper): Adjust for new interface.
(expand_tuple_move): Ditto.
* config/riscv/vector.md: Ditto.
2023-05-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-v.cc (expand_vec_series): Remove magic number.
(expand_const_vector): Ditto.
(legitimize_move): Ditto.
(sew64_scalar_helper): Ditto.
(expand_tuple_move): Ditto.
(expand_vector_init_insert_elems): Ditto.
* config/riscv/riscv.cc (vector_zero_call_used_regs): Ditto.
2023-05-24 liuhongt <hongtao.liu@intel.com>
PR target/109900
* config/i386/i386.cc (ix86_gimple_fold_builtin): Fold
_mm{,256,512}_abs_{epi8,epi16,epi32,epi64} and
_mm_abs_{pi8,pi16,pi32} into gimple ABS_EXPR.
(ix86_masked_all_ones): Handle 64-bit mask.
* config/i386/i386-builtin.def: Replace icode of related
non-mask simd abs builtins with CODE_FOR_nothing.
2023-05-23 Martin Uecker <uecker@tugraz.at>
PR c/109450
* function.cc (gimplify_parm_type): Remove function.
(gimplify_parameters): Call gimplify_type_sizes.
2023-05-23 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.md (*addsubx): Rename from '*addx',
and change to also accept '*subx' pattern.
(*subx): Remove.
2023-05-23 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/predicates.md (addsub_operator): New.
* config/xtensa/xtensa.md (*extzvsi-1bit_ashlsi3,
*extzvsi-1bit_addsubx): New insn_and_split patterns.
* config/xtensa/xtensa.cc (xtensa_rtx_costs):
Add a special case about ifcvt 'noce_try_cmove()' to handle
constant loads that do not fit into signed 12 bits in the
patterns added above.
2023-05-23 Richard Biener <rguenther@suse.de>
PR tree-optimization/109747
* tree-vect-slp.cc (vect_prologue_cost_for_slp): Pass down
the SLP node only once to the cost hook.
2023-05-23 Georg-Johann Lay <avr@gjlay.de>
* config/avr/avr.cc (avr_insn_cost): New static function.
(TARGET_INSN_COST): Define to that function.
2023-05-23 Richard Biener <rguenther@suse.de>
PR target/109944
* config/i386/i386.cc (ix86_vector_costs::add_stmt_cost):
For vector construction or splats apply GPR->XMM move
costing. QImode memory can be handled directly only
with SSE4.1 pinsrb.
2023-05-23 Richard Biener <rguenther@suse.de>
PR tree-optimization/108752
* tree-vect-stmts.cc (vectorizable_operation): For bit
operations with generic word_mode vectors do not cost
an extra stmt. For plus, minus and negate also cost the
constant materialization.
2023-05-23 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386-expand.cc (ix86_expand_vecop_qihi_partial):
Call ix86_expand_vec_shift_qihi_constant for shifts
with constant count operand.
* config/i386/i386.cc (ix86_shift_rotate_cost):
Handle V4QImode and V8QImode.
* config/i386/mmx.md (<insn>v8qi3): New insn pattern.
(<insn>v4qi3): Ditto.
2023-05-23 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/vector.md: Add mode.
2023-05-23 Aldy Hernandez <aldyh@redhat.com>
PR tree-optimization/109934
* value-range.cc (irange::invert): Remove buggy special case.
2023-05-23 Richard Biener <rguenther@suse.de>
* tree-ssa-pre.cc (compute_antic_aux): Dump the correct
ANTIC_OUT.
2023-05-23 Richard Sandiford <richard.sandiford@arm.com>
PR target/109632
* config/aarch64/aarch64.cc (aarch64_modes_tieable_p): Allow
subregs between any scalars that are 64 bits or smaller.
* config/aarch64/iterators.md (SUBDI_BITS): New int iterator.
(bits_etype): New int attribute.
* config/aarch64/aarch64.md (*insv_reg<mode>_<SUBDI_BITS>)
(*aarch64_bfi<GPI:mode><ALLX:mode>_<SUBDI_BITS>): New patterns.
(*aarch64_bfidi<ALLX:mode>_subreg_<SUBDI_BITS>): Likewise.
2023-05-23 Richard Sandiford <richard.sandiford@arm.com>
* doc/md.texi: Document that <FOO> can be used to refer to the
numerical value of an int iterator FOO. Tweak other parts of
the int iterator documentation.
* read-rtl.cc (iterator_group::has_self_attr): New field.
(map_attr_string): When has_self_attr is true, make <FOO>
expand to the current value of iterator FOO.
(initialize_iterators): Set has_self_attr for int iterators.
2023-05-23 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/autovec.md: Refactor the framework of RVV auto-vectorization.
* config/riscv/riscv-protos.h (RVV_MISC_OP_NUM): Ditto.
(RVV_UNOP_NUM): New macro.
(RVV_BINOP_NUM): Ditto.
(legitimize_move): Refactor the framework of RVV auto-vectorization.
(emit_vlmax_op): Ditto.
(emit_vlmax_reg_op): Ditto.
(emit_len_op): Ditto.
(emit_len_binop): Ditto.
(emit_vlmax_tany_many): Ditto.
(emit_nonvlmax_tany_many): Ditto.
(sew64_scalar_helper): Ditto.
(expand_tuple_move): Ditto.
* config/riscv/riscv-v.cc (emit_pred_op): Ditto.
(emit_pred_binop): Ditto.
(emit_vlmax_op): Ditto.
(emit_vlmax_tany_many): New function.
(emit_len_op): Remove.
(emit_nonvlmax_tany_many): New function.
(emit_vlmax_reg_op): Remove.
(emit_len_binop): Ditto.
(emit_index_op): Ditto.
(expand_vec_series): Refactor the framework of RVV auto-vectorization.
(expand_const_vector): Ditto.
(legitimize_move): Ditto.
(sew64_scalar_helper): Ditto.
(expand_tuple_move): Ditto.
(expand_vector_init_insert_elems): Ditto.
* config/riscv/riscv.cc (vector_zero_call_used_regs): Ditto.
* config/riscv/vector.md: Ditto.
2023-05-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR target/109855
* config/aarch64/aarch64-simd.md (add_vec_concat_subst_le): Add predicate
and constraint for operand 0.
(add_vec_concat_subst_be): Likewise.
2023-05-23 Richard Biener <rguenther@suse.de>
PR tree-optimization/109849
* tree-ssa-pre.cc (do_hoist_insertion): Compute ANTIC_OUT
and use that to determine what to hoist.
2023-05-23 Eric Botcazou <ebotcazou@adacore.com>
* fold-const.cc (native_encode_initializer) <CONSTRUCTOR>: Apply the
specific treatment for bit-fields only if they have an integral type
and filter out non-integral bit-fields that do not start and end on
a byte boundary.
2023-05-23 Aldy Hernandez <aldyh@redhat.com>
PR tree-optimization/109920
* value-range.h (RESIZABLE>::~int_range): Use delete[].
2023-05-22 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.cc (ix86_shift_rotate_cost): Correct
calcuation of integer vector mode costs to reflect generated
instruction sequences of different integer vector modes and
different target ABIs. Remove "speed" function argument.
(ix86_rtx_costs): Update call for removed function argument.
(ix86_vector_costs::add_stmt_cost): Ditto.
2023-05-22 Aldy Hernandez <aldyh@redhat.com>
* value-range.h (class Value_Range): Implement set_zero,
set_nonzero, and nonzero_p.
2023-05-22 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.cc (ix86_multiplication_cost): Add
the cost of a memory read to the cost of V?QImode sequences.
2023-05-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-v.cc: Add "m_" prefix.
2023-05-22 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* tree-vect-loop.cc (vect_get_loop_len): Fix issue for
multiple-rgroup of length.
* tree-vect-stmts.cc (vectorizable_store): Ditto.
(vectorizable_load): Ditto.
* tree-vectorizer.h (vect_get_loop_len): Ditto.
2023-05-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv.cc (riscv_const_insns): Reorganize the
codes.
2023-05-22 Kewen Lin <linkw@linux.ibm.com>
* tree-vect-slp.cc (vect_transform_slp_perm_load_1): Refactor the
handling for the case index == count.
2023-05-21 Georg-Johann Lay <avr@gjlay.de>
PR target/90622
* config/avr/avr.cc (avr_fold_builtin) [AVR_BUILTIN_INSERT_BITS]:
Don't fold to XOR / AND / XOR if just one bit is copied to the
same position.
2023-05-21 Roger Sayle <roger@nextmovesoftware.com>
* config/nvptx/nvptx.cc (nvptx_expand_brev): Expand target
builtin for bit reversal using brev instruction.
(enum nvptx_builtins): Add NVPTX_BUILTIN_BREV and
NVPTX_BUILTIN_BREVLL.
(nvptx_init_builtins): Define "brev" and "brevll".
(nvptx_expand_builtin): Expand NVPTX_BUILTIN_BREV and
NVPTX_BUILTIN_BREVLL via nvptx_expand_brev function.
* doc/extend.texi (Nvidia PTX Builtin-in Functions): New
section, document __builtin_nvptx_brev{,ll}.
2023-05-21 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/109505
* match.pd ((x | CST1) & CST2 -> (x & CST2) | (CST1 & CST2),
Combine successive equal operations with constants,
(A +- CST1) +- CST2 -> A + CST3, (CST1 - A) +- CST2 -> CST3 - A,
CST1 - (CST2 - A) -> CST3 + A): Use ! on ops with 2 CONSTANT_CLASS_P
operands.
2023-05-21 Andrew Pinski <apinski@marvell.com>
* expr.cc (expand_single_bit_test): Correct bitpos for big-endian.
2023-05-21 Pan Li <pan2.li@intel.com>
* config/riscv/genrvv-type-indexer.cc (BOOL_SIZE_LIST): Add the
rest bool size, aka 2, 4, 8, 16, 32, 64.
* config/riscv/riscv-vector-builtins-functions.def (vreinterpret):
Register vbool[2|4|8|16|32|64] interpret function.
* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_BOOL2_INTERPRET_OPS):
New macro for vbool2_t.
(DEF_RVV_BOOL4_INTERPRET_OPS): Likewise.
(DEF_RVV_BOOL8_INTERPRET_OPS): Likewise.
(DEF_RVV_BOOL16_INTERPRET_OPS): Likewise.
(DEF_RVV_BOOL32_INTERPRET_OPS): Likewise.
(DEF_RVV_BOOL64_INTERPRET_OPS): Likewise.
(vint8m1_t): Add the type to bool[2|4|8|16|32|64]_interpret_ops.
(vint16m1_t): Likewise.
(vint32m1_t): Likewise.
(vint64m1_t): Likewise.
(vuint8m1_t): Likewise.
(vuint16m1_t): Likewise.
(vuint32m1_t): Likewise.
(vuint64m1_t): Likewise.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_BOOL2_INTERPRET_OPS):
New macro for vbool2_t.
(DEF_RVV_BOOL4_INTERPRET_OPS): Likewise.
(DEF_RVV_BOOL8_INTERPRET_OPS): Likewise.
(DEF_RVV_BOOL16_INTERPRET_OPS): Likewise.
(DEF_RVV_BOOL32_INTERPRET_OPS): Likewise.
(DEF_RVV_BOOL64_INTERPRET_OPS): Likewise.
(required_extensions_p): Add vbool[2|4|8|16|32|64] interpret case.
* config/riscv/riscv-vector-builtins.def (bool2_interpret): Add
vbool2_t interprect to base type.
(bool4_interpret): Likewise.
(bool8_interpret): Likewise.
(bool16_interpret): Likewise.
(bool32_interpret): Likewise.
(bool64_interpret): Likewise.
2023-05-21 Andrew Pinski <apinski@marvell.com>
PR middle-end/109919
* expr.cc (expand_single_bit_test): Don't use the
target for expand_expr.
2023-05-20 Gerald Pfeifer <gerald@pfeifer.com>
* doc/install.texi (Specific): Remove de facto empty alpha*-*-*
section.
2023-05-20 Pan Li <pan2.li@intel.com>
* mode-switching.cc (entity_map): Initialize the array to zero.
(bb_info): Ditto.
2023-05-20 Triffid Hunter <triffid.hunter@gmail.com>
PR target/105753
* config/avr/avr.md (divmodpsi, udivmodpsi, divmodsi, udivmodsi):
Remove superfluous "parallel" in insn pattern.
([u]divmod<mode>4): Tidy code. Use gcc_unreachable() instead of
printing error text to assembly.
2023-05-20 Andrew Pinski <apinski@marvell.com>
* expr.cc (fold_single_bit_test): Rename to ...
(expand_single_bit_test): This and expand directly.
(do_store_flag): Update for the rename function.
2023-05-20 Andrew Pinski <apinski@marvell.com>
* expr.cc (fold_single_bit_test): Use BIT_FIELD_REF
instead of shift/and.
2023-05-20 Andrew Pinski <apinski@marvell.com>
* expr.cc (fold_single_bit_test): Add an assert
and simplify based on code being NE_EXPR or EQ_EXPR.
2023-05-20 Andrew Pinski <apinski@marvell.com>
* expr.cc (fold_single_bit_test): Take inner and bitnum
instead of arg0 and arg1. Update the code.
(do_store_flag): Don't create a tree when calling
fold_single_bit_test instead just call it with the bitnum
and the inner tree.
2023-05-20 Andrew Pinski <apinski@marvell.com>
* expr.cc (fold_single_bit_test): Use get_def_for_expr
instead of checking the inner's code.
2023-05-20 Andrew Pinski <apinski@marvell.com>
* expr.cc (fold_single_bit_test_into_sign_test): Inline into ...
(fold_single_bit_test): This and simplify.
2023-05-20 Andrew Pinski <apinski@marvell.com>
* fold-const.cc (fold_single_bit_test_into_sign_test): Move to
expr.cc.
(fold_single_bit_test): Likewise.
* expr.cc (fold_single_bit_test_into_sign_test): Move from fold-const.cc
(fold_single_bit_test): Likewise and make static.
* fold-const.h (fold_single_bit_test): Remove declaration.
2023-05-20 Die Li <lidie@eswincomputing.com>
* config/riscv/riscv.cc (riscv_expand_conditional_move): Fix mode
checking.
2023-05-20 Raphael Moreira Zinsly <rzinsly@ventanamicro.com>
* config/riscv/bitmanip.md (branch<X:mode>_bext): New split pattern.
2023-05-20 Raphael Moreira Zinsly <rzinsly@ventanamicro.com>
PR target/106888
* config/riscv/bitmanip.md
(<bitmanip_optab>disi2): Match with any_extend.
(<bitmanip_optab>disi2_sext): New pattern to match
with sign extend using an ANDI instruction.
2023-05-19 Nathan Sidwell <nathan@acm.org>
PR other/99451
* opts.h (handle_deferred_dump_options): Declare.
* opts-global.cc (handle_common_deferred_options): Do not handle
dump options here.
(handle_deferred_dump_options): New.
* toplev.cc (toplev::main): Call it after plugin init.
2023-05-19 Joern Rennecke <joern.rennecke@embecosm.com>
* config/riscv/constraints.md (DsS, DsD): Restore agreement
with shiftm1 mode attribute.
2023-05-19 Andrew Pinski <apinski@marvell.com>
PR driver/33980
* gcc.cc (default_compilers["@c-header"]): Add %w
after the --output-pch.
2023-05-19 Vineet Gupta <vineetg@rivosinc.com>
* config/riscv/riscv.cc (riscv_split_integer): if loval is equal
to hival, ASHIFT the corresponding regs.
2023-05-19 Robin Dapp <rdapp@ventanamicro.com>
* config/riscv/riscv.cc (riscv_const_insns): Remove else.
2023-05-19 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/105776
* tree-ssa-math-opts.cc (arith_overflow_check_p): If cast_stmt is
non-NULL, allow division statement to have a cast as single imm use
rather than comparison/condition.
(match_arith_overflow): In that case remove the cast stmt in addition
to the division statement.
2023-05-19 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/101856
* tree-ssa-math-opts.cc (match_arith_overflow): Pattern detect
unsigned __builtin_mul_overflow_p even when umulv4_optab doesn't
support it but umul_highpart_optab does.
2023-05-19 Eric Botcazou <ebotcazou@adacore.com>
* varasm.cc (output_constructor_bitfield): Call tree_to_uhwi instead
of tree_to_shwi on array indices. Minor tweaks.
2023-05-18 Bernhard Reutner-Fischer <aldot@gcc.gnu.org>
* alias.cc (ref_all_alias_ptr_type_p): Use _P() defines from tree.h.
* attribs.cc (diag_attr_exclusions): Ditto.
(decl_attributes): Ditto.
(build_type_attribute_qual_variant): Ditto.
* builtins.cc (fold_builtin_carg): Ditto.
(fold_builtin_next_arg): Ditto.
(do_mpc_arg2): Ditto.
* cfgexpand.cc (expand_return): Ditto.
* cgraph.h (decl_in_symtab_p): Ditto.
(symtab_node::get_create): Ditto.
* dwarf2out.cc (base_type_die): Ditto.
(implicit_ptr_descriptor): Ditto.
(gen_array_type_die): Ditto.
(gen_type_die_with_usage): Ditto.
(optimize_location_into_implicit_ptr): Ditto.
* expr.cc (do_store_flag): Ditto.
* fold-const.cc (negate_expr_p): Ditto.
(fold_negate_expr_1): Ditto.
(fold_convert_const): Ditto.
(fold_convert_loc): Ditto.
(constant_boolean_node): Ditto.
(fold_binary_op_with_conditional_arg): Ditto.
(build_fold_addr_expr_with_type_loc): Ditto.
(fold_comparison): Ditto.
(fold_checksum_tree): Ditto.
(tree_unary_nonnegative_warnv_p): Ditto.
(integer_valued_real_unary_p): Ditto.
(fold_read_from_constant_string): Ditto.
* gcc-rich-location.cc (maybe_range_label_for_tree_type_mismatch::get_text): Ditto.
* gimple-expr.cc (useless_type_conversion_p): Ditto.
(is_gimple_reg): Ditto.
(is_gimple_asm_val): Ditto.
(mark_addressable): Ditto.
* gimple-expr.h (is_gimple_variable): Ditto.
(virtual_operand_p): Ditto.
* gimple-ssa-warn-access.cc (pass_waccess::check_dangling_stores): Ditto.
* gimplify.cc (gimplify_bind_expr): Ditto.
(gimplify_return_expr): Ditto.
(gimple_add_padding_init_for_auto_var): Ditto.
(gimplify_addr_expr): Ditto.
(omp_add_variable): Ditto.
(omp_notice_variable): Ditto.
(omp_get_base_pointer): Ditto.
(omp_strip_components_and_deref): Ditto.
(omp_strip_indirections): Ditto.
(omp_accumulate_sibling_list): Ditto.
(omp_build_struct_sibling_lists): Ditto.
(gimplify_adjust_omp_clauses_1): Ditto.
(gimplify_adjust_omp_clauses): Ditto.
(gimplify_omp_for): Ditto.
(goa_lhs_expr_p): Ditto.
(gimplify_one_sizepos): Ditto.
* graphite-scop-detection.cc (scop_detection::graphite_can_represent_scev): Ditto.
* ipa-devirt.cc (odr_types_equivalent_p): Ditto.
* ipa-prop.cc (ipa_set_jf_constant): Ditto.
(propagate_controlled_uses): Ditto.
* ipa-sra.cc (type_prevails_p): Ditto.
(scan_expr_access): Ditto.
* optabs-tree.cc (optab_for_tree_code): Ditto.
* toplev.cc (wrapup_global_declaration_1): Ditto.
* trans-mem.cc (transaction_invariant_address_p): Ditto.
* tree-cfg.cc (verify_types_in_gimple_reference): Ditto.
(verify_gimple_comparison): Ditto.
(verify_gimple_assign_binary): Ditto.
(verify_gimple_assign_single): Ditto.
* tree-complex.cc (get_component_ssa_name): Ditto.
* tree-emutls.cc (lower_emutls_2): Ditto.
* tree-inline.cc (copy_tree_body_r): Ditto.
(estimate_move_cost): Ditto.
(copy_decl_for_dup_finish): Ditto.
* tree-nested.cc (convert_nonlocal_omp_clauses): Ditto.
(note_nonlocal_vla_type): Ditto.
(convert_local_omp_clauses): Ditto.
(remap_vla_decls): Ditto.
(fixup_vla_decls): Ditto.
* tree-parloops.cc (loop_has_vector_phi_nodes): Ditto.
* tree-pretty-print.cc (print_declaration): Ditto.
(print_call_name): Ditto.
* tree-sra.cc (compare_access_positions): Ditto.
* tree-ssa-alias.cc (compare_type_sizes): Ditto.
* tree-ssa-ccp.cc (get_default_value): Ditto.
* tree-ssa-coalesce.cc (populate_coalesce_list_for_outofssa): Ditto.
* tree-ssa-dom.cc (reduce_vector_comparison_to_scalar_comparison): Ditto.
* tree-ssa-forwprop.cc (can_propagate_from): Ditto.
* tree-ssa-propagate.cc (may_propagate_copy): Ditto.
* tree-ssa-sccvn.cc (fully_constant_vn_reference_p): Ditto.
* tree-ssa-sink.cc (statement_sink_location): Ditto.
* tree-ssa-structalias.cc (type_must_have_pointers): Ditto.
* tree-ssa-ter.cc (find_replaceable_in_bb): Ditto.
* tree-ssa-uninit.cc (warn_uninit): Ditto.
* tree-ssa.cc (maybe_rewrite_mem_ref_base): Ditto.
(non_rewritable_mem_ref_base): Ditto.
* tree-streamer-in.cc (lto_input_ts_type_non_common_tree_pointers): Ditto.
* tree-streamer-out.cc (write_ts_type_non_common_tree_pointers): Ditto.
* tree-vect-generic.cc (do_binop): Ditto.
(do_cond): Ditto.
* tree-vect-stmts.cc (vect_init_vector): Ditto.
* tree-vector-builder.h (tree_vector_builder::note_representative): Ditto.
* tree.cc (sign_mask_for): Ditto.
(verify_type_variant): Ditto.
(gimple_canonical_types_compatible_p): Ditto.
(verify_type): Ditto.
* ubsan.cc (get_ubsan_type_info_for_type): Ditto.
* var-tracking.cc (prepare_call_arguments): Ditto.
(vt_add_function_parameters): Ditto.
* varasm.cc (decode_addr_const): Ditto.
2023-05-18 Bernhard Reutner-Fischer <aldot@gcc.gnu.org>
* omp-low.cc (scan_sharing_clauses): Use _P() defines from tree.h.
(lower_reduction_clauses): Ditto.
(lower_send_clauses): Ditto.
(lower_omp_task_reductions): Ditto.
* omp-oacc-neuter-broadcast.cc (install_var_field): Ditto.
(worker_single_copy): Ditto.
* omp-offload.cc (oacc_rewrite_var_decl): Ditto.
* omp-simd-clone.cc (plausible_type_for_simd_clone): Ditto.
2023-05-18 Bernhard Reutner-Fischer <aldot@gcc.gnu.org>
* lto-streamer-in.cc (lto_input_var_decl_ref): Use _P defines from
tree.h.
(lto_read_body_or_constructor): Ditto.
* lto-streamer-out.cc (tree_is_indexable): Ditto.
(lto_output_var_decl_ref): Ditto.
(DFS::DFS_write_tree_body): Ditto.
(wrap_refs): Ditto.
(write_symbol_extension_info): Ditto.
2023-05-18 Bernhard Reutner-Fischer <aldot@gcc.gnu.org>
* config/aarch64/aarch64.cc (aarch64_short_vector_p): Use _P
defines from tree.h.
(aarch64_mangle_type): Ditto.
* config/alpha/alpha.cc (alpha_in_small_data_p): Ditto.
(alpha_gimplify_va_arg_1): Ditto.
* config/arc/arc.cc (arc_encode_section_info): Ditto.
(arc_is_aux_reg_p): Ditto.
(arc_is_uncached_mem_p): Ditto.
(arc_handle_aux_attribute): Ditto.
* config/arm/arm.cc (arm_handle_isr_attribute): Ditto.
(arm_handle_cmse_nonsecure_call): Ditto.
(arm_set_default_type_attributes): Ditto.
(arm_is_segment_info_known): Ditto.
(arm_mangle_type): Ditto.
* config/arm/unknown-elf.h (IN_NAMED_SECTION_P): Ditto.
* config/avr/avr.cc (avr_lookup_function_attribute1): Ditto.
(avr_decl_absdata_p): Ditto.
(avr_insert_attributes): Ditto.
(avr_section_type_flags): Ditto.
(avr_encode_section_info): Ditto.
* config/bfin/bfin.cc (bfin_handle_l2_attribute): Ditto.
* config/bpf/bpf.cc (bpf_core_compute): Ditto.
* config/c6x/c6x.cc (c6x_in_small_data_p): Ditto.
* config/csky/csky.cc (csky_handle_isr_attribute): Ditto.
(csky_mangle_type): Ditto.
* config/darwin-c.cc (darwin_pragma_unused): Ditto.
* config/darwin.cc (is_objc_metadata): Ditto.
* config/epiphany/epiphany.cc (epiphany_function_ok_for_sibcall): Ditto.
* config/epiphany/epiphany.h (ROUND_TYPE_ALIGN): Ditto.
* config/frv/frv.cc (frv_emit_movsi): Ditto.
* config/gcn/gcn-tree.cc (gcn_lockless_update): Ditto.
* config/gcn/gcn.cc (gcn_asm_output_symbol_ref): Ditto.
* config/h8300/h8300.cc (h8300_encode_section_info): Ditto.
* config/i386/i386-expand.cc: Ditto.
* config/i386/i386.cc (type_natural_mode): Ditto.
(ix86_function_arg): Ditto.
(ix86_data_alignment): Ditto.
(ix86_local_alignment): Ditto.
(ix86_simd_clone_compute_vecsize_and_simdlen): Ditto.
* config/i386/winnt-cxx.cc (i386_pe_type_dllimport_p): Ditto.
(i386_pe_type_dllexport_p): Ditto.
(i386_pe_adjust_class_at_definition): Ditto.
* config/i386/winnt.cc (i386_pe_determine_dllimport_p): Ditto.
(i386_pe_binds_local_p): Ditto.
(i386_pe_section_type_flags): Ditto.
* config/ia64/ia64.cc (ia64_encode_section_info): Ditto.
(ia64_gimplify_va_arg): Ditto.
(ia64_in_small_data_p): Ditto.
* config/iq2000/iq2000.cc (iq2000_function_arg): Ditto.
* config/lm32/lm32.cc (lm32_in_small_data_p): Ditto.
* config/loongarch/loongarch.cc (loongarch_handle_model_attribute): Ditto.
* config/m32c/m32c.cc (m32c_insert_attributes): Ditto.
* config/mcore/mcore.cc (mcore_mark_dllimport): Ditto.
(mcore_encode_section_info): Ditto.
* config/microblaze/microblaze.cc (microblaze_elf_in_small_data_p): Ditto.
* config/mips/mips.cc (mips_output_aligned_decl_common): Ditto.
* config/mmix/mmix.cc (mmix_encode_section_info): Ditto.
* config/nvptx/nvptx.cc (nvptx_encode_section_info): Ditto.
(pass_in_memory): Ditto.
(nvptx_generate_vector_shuffle): Ditto.
(nvptx_lockless_update): Ditto.
* config/pa/pa.cc (pa_function_arg_padding): Ditto.
(pa_function_value): Ditto.
(pa_function_arg): Ditto.
* config/pa/pa.h (IN_NAMED_SECTION_P): Ditto.
(TEXT_SPACE_P): Ditto.
* config/pa/som.h (MAKE_DECL_ONE_ONLY): Ditto.
* config/pdp11/pdp11.cc (pdp11_return_in_memory): Ditto.
* config/riscv/riscv.cc (riscv_in_small_data_p): Ditto.
(riscv_mangle_type): Ditto.
* config/rl78/rl78.cc (rl78_insert_attributes): Ditto.
(rl78_addsi3_internal): Ditto.
* config/rs6000/aix.h (ROUND_TYPE_ALIGN): Ditto.
* config/rs6000/darwin.h (ROUND_TYPE_ALIGN): Ditto.
* config/rs6000/freebsd64.h (ROUND_TYPE_ALIGN): Ditto.
* config/rs6000/linux64.h (ROUND_TYPE_ALIGN): Ditto.
* config/rs6000/rs6000-call.cc (rs6000_function_arg_boundary): Ditto.
(rs6000_function_arg_advance_1): Ditto.
(rs6000_function_arg): Ditto.
(rs6000_pass_by_reference): Ditto.
* config/rs6000/rs6000-logue.cc (rs6000_function_ok_for_sibcall): Ditto.
* config/rs6000/rs6000.cc (rs6000_data_alignment): Ditto.
(rs6000_set_default_type_attributes): Ditto.
(rs6000_elf_in_small_data_p): Ditto.
(IN_NAMED_SECTION): Ditto.
(rs6000_xcoff_encode_section_info): Ditto.
(rs6000_function_value): Ditto.
(invalid_arg_for_unprototyped_fn): Ditto.
* config/s390/s390-c.cc (s390_fn_types_compatible): Ditto.
(s390_vec_n_elem): Ditto.
* config/s390/s390.cc (s390_check_type_for_vector_abi): Ditto.
(s390_function_arg_integer): Ditto.
(s390_return_in_memory): Ditto.
(s390_encode_section_info): Ditto.
* config/sh/sh.cc (sh_gimplify_va_arg_expr): Ditto.
(sh_function_value): Ditto.
* config/sol2.cc (solaris_insert_attributes): Ditto.
* config/sparc/sparc.cc (function_arg_slotno): Ditto.
* config/sparc/sparc.h (ROUND_TYPE_ALIGN): Ditto.
* config/stormy16/stormy16.cc (xstormy16_encode_section_info): Ditto.
(xstormy16_handle_below100_attribute): Ditto.
* config/v850/v850.cc (v850_encode_section_info): Ditto.
(v850_insert_attributes): Ditto.
* config/visium/visium.cc (visium_pass_by_reference): Ditto.
(visium_return_in_memory): Ditto.
* config/xtensa/xtensa.cc (xtensa_multibss_section_type_flags): Ditto.
2023-05-18 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386-expand.cc (ix86_expand_vecop_qihi_partial): New.
(ix86_expand_vecop_qihi): Add op2vec bool variable.
Do not set REG_EQUAL note.
* config/i386/i386-protos.h (ix86_expand_vecop_qihi_partial):
Add prototype.
* config/i386/i386.cc (ix86_multiplication_cost): Handle
V4QImode and V8QImode.
* config/i386/mmx.md (mulv8qi3): New expander.
(mulv4qi3): Ditto.
* config/i386/sse.md (mulv8qi3): Remove.
2023-05-18 Georg-Johann Lay <avr@gjlay.de>
* config/avr/gen-avr-mmcu-specs.cc: Remove stale */ after // comment.
2023-05-18 Jonathan Wakely <jwakely@redhat.com>
PR bootstrap/105831
* config.gcc: Use = operator instead of ==.
2023-05-18 Michael Bäuerle <micha@NetBSD.org>
PR bootstrap/105831
* config/nvptx/gen-opt.sh: Use = operator instead of ==.
* configure.ac: Likewise.
* configure: Regenerate.
2023-05-18 Stam Markianos-Wright <stam.markianos-wright@arm.com>
* config/arm/arm_mve.h: (__ARM_mve_typeid): Add more pointer types.
(__ARM_mve_coerce1): Remove.
(__ARM_mve_coerce2): Remove.
(__ARM_mve_coerce3): Remove.
(__ARM_mve_coerce_i_scalar): New.
(__ARM_mve_coerce_s8_ptr): New.
(__ARM_mve_coerce_u8_ptr): New.
(__ARM_mve_coerce_s16_ptr): New.
(__ARM_mve_coerce_u16_ptr): New.
(__ARM_mve_coerce_s32_ptr): New.
(__ARM_mve_coerce_u32_ptr): New.
(__ARM_mve_coerce_s64_ptr): New.
(__ARM_mve_coerce_u64_ptr): New.
(__ARM_mve_coerce_f_scalar): New.
(__ARM_mve_coerce_f16_ptr): New.
(__ARM_mve_coerce_f32_ptr): New.
(__arm_vst4q): Change _coerce_ overloads.
(__arm_vbicq): Change _coerce_ overloads.
(__arm_vld1q): Change _coerce_ overloads.
(__arm_vld1q_z): Change _coerce_ overloads.
(__arm_vld2q): Change _coerce_ overloads.
(__arm_vld4q): Change _coerce_ overloads.
(__arm_vldrhq_gather_offset): Change _coerce_ overloads.
(__arm_vldrhq_gather_offset_z): Change _coerce_ overloads.
(__arm_vldrhq_gather_shifted_offset): Change _coerce_ overloads.
(__arm_vldrhq_gather_shifted_offset_z): Change _coerce_ overloads.
(__arm_vldrwq_gather_offset): Change _coerce_ overloads.
(__arm_vldrwq_gather_offset_z): Change _coerce_ overloads.
(__arm_vldrwq_gather_shifted_offset): Change _coerce_ overloads.
(__arm_vldrwq_gather_shifted_offset_z): Change _coerce_ overloads.
(__arm_vst1q_p): Change _coerce_ overloads.
(__arm_vst2q): Change _coerce_ overloads.
(__arm_vst1q): Change _coerce_ overloads.
(__arm_vstrhq): Change _coerce_ overloads.
(__arm_vstrhq_p): Change _coerce_ overloads.
(__arm_vstrhq_scatter_offset_p): Change _coerce_ overloads.
(__arm_vstrhq_scatter_offset): Change _coerce_ overloads.
(__arm_vstrhq_scatter_shifted_offset_p): Change _coerce_ overloads.
(__arm_vstrhq_scatter_shifted_offset): Change _coerce_ overloads.
(__arm_vstrwq_p): Change _coerce_ overloads.
(__arm_vstrwq): Change _coerce_ overloads.
(__arm_vstrwq_scatter_offset): Change _coerce_ overloads.
(__arm_vstrwq_scatter_offset_p): Change _coerce_ overloads.
(__arm_vstrwq_scatter_shifted_offset): Change _coerce_ overloads.
(__arm_vstrwq_scatter_shifted_offset_p): Change _coerce_ overloads.
(__arm_vsetq_lane): Change _coerce_ overloads.
(__arm_vldrbq_gather_offset): Change _coerce_ overloads.
(__arm_vdwdupq_x_u8): Change _coerce_ overloads.
(__arm_vdwdupq_x_u16): Change _coerce_ overloads.
(__arm_vdwdupq_x_u32): Change _coerce_ overloads.
(__arm_viwdupq_x_u8): Change _coerce_ overloads.
(__arm_viwdupq_x_u16): Change _coerce_ overloads.
(__arm_viwdupq_x_u32): Change _coerce_ overloads.
(__arm_vidupq_x_u8): Change _coerce_ overloads.
(__arm_vddupq_x_u8): Change _coerce_ overloads.
(__arm_vidupq_x_u16): Change _coerce_ overloads.
(__arm_vddupq_x_u16): Change _coerce_ overloads.
(__arm_vidupq_x_u32): Change _coerce_ overloads.
(__arm_vddupq_x_u32): Change _coerce_ overloads.
(__arm_vldrdq_gather_offset): Change _coerce_ overloads.
(__arm_vldrdq_gather_offset_z): Change _coerce_ overloads.
(__arm_vldrdq_gather_shifted_offset): Change _coerce_ overloads.
(__arm_vldrdq_gather_shifted_offset_z): Change _coerce_ overloads.
(__arm_vldrbq_gather_offset_z): Change _coerce_ overloads.
(__arm_vidupq_u16): Change _coerce_ overloads.
(__arm_vidupq_u32): Change _coerce_ overloads.
(__arm_vidupq_u8): Change _coerce_ overloads.
(__arm_vddupq_u16): Change _coerce_ overloads.
(__arm_vddupq_u32): Change _coerce_ overloads.
(__arm_vddupq_u8): Change _coerce_ overloads.
(__arm_viwdupq_m): Change _coerce_ overloads.
(__arm_viwdupq_u16): Change _coerce_ overloads.
(__arm_viwdupq_u32): Change _coerce_ overloads.
(__arm_viwdupq_u8): Change _coerce_ overloads.
(__arm_vdwdupq_m): Change _coerce_ overloads.
(__arm_vdwdupq_u16): Change _coerce_ overloads.
(__arm_vdwdupq_u32): Change _coerce_ overloads.
(__arm_vdwdupq_u8): Change _coerce_ overloads.
(__arm_vstrbq): Change _coerce_ overloads.
(__arm_vstrbq_p): Change _coerce_ overloads.
(__arm_vstrbq_scatter_offset_p): Change _coerce_ overloads.
(__arm_vstrdq_scatter_offset_p): Change _coerce_ overloads.
(__arm_vstrdq_scatter_offset): Change _coerce_ overloads.
(__arm_vstrdq_scatter_shifted_offset_p): Change _coerce_ overloads.
(__arm_vstrdq_scatter_shifted_offset): Change _coerce_ overloads.
2023-05-18 Stam Markianos-Wright <stam.markianos-wright@arm.com>
* config/arm/arm_mve.h (__arm_vbicq): Change coerce on
scalar constant.
2023-05-18 Stam Markianos-Wright <stam.markianos-wright@arm.com>
* config/arm/arm_mve.h (__arm_vadcq_s32): Fix arithmetic.
(__arm_vadcq_u32): Likewise.
(__arm_vadcq_m_s32): Likewise.
(__arm_vadcq_m_u32): Likewise.
(__arm_vsbcq_s32): Likewise.
(__arm_vsbcq_u32): Likewise.
(__arm_vsbcq_m_s32): Likewise.
(__arm_vsbcq_m_u32): Likewise.
* config/arm/mve.md (get_fpscr_nzcvqc): Make unspec_volatile.
2023-05-18 Andrea Corallo <andrea.corallo@arm.com>
* config/arm/mve.md (mve_vrndq_m_f<mode>, mve_vrev64q_f<mode>)
(mve_vrev32q_fv8hf, mve_vcvttq_f32_f16v4sf)
(mve_vcvtbq_f32_f16v4sf, mve_vcvtq_to_f_<supf><mode>)
(mve_vrev64q_<supf><mode>, mve_vcvtq_from_f_<supf><mode>)
(mve_vmovltq_<supf><mode>, mve_vmovlbq_<supf><mode>)
(mve_vcvtpq_<supf><mode>, mve_vcvtnq_<supf><mode>)
(mve_vcvtmq_<supf><mode>, mve_vcvtaq_<supf><mode>)
(mve_vmvnq_n_<supf><mode>, mve_vrev16q_<supf>v16qi)
(mve_vctp<MVE_vctp>q<MVE_vpred>, mve_vbrsrq_n_f<mode>)
(mve_vbrsrq_n_<supf><mode>, mve_vandq_f<mode>, mve_vbicq_f<mode>)
(mve_vctp<MVE_vctp>q_m<MVE_vpred>, mve_vcvtbq_f16_f32v8hf)
(mve_vcvttq_f16_f32v8hf, mve_veorq_f<mode>)
(mve_vmlaldavxq_s<mode>, mve_vmlsldavq_s<mode>)
(mve_vmlsldavxq_s<mode>, mve_vornq_f<mode>, mve_vorrq_f<mode>)
(mve_vrmlaldavhxq_sv4si, mve_vcvtq_m_to_f_<supf><mode>)
(mve_vshlcq_<supf><mode>, mve_vmvnq_m_<supf><mode>)
(mve_vpselq_<supf><mode>, mve_vcvtbq_m_f16_f32v8hf)
(mve_vcvtbq_m_f32_f16v4sf, mve_vcvttq_m_f16_f32v8hf)
(mve_vcvttq_m_f32_f16v4sf, mve_vmlaldavq_p_<supf><mode>)
(mve_vmlsldavaq_s<mode>, mve_vmlsldavaxq_s<mode>)
(mve_vmlsldavq_p_s<mode>, mve_vmlsldavxq_p_s<mode>)
(mve_vmvnq_m_n_<supf><mode>, mve_vorrq_m_n_<supf><mode>)
(mve_vpselq_f<mode>, mve_vrev32q_m_fv8hf)
(mve_vrev32q_m_<supf><mode>, mve_vrev64q_m_f<mode>)
(mve_vrmlaldavhaxq_sv4si, mve_vrmlaldavhxq_p_sv4si)
(mve_vrmlsldavhaxq_sv4si, mve_vrmlsldavhq_p_sv4si)
(mve_vrmlsldavhxq_p_sv4si, mve_vrev16q_m_<supf>v16qi)
(mve_vrmlaldavhq_p_<supf>v4si, mve_vrmlsldavhaq_sv4si)
(mve_vandq_m_<supf><mode>, mve_vbicq_m_<supf><mode>)
(mve_veorq_m_<supf><mode>, mve_vornq_m_<supf><mode>)
(mve_vorrq_m_<supf><mode>, mve_vandq_m_f<mode>)
(mve_vbicq_m_f<mode>, mve_veorq_m_f<mode>, mve_vornq_m_f<mode>)
(mve_vorrq_m_f<mode>)
(mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn)
(mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn)
(mve_vstrdq_scatter_base_wb_p_<supf>v2di) : Fix spacing and
capitalization in the emitted asm.
2023-05-18 Andrea Corallo <andrea.corallo@arm.com>
* config/arm/constraints.md (mve_vldrd_immediate): Move it to
predicates.md.
(Ri): Move constraint definition from predicates.md.
(Rl): Define new constraint.
* config/arm/mve.md (mve_vstrwq_scatter_base_wb_p_<supf>v4si): Add
missing constraint.
(mve_vstrwq_scatter_base_wb_p_fv4sf): Add missing Up constraint
for op 1, use mve_vstrw_immediate predicate and Rl constraint for
op 2. Fix asm output spacing.
(mve_vstrdq_scatter_base_wb_p_<supf>v2di): Add missing constraint.
* config/arm/predicates.md (Ri) Move constraint to constraints.md
(mve_vldrd_immediate): Move it from
constraints.md.
(mve_vstrw_immediate): New predicate.
2023-05-18 Pan Li <pan2.li@intel.com>
Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Kito Cheng <kito.cheng@sifive.com>
Richard Biener <rguenther@suse.de>
Richard Sandiford <richard.sandiford@arm.com>
* combine.cc (struct reg_stat_type): Extend machine_mode to 16 bits.
* cse.cc (struct qty_table_elem): Extend machine_mode to 16 bits
(struct table_elt): Extend machine_mode to 16 bits.
(struct set): Ditto.
* genmodes.cc (emit_mode_wider): Extend type from char to short.
(emit_mode_complex): Ditto.
(emit_mode_inner): Ditto.
(emit_class_narrowest_mode): Ditto.
* genopinit.cc (main): Extend the machine_mode limit.
* ira-int.h (struct ira_allocno): Extend machine_mode to 16 bits and
re-ordered the struct fields for padding.
* machmode.h (MACHINE_MODE_BITSIZE): New macro.
(GET_MODE_2XWIDER_MODE): Extend type from char to short.
(get_mode_alignment): Extend type from char to short.
* ree.cc (struct ext_modified): Extend machine_mode to 16 bits and
removed the ATTRIBUTE_PACKED.
* rtl-ssa/accesses.h: Extend machine_mode to 16 bits, narrow
* rtl-ssa/internals.inl (rtl_ssa::access_info): Adjust the assignment.
m_kind to 2 bits and remove m_spare.
* rtl.h (RTX_CODE_BITSIZE): New macro.
(struct rtx_def): Swap both the bit size and location between the
rtx_code and the machine_mode.
(subreg_shape::unique_id): Extend the machine_mode limit.
* rtlanal.h: Extend machine_mode to 16 bits.
* tree-core.h (struct tree_type_common): Extend machine_mode to 16
bits and re-ordered the struct fields for padding.
(struct tree_decl_common): Extend machine_mode to 16 bits.
2023-05-17 Jin Ma <jinma@linux.alibaba.com>
* genrecog.cc (print_nonbool_test): Fix type error of
switch (SUBREG_BYTE (op))'.
2023-05-17 Jin Ma <jinma@linux.alibaba.com>
* common/config/riscv/riscv-common.cc: Remove
trailing spaces on lines.
* config/riscv/riscv.cc (riscv_legitimize_move): Likewise.
* config/riscv/riscv.h (enum reg_class): Likewise.
* config/riscv/riscv.md: Likewise.
2023-05-17 John David Anglin <danglin@gcc.gnu.org>
* config/pa/pa.md (clear_cache): New.
2023-05-17 Arsen Arsenović <arsen@aarsen.me>
* doc/extend.texi (C++ Concepts) <forall>: Remove extraneous
parenthesis. Fix misnamed index entry.
<concept>: Fix misnamed index entry.
2023-05-17 Jivan Hakobyan <jivanhakobyan9@gmail.com>
* config/riscv/riscv.md (*<optab><GPR:mode>3_mask): New pattern,
combined from ...
(*<optab>si3_mask, *<optab>di3_mask): Here.
(*<optab>si3_mask_1, *<optab>di3_mask_1): And here.
* config/riscv/bitmanip.md (*<bitmanip_optab><GPR:mode>3_mask): New
pattern.
(*<bitmanip_optab>si3_sext_mask): Likewise.
* config/riscv/iterators.md (shiftm1): Use const_si_mask_operand
and const_di_mask_operand.
(bitmanip_rotate): New iterator.
(bitmanip_optab): Add rotates.
* config/riscv/predicates.md (const_si_mask_operand): Renamed
from const31_operand. Generalize to handle more mask constants.
(const_di_mask_operand): Similarly.
2023-05-17 Jakub Jelinek <jakub@redhat.com>
PR c++/109884
* config/i386/i386-builtin-types.def (FLOAT128): Use
float128t_type_node rather than float128_type_node.
2023-05-17 Alexander Monakov <amonakov@ispras.ru>
* tree-ssa-math-opts.cc (convert_mult_to_fma): Enable only for
FP_CONTRACT_FAST (no functional change).
2023-05-17 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.cc (ix86_multiplication_cost): Correct
calcuation of integer vector mode costs to reflect generated
instruction sequences of different integer vector modes and
different target ABIs.
2023-05-17 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-opts.h (enum riscv_entity): New enum.
* config/riscv/riscv.cc (riscv_emit_mode_set): New function.
(riscv_mode_needed): Ditto.
(riscv_mode_after): Ditto.
(riscv_mode_entry): Ditto.
(riscv_mode_exit): Ditto.
(riscv_mode_priority): Ditto.
(TARGET_MODE_EMIT): New target hook.
(TARGET_MODE_NEEDED): Ditto.
(TARGET_MODE_AFTER): Ditto.
(TARGET_MODE_ENTRY): Ditto.
(TARGET_MODE_EXIT): Ditto.
(TARGET_MODE_PRIORITY): Ditto.
* config/riscv/riscv.h (OPTIMIZE_MODE_SWITCHING): Ditto.
(NUM_MODES_FOR_MODE_SWITCHING): Ditto.
* config/riscv/riscv.md: Add csrwvxrm.
* config/riscv/vector.md (rnu,rne,rdn,rod,none): New attribute.
(vxrmsi): New pattern.
2023-05-17 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vector-builtins-bases.cc: Introduce rounding mode.
* config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): Ditto.
(struct narrow_alu_def): Ditto.
* config/riscv/riscv-vector-builtins.cc (function_builder::apply_predication): Ditto.
(function_expander::use_exact_insn): Ditto.
* config/riscv/riscv-vector-builtins.h (function_checker::arg_num): New function.
(function_base::has_rounding_mode_operand_p): New function.
2023-05-17 Andrew Pinski <apinski@marvell.com>
* tree-ssa-forwprop.cc (simplify_builtin_call): Check
against 0 instead of calling integer_zerop.
2023-05-17 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vector-builtins.cc (register_vxrm): New function.
(DEF_RVV_VXRM_ENUM): New macro.
(handle_pragma_vector): Add vxrm enum register.
* config/riscv/riscv-vector-builtins.def (DEF_RVV_VXRM_ENUM): New macro.
(RNU): Ditto.
(RNE): Ditto.
(RDN): Ditto.
(ROD): Ditto.
2023-05-17 Aldy Hernandez <aldyh@redhat.com>
* value-range.h (Value_Range::operator=): New.
2023-05-17 Aldy Hernandez <aldyh@redhat.com>
* value-range.cc (vrange::operator=): Add a stub to copy
unsupported ranges.
* value-range.h (is_a <unsupported_range>): New.
(Value_Range::operator=): Support copying unsupported ranges.
2023-05-17 Aldy Hernandez <aldyh@redhat.com>
* data-streamer-in.cc (streamer_read_real_value): New.
(streamer_read_value_range): New.
* data-streamer-out.cc (streamer_write_real_value): New.
(streamer_write_vrange): New.
* data-streamer.h (streamer_write_vrange): New.
(streamer_read_value_range): New.
2023-05-17 Jonathan Wakely <jwakely@redhat.com>
PR c++/109532
* doc/invoke.texi (Code Gen Options): Note that -fshort-enums
is ignored for a fixed underlying type.
(C++ Dialect Options): Likewise for -fstrict-enums.
2023-05-17 Tobias Burnus <tobias@codesourcery.com>
* gimplify.cc (gimplify_scan_omp_clauses): Remove Fortran
special case.
2023-05-17 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
* config/s390/s390.cc (TARGET_ATOMIC_ALIGN_FOR_MODE):
New.
(s390_atomic_align_for_mode): New.
2023-05-17 Jakub Jelinek <jakub@redhat.com>
* wide-int.cc (wi::from_array): Add missing closing paren in function
comment.
2023-05-17 Kewen Lin <linkw@linux.ibm.com>
* tree-vect-loop.cc (vect_analyze_loop_1): Don't retry analysis with
suggested unroll factor once the previous analysis fails.
2023-05-17 Pan Li <pan2.li@intel.com>
* config/riscv/genrvv-type-indexer.cc (BOOL_SIZE_LIST): New
macro.
(main): Add bool1 to the type indexer.
* config/riscv/riscv-vector-builtins-functions.def
(vreinterpret): Register vbool1 interpret function.
* config/riscv/riscv-vector-builtins-types.def
(DEF_RVV_BOOL1_INTERPRET_OPS): New macro.
(vint8m1_t): Add the type to bool1_interpret_ops.
(vint16m1_t): Ditto.
(vint32m1_t): Ditto.
(vint64m1_t): Ditto.
(vuint8m1_t): Ditto.
(vuint16m1_t): Ditto.
(vuint32m1_t): Ditto.
(vuint64m1_t): Ditto.
* config/riscv/riscv-vector-builtins.cc
(DEF_RVV_BOOL1_INTERPRET_OPS): New macro.
(required_extensions_p): Add bool1 interpret case.
* config/riscv/riscv-vector-builtins.def
(bool1_interpret): Add bool1 interpret to base type.
* config/riscv/vector.md (@vreinterpret<mode>): Add new expand
with VB dest for vreinterpret.
2023-05-17 Jiufu Guo <guojiufu@linux.ibm.com>
PR target/106708
* config/rs6000/rs6000.cc (rs6000_emit_set_long_const): Support building
constants through "lis; xoris".
2023-05-16 Ajit Kumar Agarwal <aagarwa1@linux.ibm.com>
* common/config/rs6000/rs6000-common.cc: Add REE pass as a
default rs6000 target pass for O2 and above.
* doc/invoke.texi: Document -free
2023-05-16 Kito Cheng <kito.cheng@sifive.com>
* common/config/riscv/riscv-common.cc (riscv_compute_multilib):
Fix wrong select_kind...
2023-05-16 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
* config/s390/s390-protos.h (s390_expand_setmem): Change
function signature.
* config/s390/s390.cc (s390_expand_setmem): For memset's less
than or equal to 256 byte do not perform a libc call.
* config/s390/s390.md: Change expander into a version which
takes 8 operands.
2023-05-16 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
* config/s390/s390-protos.h (s390_expand_movmem): New.
* config/s390/s390.cc (s390_expand_movmem): New.
* config/s390/s390.md (movmem<mode>): New.
(*mvcrl): New.
(mvcrl): New.
2023-05-16 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
* config/s390/s390-protos.h (s390_expand_cpymem): Change
function signature.
* config/s390/s390.cc (s390_expand_cpymem): For memcpy's less
than or equal to 256 byte do not perform a libc call.
(s390_expand_insv): Adapt new function signature of
s390_expand_cpymem.
* config/s390/s390.md: Change expander into a version which
takes 8 operands.
2023-05-16 Andrew Pinski <apinski@marvell.com>
PR tree-optimization/109424
* match.pd: Add patterns for min/max of zero_one_valued
values to `&`/`|`.
2023-05-16 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-protos.h (enum frm_field_enum): New enum.
* config/riscv/riscv-vector-builtins.cc
(function_expander::use_ternop_insn): Add default rounding mode.
(function_expander::use_widen_ternop_insn): Ditto.
* config/riscv/riscv.cc (riscv_hard_regno_nregs): Add FRM REGNUM.
(riscv_hard_regno_mode_ok): Ditto.
(riscv_conditional_register_usage): Ditto.
* config/riscv/riscv.h (DWARF_FRAME_REGNUM): Ditto.
(FRM_REG_P): Ditto.
(RISCV_DWARF_FRM): Ditto.
* config/riscv/riscv.md: Ditto.
* config/riscv/vector-iterators.md: split no frm and has frm operations.
* config/riscv/vector.md (@pred_<optab><mode>_scalar): New pattern.
(@pred_<optab><mode>): Ditto.
2023-05-15 Aldy Hernandez <aldyh@redhat.com>
PR tree-optimization/109695
* value-range.cc (irange::operator=): Resize range.
(irange::union_): Same.
(irange::intersect): Same.
(irange::invert): Same.
(int_range_max): Default to 3 sub-ranges and resize as needed.
* value-range.h (irange::maybe_resize): New.
(~int_range): New.
(int_range::int_range): Adjust for resizing.
(int_range::operator=): Same.
2023-05-15 Aldy Hernandez <aldyh@redhat.com>
* ipa-cp.cc (ipcp_vr_lattice::meet_with_1): Avoid unnecessary
range copying
* value-range.cc (irange::union_nonzero_bits): Return TRUE only
when range changed.
2023-05-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-protos.h (enum vxrm_field_enum): New enum.
* config/riscv/riscv-vector-builtins.cc
(function_expander::use_exact_insn): Add default rounding mode operand.
* config/riscv/riscv.cc (riscv_hard_regno_nregs): Add VXRM_REGNUM.
(riscv_hard_regno_mode_ok): Ditto.
(riscv_conditional_register_usage): Ditto.
* config/riscv/riscv.h (DWARF_FRAME_REGNUM): Ditto.
(VXRM_REG_P): Ditto.
(RISCV_DWARF_VXRM): Ditto.
* config/riscv/riscv.md: Ditto.
* config/riscv/vector.md: Ditto
2023-05-15 Pan Li <pan2.li@intel.com>
* optabs.cc (maybe_gen_insn): Add case to generate instruction
that has 11 operands.
2023-05-15 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64.cc (aarch64_rtx_costs, NEG case): Add costing
logic for vector modes.
2023-05-15 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR target/99195
* config/aarch64/aarch64-simd.md (aarch64_cm<optab><mode>): Rename to...
(aarch64_cm<optab><mode><vczle><vczbe>): ... This.
(aarch64_cmtst<mode>): Rename to...
(aarch64_cmtst<mode><vczle><vczbe>): ... This.
(*aarch64_cmtst_same_<mode>): Rename to...
(*aarch64_cmtst_same_<mode><vczle><vczbe>): ... This.
(*aarch64_cmtstdi): Rename to...
(*aarch64_cmtstdi<vczle><vczbe>): ... This.
(aarch64_fac<optab><mode>): Rename to...
(aarch64_fac<optab><mode><vczle><vczbe>): ... This.
2023-05-15 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR target/99195
* config/aarch64/aarch64-simd.md (aarch64_s<optab><mode>): Rename to...
(aarch64_s<optab><mode><vczle><vczbe>): ... This.
2023-05-15 Pan Li <pan2.li@intel.com>
Juzhe-Zhong <juzhe.zhong@rivai.ai>
kito-cheng <kito.cheng@sifive.com>
* config/riscv/riscv-v.cc (const_vlmax_p): New function for
deciding the mode is constant or not.
(set_len_and_policy): Optimize VLS-VLMAX code gen to vsetivli.
2023-05-15 Richard Biener <rguenther@suse.de>
PR tree-optimization/109848
* tree-ssa-forwprop.cc (pass_forwprop::execute): Put the
TARGET_MEM_REF address preparation before the store, not
before the CTOR.
2023-05-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv.cc
(riscv_vectorize_preferred_vector_alignment): New function.
(TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT): New target hook.
2023-05-14 Andrew Pinski <apinski@marvell.com>
PR tree-optimization/109829
* match.pd: Add pattern for `signbit(x) !=/== 0 ? x : -x`.
2023-05-14 Uros Bizjak <ubizjak@gmail.com>
PR target/109807
* config/i386/i386.cc: Revert the 2023-05-11 change.
(ix86_widen_mult_cost): Return high value instead of
ICEing for unsupported modes.
2023-05-14 Ard Biesheuvel <ardb@kernel.org>
* config/i386/i386.cc (x86_function_profiler): Take
ix86_direct_extern_access into account when generating calls
to __fentry__()
2023-05-14 Pan Li <pan2.li@intel.com>
* config/riscv/riscv-vector-builtins.cc (required_extensions_p):
Refactor the or pattern to switch cases.
2023-05-13 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
* config/aarch64/aarch64.cc (aarch64_expand_vector_init_fallback): Rename
aarch64_expand_vector_init to this, and remove interleaving case.
Recursively call aarch64_expand_vector_init_fallback, instead of
aarch64_expand_vector_init.
(aarch64_unzip_vector_init): New function.
(aarch64_expand_vector_init): Likewise.
2023-05-13 Kito Cheng <kito.cheng@sifive.com>
* config/riscv/riscv-vsetvl.cc (pass_vsetvl::cleanup_insns):
Pull out function call from the gcc_assert.
2023-05-13 Kito Cheng <kito.cheng@sifive.com>
* config/riscv/riscv-vsetvl.cc (vlmul_to_str): New.
(policy_to_str): New.
(vector_insn_info::dump): Use vlmul_to_str and policy_to_str.
2023-05-13 Andrew Pinski <apinski@marvell.com>
PR tree-optimization/109834
* match.pd (popcount(bswap(x))->popcount(x)): Fix up unsigned type checking.
(popcount(rotate(x,y))->popcount(x)): Likewise.
2023-05-12 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386-expand.cc (ix86_expand_vecop_qihi2): Also
reject ymm instructions for TARGET_PREFER_AVX128. Use generic
gen_extend_insn to generate zero/sign extension instructions.
Fix comments.
(ix86_expand_vecop_qihi): Initialize interleave functions
for MULT code only. Fix comments.
2023-05-12 Uros Bizjak <ubizjak@gmail.com>
PR target/109797
* config/i386/mmx.md (mulv2si3): Remove expander.
(mulv2si3): Rename insn pattern from *mulv2si.
2023-05-12 Tobias Burnus <tobias@codesourcery.com>
PR libstdc++/109816
* lto-cgraph.cc (output_symtab): Guard lto_output_toplevel_asms by
'!lto_stream_offload_p'.
2023-05-12 Kito Cheng <kito.cheng@sifive.com>
Juzhe-Zhong <juzhe.zhong@rivai.ai>
PR target/109743
* config/riscv/riscv-vsetvl.cc (pass_vsetvl::get_vsetvl_at_end): New.
(local_avl_compatible_p): New.
(pass_vsetvl::local_eliminate_vsetvl_insn): Enhance local optimizations
for LCM, rewrite as a backward algorithm.
(pass_vsetvl::cleanup_insns): Use new local_eliminate_vsetvl_insn
interface, handle a BB at once.
2023-05-12 Richard Biener <rguenther@suse.de>
PR tree-optimization/64731
* tree-ssa-forwprop.cc (pass_forwprop::execute): Also
handle TARGET_MEM_REF destinations of stores from vector
CTORs.
2023-05-12 Richard Biener <rguenther@suse.de>
PR tree-optimization/109791
* match.pd (minus (convert ADDR_EXPR@0) (convert (pointer_plus @1 @2))):
New pattern.
(minus (convert (pointer_plus @1 @2)) (convert ADDR_EXPR@0)):
Likewise.
2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (vsriq): New.
* config/arm/arm-mve-builtins-base.def (vsriq): New.
* config/arm/arm-mve-builtins-base.h (vsriq): New.
* config/arm/arm-mve-builtins.cc
(function_instance::has_inactive_argument): Handle vsriq.
* config/arm/arm_mve.h (vsriq): Remove.
(vsriq_m): Remove.
(vsriq_n_u8): Remove.
(vsriq_n_s8): Remove.
(vsriq_n_u16): Remove.
(vsriq_n_s16): Remove.
(vsriq_n_u32): Remove.
(vsriq_n_s32): Remove.
(vsriq_m_n_s8): Remove.
(vsriq_m_n_u8): Remove.
(vsriq_m_n_s16): Remove.
(vsriq_m_n_u16): Remove.
(vsriq_m_n_s32): Remove.
(vsriq_m_n_u32): Remove.
(__arm_vsriq_n_u8): Remove.
(__arm_vsriq_n_s8): Remove.
(__arm_vsriq_n_u16): Remove.
(__arm_vsriq_n_s16): Remove.
(__arm_vsriq_n_u32): Remove.
(__arm_vsriq_n_s32): Remove.
(__arm_vsriq_m_n_s8): Remove.
(__arm_vsriq_m_n_u8): Remove.
(__arm_vsriq_m_n_s16): Remove.
(__arm_vsriq_m_n_u16): Remove.
(__arm_vsriq_m_n_s32): Remove.
(__arm_vsriq_m_n_u32): Remove.
(__arm_vsriq): Remove.
(__arm_vsriq_m): Remove.
2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (mve_insn): Add vsri.
* config/arm/mve.md (mve_vsriq_n_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_n_<supf><mode>): .,. this.
(mve_vsriq_m_n_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-shapes.cc (ternary_rshift): New.
* config/arm/arm-mve-builtins-shapes.h (ternary_rshift): New.
2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (vsliq): New.
* config/arm/arm-mve-builtins-base.def (vsliq): New.
* config/arm/arm-mve-builtins-base.h (vsliq): New.
* config/arm/arm-mve-builtins.cc
(function_instance::has_inactive_argument): Handle vsliq.
* config/arm/arm_mve.h (vsliq): Remove.
(vsliq_m): Remove.
(vsliq_n_u8): Remove.
(vsliq_n_s8): Remove.
(vsliq_n_u16): Remove.
(vsliq_n_s16): Remove.
(vsliq_n_u32): Remove.
(vsliq_n_s32): Remove.
(vsliq_m_n_s8): Remove.
(vsliq_m_n_s32): Remove.
(vsliq_m_n_s16): Remove.
(vsliq_m_n_u8): Remove.
(vsliq_m_n_u32): Remove.
(vsliq_m_n_u16): Remove.
(__arm_vsliq_n_u8): Remove.
(__arm_vsliq_n_s8): Remove.
(__arm_vsliq_n_u16): Remove.
(__arm_vsliq_n_s16): Remove.
(__arm_vsliq_n_u32): Remove.
(__arm_vsliq_n_s32): Remove.
(__arm_vsliq_m_n_s8): Remove.
(__arm_vsliq_m_n_s32): Remove.
(__arm_vsliq_m_n_s16): Remove.
(__arm_vsliq_m_n_u8): Remove.
(__arm_vsliq_m_n_u32): Remove.
(__arm_vsliq_m_n_u16): Remove.
(__arm_vsliq): Remove.
(__arm_vsliq_m): Remove.
2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (mve_insn>): Add vsli.
* config/arm/mve.md (mve_vsliq_n_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_n_<supf><mode>): ... this.
(mve_vsliq_m_n_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-shapes.cc (ternary_lshift): New.
* config/arm/arm-mve-builtins-shapes.h (ternary_lshift): New.
2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (vpselq): New.
* config/arm/arm-mve-builtins-base.def (vpselq): New.
* config/arm/arm-mve-builtins-base.h (vpselq): New.
* config/arm/arm_mve.h (vpselq): Remove.
(vpselq_u8): Remove.
(vpselq_s8): Remove.
(vpselq_u16): Remove.
(vpselq_s16): Remove.
(vpselq_u32): Remove.
(vpselq_s32): Remove.
(vpselq_u64): Remove.
(vpselq_s64): Remove.
(vpselq_f16): Remove.
(vpselq_f32): Remove.
(__arm_vpselq_u8): Remove.
(__arm_vpselq_s8): Remove.
(__arm_vpselq_u16): Remove.
(__arm_vpselq_s16): Remove.
(__arm_vpselq_u32): Remove.
(__arm_vpselq_s32): Remove.
(__arm_vpselq_u64): Remove.
(__arm_vpselq_s64): Remove.
(__arm_vpselq_f16): Remove.
(__arm_vpselq_f32): Remove.
(__arm_vpselq): Remove.
2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-shapes.cc (vpsel): New.
* config/arm/arm-mve-builtins-shapes.h (vpsel): New.
2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm.cc (arm_expand_vcond): Use gen_mve_q instead of
gen_mve_vpselq.
* config/arm/iterators.md (MVE_VPSELQ_F): New.
(mve_insn): Add vpsel.
* config/arm/mve.md (@mve_vpselq_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_<supf><mode>): ... this.
(@mve_vpselq_f<mode>): Rename into ...
(@mve_<mve_insn>q_f<mode>): ... this.
2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (vfmaq, vfmasq, vfmsq): New.
* config/arm/arm-mve-builtins-base.def (vfmaq, vfmasq, vfmsq): New.
* config/arm/arm-mve-builtins-base.h (vfmaq, vfmasq, vfmsq): New.
* config/arm/arm-mve-builtins.cc
(function_instance::has_inactive_argument): Handle vfmaq, vfmasq,
vfmsq.
* config/arm/arm_mve.h (vfmaq): Remove.
(vfmasq): Remove.
(vfmsq): Remove.
(vfmaq_m): Remove.
(vfmasq_m): Remove.
(vfmsq_m): Remove.
(vfmaq_f16): Remove.
(vfmaq_n_f16): Remove.
(vfmasq_n_f16): Remove.
(vfmsq_f16): Remove.
(vfmaq_f32): Remove.
(vfmaq_n_f32): Remove.
(vfmasq_n_f32): Remove.
(vfmsq_f32): Remove.
(vfmaq_m_f32): Remove.
(vfmaq_m_f16): Remove.
(vfmaq_m_n_f32): Remove.
(vfmaq_m_n_f16): Remove.
(vfmasq_m_n_f32): Remove.
(vfmasq_m_n_f16): Remove.
(vfmsq_m_f32): Remove.
(vfmsq_m_f16): Remove.
(__arm_vfmaq_f16): Remove.
(__arm_vfmaq_n_f16): Remove.
(__arm_vfmasq_n_f16): Remove.
(__arm_vfmsq_f16): Remove.
(__arm_vfmaq_f32): Remove.
(__arm_vfmaq_n_f32): Remove.
(__arm_vfmasq_n_f32): Remove.
(__arm_vfmsq_f32): Remove.
(__arm_vfmaq_m_f32): Remove.
(__arm_vfmaq_m_f16): Remove.
(__arm_vfmaq_m_n_f32): Remove.
(__arm_vfmaq_m_n_f16): Remove.
(__arm_vfmasq_m_n_f32): Remove.
(__arm_vfmasq_m_n_f16): Remove.
(__arm_vfmsq_m_f32): Remove.
(__arm_vfmsq_m_f16): Remove.
(__arm_vfmaq): Remove.
(__arm_vfmasq): Remove.
(__arm_vfmsq): Remove.
(__arm_vfmaq_m): Remove.
(__arm_vfmasq_m): Remove.
(__arm_vfmsq_m): Remove.
2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (MVE_FP_M_BINARY): Add VFMAQ_M_F,
VFMSQ_M_F.
(MVE_FP_M_N_BINARY): Add VFMAQ_M_N_F, VFMASQ_M_N_F.
(MVE_VFMxQ_F, MVE_VFMAxQ_N_F): New.
(mve_insn): Add vfma, vfmas, vfms.
* config/arm/mve.md (mve_vfmaq_f<mode>, mve_vfmsq_f<mode>): Merge
into ...
(@mve_<mve_insn>q_f<mode>): ... this.
(mve_vfmaq_n_f<mode>, mve_vfmasq_n_f<mode>): Merge into ...
(@mve_<mve_insn>q_n_f<mode>): ... this.
(mve_vfmaq_m_f<mode>, mve_vfmsq_m_f<mode>): Merge into
@mve_<mve_insn>q_m_f<mode>.
(mve_vfmaq_m_n_f<mode>, mve_vfmasq_m_n_f<mode>): Merge into
@mve_<mve_insn>q_m_n_f<mode>.
2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-shapes.cc (ternary_opt_n): New.
* config/arm/arm-mve-builtins-shapes.h (ternary_opt_n): New.
2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc
(FUNCTION_WITH_RTX_M_N_NO_F): New.
(vmvnq): New.
* config/arm/arm-mve-builtins-base.def (vmvnq): New.
* config/arm/arm-mve-builtins-base.h (vmvnq): New.
* config/arm/arm_mve.h (vmvnq): Remove.
(vmvnq_m): Remove.
(vmvnq_x): Remove.
(vmvnq_s8): Remove.
(vmvnq_s16): Remove.
(vmvnq_s32): Remove.
(vmvnq_n_s16): Remove.
(vmvnq_n_s32): Remove.
(vmvnq_u8): Remove.
(vmvnq_u16): Remove.
(vmvnq_u32): Remove.
(vmvnq_n_u16): Remove.
(vmvnq_n_u32): Remove.
(vmvnq_m_u8): Remove.
(vmvnq_m_s8): Remove.
(vmvnq_m_u16): Remove.
(vmvnq_m_s16): Remove.
(vmvnq_m_u32): Remove.
(vmvnq_m_s32): Remove.
(vmvnq_m_n_s16): Remove.
(vmvnq_m_n_u16): Remove.
(vmvnq_m_n_s32): Remove.
(vmvnq_m_n_u32): Remove.
(vmvnq_x_s8): Remove.
(vmvnq_x_s16): Remove.
(vmvnq_x_s32): Remove.
(vmvnq_x_u8): Remove.
(vmvnq_x_u16): Remove.
(vmvnq_x_u32): Remove.
(vmvnq_x_n_s16): Remove.
(vmvnq_x_n_s32): Remove.
(vmvnq_x_n_u16): Remove.
(vmvnq_x_n_u32): Remove.
(__arm_vmvnq_s8): Remove.
(__arm_vmvnq_s16): Remove.
(__arm_vmvnq_s32): Remove.
(__arm_vmvnq_n_s16): Remove.
(__arm_vmvnq_n_s32): Remove.
(__arm_vmvnq_u8): Remove.
(__arm_vmvnq_u16): Remove.
(__arm_vmvnq_u32): Remove.
(__arm_vmvnq_n_u16): Remove.
(__arm_vmvnq_n_u32): Remove.
(__arm_vmvnq_m_u8): Remove.
(__arm_vmvnq_m_s8): Remove.
(__arm_vmvnq_m_u16): Remove.
(__arm_vmvnq_m_s16): Remove.
(__arm_vmvnq_m_u32): Remove.
(__arm_vmvnq_m_s32): Remove.
(__arm_vmvnq_m_n_s16): Remove.
(__arm_vmvnq_m_n_u16): Remove.
(__arm_vmvnq_m_n_s32): Remove.
(__arm_vmvnq_m_n_u32): Remove.
(__arm_vmvnq_x_s8): Remove.
(__arm_vmvnq_x_s16): Remove.
(__arm_vmvnq_x_s32): Remove.
(__arm_vmvnq_x_u8): Remove.
(__arm_vmvnq_x_u16): Remove.
(__arm_vmvnq_x_u32): Remove.
(__arm_vmvnq_x_n_s16): Remove.
(__arm_vmvnq_x_n_s32): Remove.
(__arm_vmvnq_x_n_u16): Remove.
(__arm_vmvnq_x_n_u32): Remove.
(__arm_vmvnq): Remove.
(__arm_vmvnq_m): Remove.
(__arm_vmvnq_x): Remove.
2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (mve_insn): Add vmvn.
* config/arm/mve.md (mve_vmvnq_n_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_n_<supf><mode>): ... this.
(mve_vmvnq_m_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_m_<supf><mode>): ... this.
(mve_vmvnq_m_n_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-shapes.cc (mvn): New.
* config/arm/arm-mve-builtins-shapes.h (mvn): New.
2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (vbrsrq): New.
* config/arm/arm-mve-builtins-base.def (vbrsrq): New.
* config/arm/arm-mve-builtins-base.h (vbrsrq): New.
* config/arm/arm_mve.h (vbrsrq): Remove.
(vbrsrq_m): Remove.
(vbrsrq_x): Remove.
(vbrsrq_n_f16): Remove.
(vbrsrq_n_f32): Remove.
(vbrsrq_n_u8): Remove.
(vbrsrq_n_s8): Remove.
(vbrsrq_n_u16): Remove.
(vbrsrq_n_s16): Remove.
(vbrsrq_n_u32): Remove.
(vbrsrq_n_s32): Remove.
(vbrsrq_m_n_s8): Remove.
(vbrsrq_m_n_s32): Remove.
(vbrsrq_m_n_s16): Remove.
(vbrsrq_m_n_u8): Remove.
(vbrsrq_m_n_u32): Remove.
(vbrsrq_m_n_u16): Remove.
(vbrsrq_m_n_f32): Remove.
(vbrsrq_m_n_f16): Remove.
(vbrsrq_x_n_s8): Remove.
(vbrsrq_x_n_s16): Remove.
(vbrsrq_x_n_s32): Remove.
(vbrsrq_x_n_u8): Remove.
(vbrsrq_x_n_u16): Remove.
(vbrsrq_x_n_u32): Remove.
(vbrsrq_x_n_f16): Remove.
(vbrsrq_x_n_f32): Remove.
(__arm_vbrsrq_n_u8): Remove.
(__arm_vbrsrq_n_s8): Remove.
(__arm_vbrsrq_n_u16): Remove.
(__arm_vbrsrq_n_s16): Remove.
(__arm_vbrsrq_n_u32): Remove.
(__arm_vbrsrq_n_s32): Remove.
(__arm_vbrsrq_m_n_s8): Remove.
(__arm_vbrsrq_m_n_s32): Remove.
(__arm_vbrsrq_m_n_s16): Remove.
(__arm_vbrsrq_m_n_u8): Remove.
(__arm_vbrsrq_m_n_u32): Remove.
(__arm_vbrsrq_m_n_u16): Remove.
(__arm_vbrsrq_x_n_s8): Remove.
(__arm_vbrsrq_x_n_s16): Remove.
(__arm_vbrsrq_x_n_s32): Remove.
(__arm_vbrsrq_x_n_u8): Remove.
(__arm_vbrsrq_x_n_u16): Remove.
(__arm_vbrsrq_x_n_u32): Remove.
(__arm_vbrsrq_n_f16): Remove.
(__arm_vbrsrq_n_f32): Remove.
(__arm_vbrsrq_m_n_f32): Remove.
(__arm_vbrsrq_m_n_f16): Remove.
(__arm_vbrsrq_x_n_f16): Remove.
(__arm_vbrsrq_x_n_f32): Remove.
(__arm_vbrsrq): Remove.
(__arm_vbrsrq_m): Remove.
(__arm_vbrsrq_x): Remove.
2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (MVE_VBRSR_M_N_FP, MVE_VBRSR_N_FP): New.
(mve_insn): Add vbrsr.
* config/arm/mve.md (mve_vbrsrq_n_f<mode>): Rename into ...
(@mve_<mve_insn>q_n_f<mode>): ... this.
(mve_vbrsrq_n_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_n_<supf><mode>): ... this.
(mve_vbrsrq_m_n_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
(mve_vbrsrq_m_n_f<mode>): Rename into ...
(@mve_<mve_insn>q_m_n_f<mode>): ... this.
2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-shapes.cc (binary_imm32): New.
* config/arm/arm-mve-builtins-shapes.h (binary_imm32): New.
2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (vqshluq): New.
* config/arm/arm-mve-builtins-base.def (vqshluq): New.
* config/arm/arm-mve-builtins-base.h (vqshluq): New.
* config/arm/arm_mve.h (vqshluq): Remove.
(vqshluq_m): Remove.
(vqshluq_n_s8): Remove.
(vqshluq_n_s16): Remove.
(vqshluq_n_s32): Remove.
(vqshluq_m_n_s8): Remove.
(vqshluq_m_n_s16): Remove.
(vqshluq_m_n_s32): Remove.
(__arm_vqshluq_n_s8): Remove.
(__arm_vqshluq_n_s16): Remove.
(__arm_vqshluq_n_s32): Remove.
(__arm_vqshluq_m_n_s8): Remove.
(__arm_vqshluq_m_n_s16): Remove.
(__arm_vqshluq_m_n_s32): Remove.
(__arm_vqshluq): Remove.
(__arm_vqshluq_m): Remove.
2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (mve_insn): Add vqshlu.
(supf): Add VQSHLUQ_M_N_S, VQSHLUQ_N_S.
(VQSHLUQ_M_N, VQSHLUQ_N): New.
* config/arm/mve.md (mve_vqshluq_n_s<mode>): Change name into ...
(@mve_<mve_insn>q_n_<supf><mode>): ... this.
(mve_vqshluq_m_n_s<mode>): Change name into ...
(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-shapes.cc
(binary_lshift_unsigned): New.
* config/arm/arm-mve-builtins-shapes.h
(binary_lshift_unsigned): New.
2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (vrmlaldavhaq)
(vrmlaldavhaxq, vrmlsldavhaq, vrmlsldavhaxq): New.
* config/arm/arm-mve-builtins-base.def (vrmlaldavhaq)
(vrmlaldavhaxq, vrmlsldavhaq, vrmlsldavhaxq): New.
* config/arm/arm-mve-builtins-base.h (vrmlaldavhaq)
(vrmlaldavhaxq, vrmlsldavhaq, vrmlsldavhaxq): New.
* config/arm/arm-mve-builtins-functions.h: Handle vrmlaldavhaq,
vrmlaldavhaxq, vrmlsldavhaq, vrmlsldavhaxq.
* config/arm/arm_mve.h (vrmlaldavhaq): Remove.
(vrmlaldavhaxq): Remove.
(vrmlsldavhaq): Remove.
(vrmlsldavhaxq): Remove.
(vrmlaldavhaq_p): Remove.
(vrmlaldavhaxq_p): Remove.
(vrmlsldavhaq_p): Remove.
(vrmlsldavhaxq_p): Remove.
(vrmlaldavhaq_s32): Remove.
(vrmlaldavhaq_u32): Remove.
(vrmlaldavhaxq_s32): Remove.
(vrmlsldavhaq_s32): Remove.
(vrmlsldavhaxq_s32): Remove.
(vrmlaldavhaq_p_s32): Remove.
(vrmlaldavhaq_p_u32): Remove.
(vrmlaldavhaxq_p_s32): Remove.
(vrmlsldavhaq_p_s32): Remove.
(vrmlsldavhaxq_p_s32): Remove.
(__arm_vrmlaldavhaq_s32): Remove.
(__arm_vrmlaldavhaq_u32): Remove.
(__arm_vrmlaldavhaxq_s32): Remove.
(__arm_vrmlsldavhaq_s32): Remove.
(__arm_vrmlsldavhaxq_s32): Remove.
(__arm_vrmlaldavhaq_p_s32): Remove.
(__arm_vrmlaldavhaq_p_u32): Remove.
(__arm_vrmlaldavhaxq_p_s32): Remove.
(__arm_vrmlsldavhaq_p_s32): Remove.
(__arm_vrmlsldavhaxq_p_s32): Remove.
(__arm_vrmlaldavhaq): Remove.
(__arm_vrmlaldavhaxq): Remove.
(__arm_vrmlsldavhaq): Remove.
(__arm_vrmlsldavhaxq): Remove.
(__arm_vrmlaldavhaq_p): Remove.
(__arm_vrmlaldavhaxq_p): Remove.
(__arm_vrmlsldavhaq_p): Remove.
(__arm_vrmlsldavhaxq_p): Remove.
2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (MVE_VRMLxLDAVHAxQ)
(MVE_VRMLxLDAVHAxQ_P): New.
(mve_insn): Add vrmlaldavha, vrmlaldavhax, vrmlsldavha,
vrmlsldavhax.
(supf): Add VRMLALDAVHAXQ_P_S, VRMLALDAVHAXQ_S, VRMLSLDAVHAQ_P_S,
VRMLSLDAVHAQ_S, VRMLSLDAVHAXQ_P_S, VRMLSLDAVHAXQ_S,
VRMLALDAVHAQ_P_S.
* config/arm/mve.md (mve_vrmlaldavhaq_<supf>v4si)
(mve_vrmlaldavhaxq_sv4si, mve_vrmlsldavhaxq_sv4si)
(mve_vrmlsldavhaq_sv4si): Merge into ...
(@mve_<mve_insn>q_<supf>v4si): ... this.
(mve_vrmlaldavhaq_p_sv4si, mve_vrmlaldavhaq_p_uv4si)
(mve_vrmlaldavhaxq_p_sv4si, mve_vrmlsldavhaq_p_sv4si)
(mve_vrmlsldavhaxq_p_sv4si): Merge into ...
(@mve_<mve_insn>q_p_<supf>v4si): ... this.
2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (vqdmullbq, vqdmulltq): New.
* config/arm/arm-mve-builtins-base.def (vqdmullbq, vqdmulltq):
New.
* config/arm/arm-mve-builtins-base.h (vqdmullbq, vqdmulltq): New.
* config/arm/arm_mve.h (vqdmulltq): Remove.
(vqdmullbq): Remove.
(vqdmullbq_m): Remove.
(vqdmulltq_m): Remove.
(vqdmulltq_s16): Remove.
(vqdmulltq_n_s16): Remove.
(vqdmullbq_s16): Remove.
(vqdmullbq_n_s16): Remove.
(vqdmulltq_s32): Remove.
(vqdmulltq_n_s32): Remove.
(vqdmullbq_s32): Remove.
(vqdmullbq_n_s32): Remove.
(vqdmullbq_m_n_s32): Remove.
(vqdmullbq_m_n_s16): Remove.
(vqdmullbq_m_s32): Remove.
(vqdmullbq_m_s16): Remove.
(vqdmulltq_m_n_s32): Remove.
(vqdmulltq_m_n_s16): Remove.
(vqdmulltq_m_s32): Remove.
(vqdmulltq_m_s16): Remove.
(__arm_vqdmulltq_s16): Remove.
(__arm_vqdmulltq_n_s16): Remove.
(__arm_vqdmullbq_s16): Remove.
(__arm_vqdmullbq_n_s16): Remove.
(__arm_vqdmulltq_s32): Remove.
(__arm_vqdmulltq_n_s32): Remove.
(__arm_vqdmullbq_s32): Remove.
(__arm_vqdmullbq_n_s32): Remove.
(__arm_vqdmullbq_m_n_s32): Remove.
(__arm_vqdmullbq_m_n_s16): Remove.
(__arm_vqdmullbq_m_s32): Remove.
(__arm_vqdmullbq_m_s16): Remove.
(__arm_vqdmulltq_m_n_s32): Remove.
(__arm_vqdmulltq_m_n_s16): Remove.
(__arm_vqdmulltq_m_s32): Remove.
(__arm_vqdmulltq_m_s16): Remove.
(__arm_vqdmulltq): Remove.
(__arm_vqdmullbq): Remove.
(__arm_vqdmullbq_m): Remove.
(__arm_vqdmulltq_m): Remove.
2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (MVE_VQDMULLxQ, MVE_VQDMULLxQ_M)
(MVE_VQDMULLxQ_M_N, MVE_VQDMULLxQ_N): New.
(mve_insn): Add vqdmullb, vqdmullt.
(supf): Add VQDMULLBQ_S, VQDMULLBQ_M_S, VQDMULLBQ_M_N_S,
VQDMULLBQ_N_S, VQDMULLTQ_S, VQDMULLTQ_M_S, VQDMULLTQ_M_N_S,
VQDMULLTQ_N_S.
* config/arm/mve.md (mve_vqdmullbq_n_s<mode>)
(mve_vqdmulltq_n_s<mode>): Merge into ...
(@mve_<mve_insn>q_n_<supf><mode>): ... this.
(mve_vqdmullbq_s<mode>, mve_vqdmulltq_s<mode>): Merge into ...
(@mve_<mve_insn>q_<supf><mode>): ... this.
(mve_vqdmullbq_m_n_s<mode>, mve_vqdmulltq_m_n_s<mode>): Merge into
...
(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
(mve_vqdmullbq_m_s<mode>, mve_vqdmulltq_m_s<mode>): Merge into ...
(@mve_<mve_insn>q_m_<supf><mode>): ... this.
2023-05-12 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-shapes.cc (binary_widen_opt_n): New.
* config/arm/arm-mve-builtins-shapes.h (binary_widen_opt_n): New.
2023-05-12 Kito Cheng <kito.cheng@sifive.com>
* common/config/riscv/riscv-common.cc (riscv_select_multilib_by_abi):
Drop unused parameter.
(riscv_select_multilib): Ditto.
(riscv_compute_multilib): Update call site of
riscv_select_multilib_by_abi and riscv_select_multilib_by_abi.
2023-05-12 Juzhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/autovec.md (vec_init<mode><vel>): New pattern.
* config/riscv/riscv-protos.h (expand_vec_init): New function.
* config/riscv/riscv-v.cc (class rvv_builder): New class.
(rvv_builder::can_duplicate_repeating_sequence_p): New function.
(rvv_builder::get_merged_repeating_sequence): Ditto.
(expand_vector_init_insert_elems): Ditto.
(expand_vec_init): Ditto.
* config/riscv/vector-iterators.md: New attribute.
2023-05-12 Haochen Gui <guihaoc@gcc.gnu.org>
* config/rs6000/rs6000-builtins.def
(__builtin_vsx_scalar_insert_exp): Replace bif-pattern from xsiexpdp
to xsiexpdp_di.
(__builtin_vsx_scalar_insert_exp_dp): Replace bif-pattern from
xsiexpdpf to xsiexpdpf_di.
* config/rs6000/vsx.md (xsiexpdp): Rename to...
(xsiexpdp_<mode>): ..., set the mode of second operand to GPR and
replace TARGET_64BIT with TARGET_POWERPC64.
(xsiexpdpf): Rename to...
(xsiexpdpf_<mode>): ..., set the mode of second operand to GPR and
replace TARGET_64BIT with TARGET_POWERPC64.
2023-05-12 Haochen Gui <guihaoc@gcc.gnu.org>
* config/rs6000/rs6000-builtins.def
(__builtin_vsx_scalar_extract_sig): Set return type to const signed
long long.
* config/rs6000/vsx.md (xsxsigdp): Replace TARGET_64BIT with
TARGET_POWERPC64.
2023-05-12 Haochen Gui <guihaoc@gcc.gnu.org>
* config/rs6000/rs6000-builtins.def
(__builtin_vsx_scalar_extract_exp): Set return type to const signed
int and set its bif-pattern to xsxexpdp_si, move it from power9-64
to power9 catalog.
* config/rs6000/vsx.md (xsxexpdp): Rename to ...
(xsxexpdp_<mode>): ..., set mode of operand 0 to GPR and remove
TARGET_64BIT check.
* doc/extend.texi (scalar_extract_exp): Remove 64-bit environment
requirement when it has a 64-bit argument.
2023-05-12 Pan Li <pan2.li@intel.com>
Richard Sandiford <richard.sandiford@arm.com>
Richard Biener <rguenther@suse.de>
Jakub Jelinek <jakub@redhat.com>
* mux-utils.h: Add overload operator == and != for pointer_mux.
* var-tracking.cc: Included mux-utils.h for pointer_tmux.
(decl_or_value): Changed from void * to pointer_mux<tree_node, rtx_def>.
(dv_is_decl_p): Reconciled to the new type, aka pointer_mux.
(dv_as_decl): Ditto.
(dv_as_opaque): Removed due to unnecessary.
(struct variable_hasher): Take decl_or_value as compare_type.
(variable_hasher::equal): Diito.
(dv_from_decl): Reconciled to the new type, aka pointer_mux.
(dv_from_value): Ditto.
(attrs_list_member): Ditto.
(vars_copy): Ditto.
(var_reg_decl_set): Ditto.
(var_reg_delete_and_set): Ditto.
(find_loc_in_1pdv): Ditto.
(canonicalize_values_star): Ditto.
(variable_post_merge_new_vals): Ditto.
(dump_onepart_variable_differences): Ditto.
(variable_different_p): Ditto.
(set_slot_part): Ditto.
(clobber_slot_part): Ditto.
(clobber_variable_part): Ditto.
2023-05-11 mtsamis <manolis.tsamis@vrull.eu>
* match.pd: simplify vector shift + bit_and + multiply.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (vmlaq, vmlasq, vqdmlahq)
(vqdmlashq, vqrdmlahq, vqrdmlashq): New.
* config/arm/arm-mve-builtins-base.def (vmlaq, vmlasq, vqdmlahq)
(vqdmlashq, vqrdmlahq, vqrdmlashq): New.
* config/arm/arm-mve-builtins-base.h (vmlaq, vmlasq, vqdmlahq)
(vqdmlashq, vqrdmlahq, vqrdmlashq): New.
* config/arm/arm-mve-builtins.cc
(function_instance::has_inactive_argument): Handle vmlaq, vmlasq,
vqdmlahq, vqdmlashq, vqrdmlahq, vqrdmlashq.
* config/arm/arm_mve.h (vqrdmlashq): Remove.
(vqrdmlahq): Remove.
(vqdmlashq): Remove.
(vqdmlahq): Remove.
(vmlasq): Remove.
(vmlaq): Remove.
(vmlaq_m): Remove.
(vmlasq_m): Remove.
(vqdmlashq_m): Remove.
(vqdmlahq_m): Remove.
(vqrdmlahq_m): Remove.
(vqrdmlashq_m): Remove.
(vmlasq_n_u8): Remove.
(vmlaq_n_u8): Remove.
(vqrdmlashq_n_s8): Remove.
(vqrdmlahq_n_s8): Remove.
(vqdmlahq_n_s8): Remove.
(vqdmlashq_n_s8): Remove.
(vmlasq_n_s8): Remove.
(vmlaq_n_s8): Remove.
(vmlasq_n_u16): Remove.
(vmlaq_n_u16): Remove.
(vqrdmlashq_n_s16): Remove.
(vqrdmlahq_n_s16): Remove.
(vqdmlashq_n_s16): Remove.
(vqdmlahq_n_s16): Remove.
(vmlasq_n_s16): Remove.
(vmlaq_n_s16): Remove.
(vmlasq_n_u32): Remove.
(vmlaq_n_u32): Remove.
(vqrdmlashq_n_s32): Remove.
(vqrdmlahq_n_s32): Remove.
(vqdmlashq_n_s32): Remove.
(vqdmlahq_n_s32): Remove.
(vmlasq_n_s32): Remove.
(vmlaq_n_s32): Remove.
(vmlaq_m_n_s8): Remove.
(vmlaq_m_n_s32): Remove.
(vmlaq_m_n_s16): Remove.
(vmlaq_m_n_u8): Remove.
(vmlaq_m_n_u32): Remove.
(vmlaq_m_n_u16): Remove.
(vmlasq_m_n_s8): Remove.
(vmlasq_m_n_s32): Remove.
(vmlasq_m_n_s16): Remove.
(vmlasq_m_n_u8): Remove.
(vmlasq_m_n_u32): Remove.
(vmlasq_m_n_u16): Remove.
(vqdmlashq_m_n_s8): Remove.
(vqdmlashq_m_n_s32): Remove.
(vqdmlashq_m_n_s16): Remove.
(vqdmlahq_m_n_s8): Remove.
(vqdmlahq_m_n_s32): Remove.
(vqdmlahq_m_n_s16): Remove.
(vqrdmlahq_m_n_s8): Remove.
(vqrdmlahq_m_n_s32): Remove.
(vqrdmlahq_m_n_s16): Remove.
(vqrdmlashq_m_n_s8): Remove.
(vqrdmlashq_m_n_s32): Remove.
(vqrdmlashq_m_n_s16): Remove.
(__arm_vmlasq_n_u8): Remove.
(__arm_vmlaq_n_u8): Remove.
(__arm_vqrdmlashq_n_s8): Remove.
(__arm_vqdmlashq_n_s8): Remove.
(__arm_vqrdmlahq_n_s8): Remove.
(__arm_vqdmlahq_n_s8): Remove.
(__arm_vmlasq_n_s8): Remove.
(__arm_vmlaq_n_s8): Remove.
(__arm_vmlasq_n_u16): Remove.
(__arm_vmlaq_n_u16): Remove.
(__arm_vqrdmlashq_n_s16): Remove.
(__arm_vqdmlashq_n_s16): Remove.
(__arm_vqrdmlahq_n_s16): Remove.
(__arm_vqdmlahq_n_s16): Remove.
(__arm_vmlasq_n_s16): Remove.
(__arm_vmlaq_n_s16): Remove.
(__arm_vmlasq_n_u32): Remove.
(__arm_vmlaq_n_u32): Remove.
(__arm_vqrdmlashq_n_s32): Remove.
(__arm_vqdmlashq_n_s32): Remove.
(__arm_vqrdmlahq_n_s32): Remove.
(__arm_vqdmlahq_n_s32): Remove.
(__arm_vmlasq_n_s32): Remove.
(__arm_vmlaq_n_s32): Remove.
(__arm_vmlaq_m_n_s8): Remove.
(__arm_vmlaq_m_n_s32): Remove.
(__arm_vmlaq_m_n_s16): Remove.
(__arm_vmlaq_m_n_u8): Remove.
(__arm_vmlaq_m_n_u32): Remove.
(__arm_vmlaq_m_n_u16): Remove.
(__arm_vmlasq_m_n_s8): Remove.
(__arm_vmlasq_m_n_s32): Remove.
(__arm_vmlasq_m_n_s16): Remove.
(__arm_vmlasq_m_n_u8): Remove.
(__arm_vmlasq_m_n_u32): Remove.
(__arm_vmlasq_m_n_u16): Remove.
(__arm_vqdmlahq_m_n_s8): Remove.
(__arm_vqdmlahq_m_n_s32): Remove.
(__arm_vqdmlahq_m_n_s16): Remove.
(__arm_vqrdmlahq_m_n_s8): Remove.
(__arm_vqrdmlahq_m_n_s32): Remove.
(__arm_vqrdmlahq_m_n_s16): Remove.
(__arm_vqrdmlashq_m_n_s8): Remove.
(__arm_vqrdmlashq_m_n_s32): Remove.
(__arm_vqrdmlashq_m_n_s16): Remove.
(__arm_vqdmlashq_m_n_s8): Remove.
(__arm_vqdmlashq_m_n_s16): Remove.
(__arm_vqdmlashq_m_n_s32): Remove.
(__arm_vmlasq): Remove.
(__arm_vmlaq): Remove.
(__arm_vqrdmlashq): Remove.
(__arm_vqdmlashq): Remove.
(__arm_vqrdmlahq): Remove.
(__arm_vqdmlahq): Remove.
(__arm_vmlaq_m): Remove.
(__arm_vmlasq_m): Remove.
(__arm_vqdmlahq_m): Remove.
(__arm_vqrdmlahq_m): Remove.
(__arm_vqrdmlashq_m): Remove.
(__arm_vqdmlashq_m): Remove.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (MVE_VMLxQ_N): New.
(mve_insn): Add vmla, vmlas, vqdmlah, vqdmlash, vqrdmlah,
vqrdmlash.
(supf): Add VQDMLAHQ_N_S, VQDMLASHQ_N_S, VQRDMLAHQ_N_S,
VQRDMLASHQ_N_S.
* config/arm/mve.md (mve_vmlaq_n_<supf><mode>)
(mve_vmlasq_n_<supf><mode>, mve_vqdmlahq_n_<supf><mode>)
(mve_vqdmlashq_n_<supf><mode>, mve_vqrdmlahq_n_<supf><mode>)
(mve_vqrdmlashq_n_<supf><mode>): Merge into ...
(@mve_<mve_insn>q_n_<supf><mode>): ... this.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-shapes.cc (ternary_n): New.
* config/arm/arm-mve-builtins-shapes.h (ternary_n): New.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (vqdmladhq, vqdmladhxq)
(vqdmlsdhq, vqdmlsdhxq, vqrdmladhq, vqrdmladhxq, vqrdmlsdhq)
(vqrdmlsdhxq): New.
* config/arm/arm-mve-builtins-base.def (vqdmladhq, vqdmladhxq)
(vqdmlsdhq, vqdmlsdhxq, vqrdmladhq, vqrdmladhxq, vqrdmlsdhq)
(vqrdmlsdhxq): New.
* config/arm/arm-mve-builtins-base.h (vqdmladhq, vqdmladhxq)
(vqdmlsdhq, vqdmlsdhxq, vqrdmladhq, vqrdmladhxq, vqrdmlsdhq)
(vqrdmlsdhxq): New.
* config/arm/arm-mve-builtins.cc
(function_instance::has_inactive_argument): Handle vqrdmladhq,
vqrdmladhxq, vqrdmlsdhq, vqrdmlsdhxq vqdmladhq, vqdmladhxq,
vqdmlsdhq, vqdmlsdhxq.
* config/arm/arm_mve.h (vqrdmlsdhxq): Remove.
(vqrdmlsdhq): Remove.
(vqrdmladhxq): Remove.
(vqrdmladhq): Remove.
(vqdmlsdhxq): Remove.
(vqdmlsdhq): Remove.
(vqdmladhxq): Remove.
(vqdmladhq): Remove.
(vqdmladhq_m): Remove.
(vqdmladhxq_m): Remove.
(vqdmlsdhq_m): Remove.
(vqdmlsdhxq_m): Remove.
(vqrdmladhq_m): Remove.
(vqrdmladhxq_m): Remove.
(vqrdmlsdhq_m): Remove.
(vqrdmlsdhxq_m): Remove.
(vqrdmlsdhxq_s8): Remove.
(vqrdmlsdhq_s8): Remove.
(vqrdmladhxq_s8): Remove.
(vqrdmladhq_s8): Remove.
(vqdmlsdhxq_s8): Remove.
(vqdmlsdhq_s8): Remove.
(vqdmladhxq_s8): Remove.
(vqdmladhq_s8): Remove.
(vqrdmlsdhxq_s16): Remove.
(vqrdmlsdhq_s16): Remove.
(vqrdmladhxq_s16): Remove.
(vqrdmladhq_s16): Remove.
(vqdmlsdhxq_s16): Remove.
(vqdmlsdhq_s16): Remove.
(vqdmladhxq_s16): Remove.
(vqdmladhq_s16): Remove.
(vqrdmlsdhxq_s32): Remove.
(vqrdmlsdhq_s32): Remove.
(vqrdmladhxq_s32): Remove.
(vqrdmladhq_s32): Remove.
(vqdmlsdhxq_s32): Remove.
(vqdmlsdhq_s32): Remove.
(vqdmladhxq_s32): Remove.
(vqdmladhq_s32): Remove.
(vqdmladhq_m_s8): Remove.
(vqdmladhq_m_s32): Remove.
(vqdmladhq_m_s16): Remove.
(vqdmladhxq_m_s8): Remove.
(vqdmladhxq_m_s32): Remove.
(vqdmladhxq_m_s16): Remove.
(vqdmlsdhq_m_s8): Remove.
(vqdmlsdhq_m_s32): Remove.
(vqdmlsdhq_m_s16): Remove.
(vqdmlsdhxq_m_s8): Remove.
(vqdmlsdhxq_m_s32): Remove.
(vqdmlsdhxq_m_s16): Remove.
(vqrdmladhq_m_s8): Remove.
(vqrdmladhq_m_s32): Remove.
(vqrdmladhq_m_s16): Remove.
(vqrdmladhxq_m_s8): Remove.
(vqrdmladhxq_m_s32): Remove.
(vqrdmladhxq_m_s16): Remove.
(vqrdmlsdhq_m_s8): Remove.
(vqrdmlsdhq_m_s32): Remove.
(vqrdmlsdhq_m_s16): Remove.
(vqrdmlsdhxq_m_s8): Remove.
(vqrdmlsdhxq_m_s32): Remove.
(vqrdmlsdhxq_m_s16): Remove.
(__arm_vqrdmlsdhxq_s8): Remove.
(__arm_vqrdmlsdhq_s8): Remove.
(__arm_vqrdmladhxq_s8): Remove.
(__arm_vqrdmladhq_s8): Remove.
(__arm_vqdmlsdhxq_s8): Remove.
(__arm_vqdmlsdhq_s8): Remove.
(__arm_vqdmladhxq_s8): Remove.
(__arm_vqdmladhq_s8): Remove.
(__arm_vqrdmlsdhxq_s16): Remove.
(__arm_vqrdmlsdhq_s16): Remove.
(__arm_vqrdmladhxq_s16): Remove.
(__arm_vqrdmladhq_s16): Remove.
(__arm_vqdmlsdhxq_s16): Remove.
(__arm_vqdmlsdhq_s16): Remove.
(__arm_vqdmladhxq_s16): Remove.
(__arm_vqdmladhq_s16): Remove.
(__arm_vqrdmlsdhxq_s32): Remove.
(__arm_vqrdmlsdhq_s32): Remove.
(__arm_vqrdmladhxq_s32): Remove.
(__arm_vqrdmladhq_s32): Remove.
(__arm_vqdmlsdhxq_s32): Remove.
(__arm_vqdmlsdhq_s32): Remove.
(__arm_vqdmladhxq_s32): Remove.
(__arm_vqdmladhq_s32): Remove.
(__arm_vqdmladhq_m_s8): Remove.
(__arm_vqdmladhq_m_s32): Remove.
(__arm_vqdmladhq_m_s16): Remove.
(__arm_vqdmladhxq_m_s8): Remove.
(__arm_vqdmladhxq_m_s32): Remove.
(__arm_vqdmladhxq_m_s16): Remove.
(__arm_vqdmlsdhq_m_s8): Remove.
(__arm_vqdmlsdhq_m_s32): Remove.
(__arm_vqdmlsdhq_m_s16): Remove.
(__arm_vqdmlsdhxq_m_s8): Remove.
(__arm_vqdmlsdhxq_m_s32): Remove.
(__arm_vqdmlsdhxq_m_s16): Remove.
(__arm_vqrdmladhq_m_s8): Remove.
(__arm_vqrdmladhq_m_s32): Remove.
(__arm_vqrdmladhq_m_s16): Remove.
(__arm_vqrdmladhxq_m_s8): Remove.
(__arm_vqrdmladhxq_m_s32): Remove.
(__arm_vqrdmladhxq_m_s16): Remove.
(__arm_vqrdmlsdhq_m_s8): Remove.
(__arm_vqrdmlsdhq_m_s32): Remove.
(__arm_vqrdmlsdhq_m_s16): Remove.
(__arm_vqrdmlsdhxq_m_s8): Remove.
(__arm_vqrdmlsdhxq_m_s32): Remove.
(__arm_vqrdmlsdhxq_m_s16): Remove.
(__arm_vqrdmlsdhxq): Remove.
(__arm_vqrdmlsdhq): Remove.
(__arm_vqrdmladhxq): Remove.
(__arm_vqrdmladhq): Remove.
(__arm_vqdmlsdhxq): Remove.
(__arm_vqdmlsdhq): Remove.
(__arm_vqdmladhxq): Remove.
(__arm_vqdmladhq): Remove.
(__arm_vqdmladhq_m): Remove.
(__arm_vqdmladhxq_m): Remove.
(__arm_vqdmlsdhq_m): Remove.
(__arm_vqdmlsdhxq_m): Remove.
(__arm_vqrdmladhq_m): Remove.
(__arm_vqrdmladhxq_m): Remove.
(__arm_vqrdmlsdhq_m): Remove.
(__arm_vqrdmlsdhxq_m): Remove.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (MVE_VQxDMLxDHxQ_S): New.
(mve_insn): Add vqdmladh, vqdmladhx, vqdmlsdh, vqdmlsdhx,
vqrdmladh, vqrdmladhx, vqrdmlsdh, vqrdmlsdhx.
(supf): Add VQDMLADHQ_S, VQDMLADHXQ_S, VQDMLSDHQ_S, VQDMLSDHXQ_S,
VQRDMLADHQ_S,VQRDMLADHXQ_S, VQRDMLSDHQ_S, VQRDMLSDHXQ_S.
* config/arm/mve.md (mve_vqrdmladhq_s<mode>)
(mve_vqrdmladhxq_s<mode>, mve_vqrdmlsdhq_s<mode>)
(mve_vqrdmlsdhxq_s<mode>, mve_vqdmlsdhxq_s<mode>)
(mve_vqdmlsdhq_s<mode>, mve_vqdmladhxq_s<mode>)
(mve_vqdmladhq_s<mode>): Merge into ...
(@mve_<mve_insn>q_<supf><mode>): ... this.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-shapes.cc (ternary): New.
* config/arm/arm-mve-builtins-shapes.h (ternary): New.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (vmlaldavaq, vmlaldavaxq)
(vmlsldavaq, vmlsldavaxq): New.
* config/arm/arm-mve-builtins-base.def (vmlaldavaq, vmlaldavaxq)
(vmlsldavaq, vmlsldavaxq): New.
* config/arm/arm-mve-builtins-base.h (vmlaldavaq, vmlaldavaxq)
(vmlsldavaq, vmlsldavaxq): New.
* config/arm/arm_mve.h (vmlaldavaq): Remove.
(vmlaldavaxq): Remove.
(vmlsldavaq): Remove.
(vmlsldavaxq): Remove.
(vmlaldavaq_p): Remove.
(vmlaldavaxq_p): Remove.
(vmlsldavaq_p): Remove.
(vmlsldavaxq_p): Remove.
(vmlaldavaq_s16): Remove.
(vmlaldavaxq_s16): Remove.
(vmlsldavaq_s16): Remove.
(vmlsldavaxq_s16): Remove.
(vmlaldavaq_u16): Remove.
(vmlaldavaq_s32): Remove.
(vmlaldavaxq_s32): Remove.
(vmlsldavaq_s32): Remove.
(vmlsldavaxq_s32): Remove.
(vmlaldavaq_u32): Remove.
(vmlaldavaq_p_s32): Remove.
(vmlaldavaq_p_s16): Remove.
(vmlaldavaq_p_u32): Remove.
(vmlaldavaq_p_u16): Remove.
(vmlaldavaxq_p_s32): Remove.
(vmlaldavaxq_p_s16): Remove.
(vmlsldavaq_p_s32): Remove.
(vmlsldavaq_p_s16): Remove.
(vmlsldavaxq_p_s32): Remove.
(vmlsldavaxq_p_s16): Remove.
(__arm_vmlaldavaq_s16): Remove.
(__arm_vmlaldavaxq_s16): Remove.
(__arm_vmlsldavaq_s16): Remove.
(__arm_vmlsldavaxq_s16): Remove.
(__arm_vmlaldavaq_u16): Remove.
(__arm_vmlaldavaq_s32): Remove.
(__arm_vmlaldavaxq_s32): Remove.
(__arm_vmlsldavaq_s32): Remove.
(__arm_vmlsldavaxq_s32): Remove.
(__arm_vmlaldavaq_u32): Remove.
(__arm_vmlaldavaq_p_s32): Remove.
(__arm_vmlaldavaq_p_s16): Remove.
(__arm_vmlaldavaq_p_u32): Remove.
(__arm_vmlaldavaq_p_u16): Remove.
(__arm_vmlaldavaxq_p_s32): Remove.
(__arm_vmlaldavaxq_p_s16): Remove.
(__arm_vmlsldavaq_p_s32): Remove.
(__arm_vmlsldavaq_p_s16): Remove.
(__arm_vmlsldavaxq_p_s32): Remove.
(__arm_vmlsldavaxq_p_s16): Remove.
(__arm_vmlaldavaq): Remove.
(__arm_vmlaldavaxq): Remove.
(__arm_vmlsldavaq): Remove.
(__arm_vmlsldavaxq): Remove.
(__arm_vmlaldavaq_p): Remove.
(__arm_vmlaldavaxq_p): Remove.
(__arm_vmlsldavaq_p): Remove.
(__arm_vmlsldavaxq_p): Remove.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (MVE_VMLxLDAVAxQ, MVE_VMLxLDAVAxQ_P):
New.
(mve_insn): Add vmlaldava, vmlaldavax, vmlsldava, vmlsldavax.
(supf): Add VMLALDAVAXQ_P_S, VMLALDAVAXQ_S, VMLSLDAVAQ_P_S,
VMLSLDAVAQ_S, VMLSLDAVAXQ_P_S, VMLSLDAVAXQ_S.
* config/arm/mve.md (mve_vmlaldavaq_<supf><mode>)
(mve_vmlsldavaq_s<mode>, mve_vmlsldavaxq_s<mode>)
(mve_vmlaldavaxq_s<mode>): Merge into ...
(@mve_<mve_insn>q_<supf><mode>): ... this.
(mve_vmlaldavaq_p_<supf><mode>, mve_vmlaldavaxq_p_<supf><mode>)
(mve_vmlsldavaq_p_s<mode>, mve_vmlsldavaxq_p_s<mode>): Merge into
...
(@mve_<mve_insn>q_p_<supf><mode>): ... this.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-shapes.cc (binary_acca_int64): New.
* config/arm/arm-mve-builtins-shapes.h (binary_acca_int64): New.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (vrmlaldavhq, vrmlaldavhxq)
(vrmlsldavhq, vrmlsldavhxq): New.
* config/arm/arm-mve-builtins-base.def (vrmlaldavhq, vrmlaldavhxq)
(vrmlsldavhq, vrmlsldavhxq): New.
* config/arm/arm-mve-builtins-base.h (vrmlaldavhq, vrmlaldavhxq)
(vrmlsldavhq, vrmlsldavhxq): New.
* config/arm/arm-mve-builtins-functions.h
(unspec_mve_function_exact_insn_pred_p): Handle vrmlaldavhq,
vrmlaldavhxq, vrmlsldavhq, vrmlsldavhxq.
* config/arm/arm_mve.h (vrmlaldavhq): Remove.
(vrmlsldavhxq): Remove.
(vrmlsldavhq): Remove.
(vrmlaldavhxq): Remove.
(vrmlaldavhq_p): Remove.
(vrmlaldavhxq_p): Remove.
(vrmlsldavhq_p): Remove.
(vrmlsldavhxq_p): Remove.
(vrmlaldavhq_u32): Remove.
(vrmlsldavhxq_s32): Remove.
(vrmlsldavhq_s32): Remove.
(vrmlaldavhxq_s32): Remove.
(vrmlaldavhq_s32): Remove.
(vrmlaldavhq_p_s32): Remove.
(vrmlaldavhxq_p_s32): Remove.
(vrmlsldavhq_p_s32): Remove.
(vrmlsldavhxq_p_s32): Remove.
(vrmlaldavhq_p_u32): Remove.
(__arm_vrmlaldavhq_u32): Remove.
(__arm_vrmlsldavhxq_s32): Remove.
(__arm_vrmlsldavhq_s32): Remove.
(__arm_vrmlaldavhxq_s32): Remove.
(__arm_vrmlaldavhq_s32): Remove.
(__arm_vrmlaldavhq_p_s32): Remove.
(__arm_vrmlaldavhxq_p_s32): Remove.
(__arm_vrmlsldavhq_p_s32): Remove.
(__arm_vrmlsldavhxq_p_s32): Remove.
(__arm_vrmlaldavhq_p_u32): Remove.
(__arm_vrmlaldavhq): Remove.
(__arm_vrmlsldavhxq): Remove.
(__arm_vrmlsldavhq): Remove.
(__arm_vrmlaldavhxq): Remove.
(__arm_vrmlaldavhq_p): Remove.
(__arm_vrmlaldavhxq_p): Remove.
(__arm_vrmlsldavhq_p): Remove.
(__arm_vrmlsldavhxq_p): Remove.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (MVE_VRMLxLDAVxQ, MVE_VRMLxLDAVHxQ_P):
New.
(mve_insn): Add vrmlaldavh, vrmlaldavhx, vrmlsldavh, vrmlsldavhx.
(supf): Add VRMLALDAVHXQ_P_S, VRMLALDAVHXQ_S, VRMLSLDAVHQ_P_S,
VRMLSLDAVHQ_S, VRMLSLDAVHXQ_P_S, VRMLSLDAVHXQ_S.
* config/arm/mve.md (mve_vrmlaldavhxq_sv4si)
(mve_vrmlsldavhq_sv4si, mve_vrmlsldavhxq_sv4si)
(mve_vrmlaldavhq_<supf>v4si): Merge into ...
(@mve_<mve_insn>q_<supf>v4si): ... this.
(mve_vrmlaldavhxq_p_sv4si, mve_vrmlsldavhq_p_sv4si)
(mve_vrmlsldavhxq_p_sv4si, mve_vrmlaldavhq_p_<supf>v4si): Merge
into ...
(@mve_<mve_insn>q_p_<supf>v4si): ... this.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (vmlaldavq, vmlaldavxq)
(vmlsldavq, vmlsldavxq): New.
* config/arm/arm-mve-builtins-base.def (vmlaldavq, vmlaldavxq)
(vmlsldavq, vmlsldavxq): New.
* config/arm/arm-mve-builtins-base.h (vmlaldavq, vmlaldavxq)
(vmlsldavq, vmlsldavxq): New.
* config/arm/arm_mve.h (vmlaldavq): Remove.
(vmlsldavxq): Remove.
(vmlsldavq): Remove.
(vmlaldavxq): Remove.
(vmlaldavq_p): Remove.
(vmlaldavxq_p): Remove.
(vmlsldavq_p): Remove.
(vmlsldavxq_p): Remove.
(vmlaldavq_u16): Remove.
(vmlsldavxq_s16): Remove.
(vmlsldavq_s16): Remove.
(vmlaldavxq_s16): Remove.
(vmlaldavq_s16): Remove.
(vmlaldavq_u32): Remove.
(vmlsldavxq_s32): Remove.
(vmlsldavq_s32): Remove.
(vmlaldavxq_s32): Remove.
(vmlaldavq_s32): Remove.
(vmlaldavq_p_s16): Remove.
(vmlaldavxq_p_s16): Remove.
(vmlsldavq_p_s16): Remove.
(vmlsldavxq_p_s16): Remove.
(vmlaldavq_p_u16): Remove.
(vmlaldavq_p_s32): Remove.
(vmlaldavxq_p_s32): Remove.
(vmlsldavq_p_s32): Remove.
(vmlsldavxq_p_s32): Remove.
(vmlaldavq_p_u32): Remove.
(__arm_vmlaldavq_u16): Remove.
(__arm_vmlsldavxq_s16): Remove.
(__arm_vmlsldavq_s16): Remove.
(__arm_vmlaldavxq_s16): Remove.
(__arm_vmlaldavq_s16): Remove.
(__arm_vmlaldavq_u32): Remove.
(__arm_vmlsldavxq_s32): Remove.
(__arm_vmlsldavq_s32): Remove.
(__arm_vmlaldavxq_s32): Remove.
(__arm_vmlaldavq_s32): Remove.
(__arm_vmlaldavq_p_s16): Remove.
(__arm_vmlaldavxq_p_s16): Remove.
(__arm_vmlsldavq_p_s16): Remove.
(__arm_vmlsldavxq_p_s16): Remove.
(__arm_vmlaldavq_p_u16): Remove.
(__arm_vmlaldavq_p_s32): Remove.
(__arm_vmlaldavxq_p_s32): Remove.
(__arm_vmlsldavq_p_s32): Remove.
(__arm_vmlsldavxq_p_s32): Remove.
(__arm_vmlaldavq_p_u32): Remove.
(__arm_vmlaldavq): Remove.
(__arm_vmlsldavxq): Remove.
(__arm_vmlsldavq): Remove.
(__arm_vmlaldavxq): Remove.
(__arm_vmlaldavq_p): Remove.
(__arm_vmlaldavxq_p): Remove.
(__arm_vmlsldavq_p): Remove.
(__arm_vmlsldavxq_p): Remove.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (MVE_VMLxLDAVxQ, MVE_VMLxLDAVxQ_P): New.
(mve_insn): Add vmlaldav, vmlaldavx, vmlsldav, vmlsldavx.
(supf): Add VMLALDAVXQ_S, VMLSLDAVQ_S, VMLSLDAVXQ_S,
VMLALDAVXQ_P_S, VMLSLDAVQ_P_S, VMLSLDAVXQ_P_S.
* config/arm/mve.md (mve_vmlaldavq_<supf><mode>)
(mve_vmlaldavxq_s<mode>, mve_vmlsldavq_s<mode>)
(mve_vmlsldavxq_s<mode>): Merge into ...
(@mve_<mve_insn>q_<supf><mode>): ... this.
(mve_vmlaldavq_p_<supf><mode>, mve_vmlaldavxq_p_s<mode>)
(mve_vmlsldavq_p_s<mode>, mve_vmlsldavxq_p_s<mode>): Merge into
...
(@mve_<mve_insn>q_p_<supf><mode>): ... this.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-shapes.cc (binary_acc_int64): New.
* config/arm/arm-mve-builtins-shapes.h (binary_acc_int64): New.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (vabavq): New.
* config/arm/arm-mve-builtins-base.def (vabavq): New.
* config/arm/arm-mve-builtins-base.h (vabavq): New.
* config/arm/arm_mve.h (vabavq): Remove.
(vabavq_p): Remove.
(vabavq_s8): Remove.
(vabavq_s16): Remove.
(vabavq_s32): Remove.
(vabavq_u8): Remove.
(vabavq_u16): Remove.
(vabavq_u32): Remove.
(vabavq_p_s8): Remove.
(vabavq_p_u8): Remove.
(vabavq_p_s16): Remove.
(vabavq_p_u16): Remove.
(vabavq_p_s32): Remove.
(vabavq_p_u32): Remove.
(__arm_vabavq_s8): Remove.
(__arm_vabavq_s16): Remove.
(__arm_vabavq_s32): Remove.
(__arm_vabavq_u8): Remove.
(__arm_vabavq_u16): Remove.
(__arm_vabavq_u32): Remove.
(__arm_vabavq_p_s8): Remove.
(__arm_vabavq_p_u8): Remove.
(__arm_vabavq_p_s16): Remove.
(__arm_vabavq_p_u16): Remove.
(__arm_vabavq_p_s32): Remove.
(__arm_vabavq_p_u32): Remove.
(__arm_vabavq): Remove.
(__arm_vabavq_p): Remove.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (mve_insn): Add vabav.
* config/arm/mve.md (mve_vabavq_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_<supf><mode>): ... this,.
(mve_vabavq_p_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_p_<supf><mode>): ... this,.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (vmladavaxq, vmladavaq)
(vmlsdavaq, vmlsdavaxq): New.
* config/arm/arm-mve-builtins-base.def (vmladavaxq, vmladavaq)
(vmlsdavaq, vmlsdavaxq): New.
* config/arm/arm-mve-builtins-base.h (vmladavaxq, vmladavaq)
(vmlsdavaq, vmlsdavaxq): New.
* config/arm/arm_mve.h (vmladavaq): Remove.
(vmlsdavaxq): Remove.
(vmlsdavaq): Remove.
(vmladavaxq): Remove.
(vmladavaq_p): Remove.
(vmladavaxq_p): Remove.
(vmlsdavaq_p): Remove.
(vmlsdavaxq_p): Remove.
(vmladavaq_u8): Remove.
(vmlsdavaxq_s8): Remove.
(vmlsdavaq_s8): Remove.
(vmladavaxq_s8): Remove.
(vmladavaq_s8): Remove.
(vmladavaq_u16): Remove.
(vmlsdavaxq_s16): Remove.
(vmlsdavaq_s16): Remove.
(vmladavaxq_s16): Remove.
(vmladavaq_s16): Remove.
(vmladavaq_u32): Remove.
(vmlsdavaxq_s32): Remove.
(vmlsdavaq_s32): Remove.
(vmladavaxq_s32): Remove.
(vmladavaq_s32): Remove.
(vmladavaq_p_s8): Remove.
(vmladavaq_p_s32): Remove.
(vmladavaq_p_s16): Remove.
(vmladavaq_p_u8): Remove.
(vmladavaq_p_u32): Remove.
(vmladavaq_p_u16): Remove.
(vmladavaxq_p_s8): Remove.
(vmladavaxq_p_s32): Remove.
(vmladavaxq_p_s16): Remove.
(vmlsdavaq_p_s8): Remove.
(vmlsdavaq_p_s32): Remove.
(vmlsdavaq_p_s16): Remove.
(vmlsdavaxq_p_s8): Remove.
(vmlsdavaxq_p_s32): Remove.
(vmlsdavaxq_p_s16): Remove.
(__arm_vmladavaq_u8): Remove.
(__arm_vmlsdavaxq_s8): Remove.
(__arm_vmlsdavaq_s8): Remove.
(__arm_vmladavaxq_s8): Remove.
(__arm_vmladavaq_s8): Remove.
(__arm_vmladavaq_u16): Remove.
(__arm_vmlsdavaxq_s16): Remove.
(__arm_vmlsdavaq_s16): Remove.
(__arm_vmladavaxq_s16): Remove.
(__arm_vmladavaq_s16): Remove.
(__arm_vmladavaq_u32): Remove.
(__arm_vmlsdavaxq_s32): Remove.
(__arm_vmlsdavaq_s32): Remove.
(__arm_vmladavaxq_s32): Remove.
(__arm_vmladavaq_s32): Remove.
(__arm_vmladavaq_p_s8): Remove.
(__arm_vmladavaq_p_s32): Remove.
(__arm_vmladavaq_p_s16): Remove.
(__arm_vmladavaq_p_u8): Remove.
(__arm_vmladavaq_p_u32): Remove.
(__arm_vmladavaq_p_u16): Remove.
(__arm_vmladavaxq_p_s8): Remove.
(__arm_vmladavaxq_p_s32): Remove.
(__arm_vmladavaxq_p_s16): Remove.
(__arm_vmlsdavaq_p_s8): Remove.
(__arm_vmlsdavaq_p_s32): Remove.
(__arm_vmlsdavaq_p_s16): Remove.
(__arm_vmlsdavaxq_p_s8): Remove.
(__arm_vmlsdavaxq_p_s32): Remove.
(__arm_vmlsdavaxq_p_s16): Remove.
(__arm_vmladavaq): Remove.
(__arm_vmlsdavaxq): Remove.
(__arm_vmlsdavaq): Remove.
(__arm_vmladavaxq): Remove.
(__arm_vmladavaq_p): Remove.
(__arm_vmladavaxq_p): Remove.
(__arm_vmlsdavaq_p): Remove.
(__arm_vmlsdavaxq_p): Remove.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-shapes.cc (binary_acca_int32): New.
* config/arm/arm-mve-builtins-shapes.h (binary_acca_int32): New.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (vmladavq, vmladavxq)
(vmlsdavq, vmlsdavxq): New.
* config/arm/arm-mve-builtins-base.def (vmladavq, vmladavxq)
(vmlsdavq, vmlsdavxq): New.
* config/arm/arm-mve-builtins-base.h (vmladavq, vmladavxq)
(vmlsdavq, vmlsdavxq): New.
* config/arm/arm_mve.h (vmladavq): Remove.
(vmlsdavxq): Remove.
(vmlsdavq): Remove.
(vmladavxq): Remove.
(vmladavq_p): Remove.
(vmlsdavxq_p): Remove.
(vmlsdavq_p): Remove.
(vmladavxq_p): Remove.
(vmladavq_u8): Remove.
(vmlsdavxq_s8): Remove.
(vmlsdavq_s8): Remove.
(vmladavxq_s8): Remove.
(vmladavq_s8): Remove.
(vmladavq_u16): Remove.
(vmlsdavxq_s16): Remove.
(vmlsdavq_s16): Remove.
(vmladavxq_s16): Remove.
(vmladavq_s16): Remove.
(vmladavq_u32): Remove.
(vmlsdavxq_s32): Remove.
(vmlsdavq_s32): Remove.
(vmladavxq_s32): Remove.
(vmladavq_s32): Remove.
(vmladavq_p_u8): Remove.
(vmlsdavxq_p_s8): Remove.
(vmlsdavq_p_s8): Remove.
(vmladavxq_p_s8): Remove.
(vmladavq_p_s8): Remove.
(vmladavq_p_u16): Remove.
(vmlsdavxq_p_s16): Remove.
(vmlsdavq_p_s16): Remove.
(vmladavxq_p_s16): Remove.
(vmladavq_p_s16): Remove.
(vmladavq_p_u32): Remove.
(vmlsdavxq_p_s32): Remove.
(vmlsdavq_p_s32): Remove.
(vmladavxq_p_s32): Remove.
(vmladavq_p_s32): Remove.
(__arm_vmladavq_u8): Remove.
(__arm_vmlsdavxq_s8): Remove.
(__arm_vmlsdavq_s8): Remove.
(__arm_vmladavxq_s8): Remove.
(__arm_vmladavq_s8): Remove.
(__arm_vmladavq_u16): Remove.
(__arm_vmlsdavxq_s16): Remove.
(__arm_vmlsdavq_s16): Remove.
(__arm_vmladavxq_s16): Remove.
(__arm_vmladavq_s16): Remove.
(__arm_vmladavq_u32): Remove.
(__arm_vmlsdavxq_s32): Remove.
(__arm_vmlsdavq_s32): Remove.
(__arm_vmladavxq_s32): Remove.
(__arm_vmladavq_s32): Remove.
(__arm_vmladavq_p_u8): Remove.
(__arm_vmlsdavxq_p_s8): Remove.
(__arm_vmlsdavq_p_s8): Remove.
(__arm_vmladavxq_p_s8): Remove.
(__arm_vmladavq_p_s8): Remove.
(__arm_vmladavq_p_u16): Remove.
(__arm_vmlsdavxq_p_s16): Remove.
(__arm_vmlsdavq_p_s16): Remove.
(__arm_vmladavxq_p_s16): Remove.
(__arm_vmladavq_p_s16): Remove.
(__arm_vmladavq_p_u32): Remove.
(__arm_vmlsdavxq_p_s32): Remove.
(__arm_vmlsdavq_p_s32): Remove.
(__arm_vmladavxq_p_s32): Remove.
(__arm_vmladavq_p_s32): Remove.
(__arm_vmladavq): Remove.
(__arm_vmlsdavxq): Remove.
(__arm_vmlsdavq): Remove.
(__arm_vmladavxq): Remove.
(__arm_vmladavq_p): Remove.
(__arm_vmlsdavxq_p): Remove.
(__arm_vmlsdavq_p): Remove.
(__arm_vmladavxq_p): Remove.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (MVE_VMLxDAVQ, MVE_VMLxDAVQ_P)
(MVE_VMLxDAVAQ, MVE_VMLxDAVAQ_P): New.
(mve_insn): Add vmladava, vmladavax, vmladav, vmladavx, vmlsdava,
vmlsdavax, vmlsdav, vmlsdavx.
(supf): Add VMLADAVAXQ_P_S, VMLADAVAXQ_S, VMLADAVXQ_P_S,
VMLADAVXQ_S, VMLSDAVAQ_P_S, VMLSDAVAQ_S, VMLSDAVAXQ_P_S,
VMLSDAVAXQ_S, VMLSDAVQ_P_S, VMLSDAVQ_S, VMLSDAVXQ_P_S,
VMLSDAVXQ_S.
* config/arm/mve.md (mve_vmladavq_<supf><mode>)
(mve_vmladavxq_s<mode>, mve_vmlsdavq_s<mode>)
(mve_vmlsdavxq_s<mode>): Merge into ...
(@mve_<mve_insn>q_<supf><mode>): ... this.
(mve_vmlsdavaq_s<mode>, mve_vmladavaxq_s<mode>)
(mve_vmlsdavaxq_s<mode>, mve_vmladavaq_<supf><mode>): Merge into
...
(@mve_<mve_insn>q_<supf><mode>): ... this.
(mve_vmladavq_p_<supf><mode>, mve_vmladavxq_p_s<mode>)
(mve_vmlsdavq_p_s<mode>, mve_vmlsdavxq_p_s<mode>): Merge into ...
(@mve_<mve_insn>q_p_<supf><mode>): ... this.
(mve_vmladavaq_p_<supf><mode>, mve_vmladavaxq_p_s<mode>)
(mve_vmlsdavaq_p_s<mode>, mve_vmlsdavaxq_p_s<mode>): Merge into
...
(@mve_<mve_insn>q_p_<supf><mode>): ... this.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-shapes.cc (binary_acc_int32): New.
* config/arm/arm-mve-builtins-shapes.h (binary_acc_int32): New.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (vaddlvaq): New.
* config/arm/arm-mve-builtins-base.def (vaddlvaq): New.
* config/arm/arm-mve-builtins-base.h (vaddlvaq): New.
* config/arm/arm_mve.h (vaddlvaq): Remove.
(vaddlvaq_p): Remove.
(vaddlvaq_u32): Remove.
(vaddlvaq_s32): Remove.
(vaddlvaq_p_s32): Remove.
(vaddlvaq_p_u32): Remove.
(__arm_vaddlvaq_u32): Remove.
(__arm_vaddlvaq_s32): Remove.
(__arm_vaddlvaq_p_s32): Remove.
(__arm_vaddlvaq_p_u32): Remove.
(__arm_vaddlvaq): Remove.
(__arm_vaddlvaq_p): Remove.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-shapes.cc (unary_widen_acc): New.
* config/arm/arm-mve-builtins-shapes.h (unary_widen_acc): New.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (mve_insn): Add vaddlva.
* config/arm/mve.md (mve_vaddlvaq_<supf>v4si): Rename into ...
(@mve_<mve_insn>q_<supf>v4si): ... this.
(mve_vaddlvaq_p_<supf>v4si): Rename into ...
(@mve_<mve_insn>q_p_<supf>v4si): ... this.
2023-05-11 Uros Bizjak <ubizjak@gmail.com>
PR target/109807
* config/i386/i386.cc (ix86_widen_mult_cost):
Handle V4HImode and V2SImode.
2023-05-11 Andrew Pinski <apinski@marvell.com>
* tree-ssa-dce.cc (simple_dce_from_worklist): For ssa names
defined by a phi node with more than one uses, allow for the
only uses are in that same defining statement.
2023-05-11 Robin Dapp <rdapp@ventanamicro.com>
* config/riscv/riscv.cc (riscv_const_insns): Add permissible
vector constants.
2023-05-11 Pan Li <pan2.li@intel.com>
* config/riscv/vector.md: Add comments for simplifying to vmset.
2023-05-11 Robin Dapp <rdapp@ventanamicro.com>
* config/riscv/autovec.md (<optab><mode>3): Add scalar shift
pattern.
(v<optab><mode>3): Add vector shift pattern.
* config/riscv/vector-iterators.md: New iterator.
2023-05-11 Robin Dapp <rdapp@ventanamicro.com>
* config/riscv/autovec.md: Use renamed functions.
* config/riscv/riscv-protos.h (emit_vlmax_op): Rename.
(emit_vlmax_reg_op): To this.
(emit_nonvlmax_op): Rename.
(emit_len_op): To this.
(emit_nonvlmax_binop): Rename.
(emit_len_binop): To this.
* config/riscv/riscv-v.cc (emit_pred_op): Add default parameter.
(emit_pred_binop): Remove vlmax_p.
(emit_vlmax_op): Rename.
(emit_vlmax_reg_op): To this.
(emit_nonvlmax_op): Rename.
(emit_len_op): To this.
(emit_nonvlmax_binop): Rename.
(emit_len_binop): To this.
(sew64_scalar_helper): Use renamed functions.
(expand_tuple_move): Use renamed functions.
* config/riscv/riscv.cc (vector_zero_call_used_regs): Use
renamed functions.
* config/riscv/vector.md: Use renamed functions.
2023-05-11 Robin Dapp <rdapp@ventanamicro.com>
Michael Collison <collison@rivosinc.com>
* config/riscv/autovec.md (<optab><mode>3): Add integer binops.
* config/riscv/riscv-protos.h (emit_nonvlmax_binop): Declare.
* config/riscv/riscv-v.cc (emit_pred_op): New function.
(set_expander_dest_and_mask): New function.
(emit_pred_binop): New function.
(emit_nonvlmax_binop): New function.
2023-05-11 Pan Li <pan2.li@intel.com>
* cfgloopmanip.cc (create_empty_loop_on_edge): Add PLUS_EXPR.
* gimple-loop-interchange.cc
(tree_loop_interchange::map_inductions_to_loop): Ditto.
* tree-ssa-loop-ivcanon.cc (create_canonical_iv): Ditto.
* tree-ssa-loop-ivopts.cc (create_new_iv): Ditto.
* tree-ssa-loop-manip.cc (create_iv): Ditto.
(tree_transform_and_unroll_loop): Ditto.
(canonicalize_loop_ivs): Ditto.
* tree-ssa-loop-manip.h (create_iv): Ditto.
* tree-vect-data-refs.cc (vect_create_data_ref_ptr): Ditto.
* tree-vect-loop-manip.cc (vect_set_loop_controls_directly):
Ditto.
(vect_set_loop_condition_normal): Ditto.
* tree-vect-loop.cc (vect_create_epilog_for_reduction): Ditto.
* tree-vect-stmts.cc (vectorizable_store): Ditto.
(vectorizable_load): Ditto.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (vmovlbq, vmovltq): New.
* config/arm/arm-mve-builtins-base.def (vmovlbq, vmovltq): New.
* config/arm/arm-mve-builtins-base.h (vmovlbq, vmovltq): New.
* config/arm/arm_mve.h (vmovlbq): Remove.
(vmovltq): Remove.
(vmovlbq_m): Remove.
(vmovltq_m): Remove.
(vmovlbq_x): Remove.
(vmovltq_x): Remove.
(vmovlbq_s8): Remove.
(vmovlbq_s16): Remove.
(vmovltq_s8): Remove.
(vmovltq_s16): Remove.
(vmovltq_u8): Remove.
(vmovltq_u16): Remove.
(vmovlbq_u8): Remove.
(vmovlbq_u16): Remove.
(vmovlbq_m_s8): Remove.
(vmovltq_m_s8): Remove.
(vmovlbq_m_u8): Remove.
(vmovltq_m_u8): Remove.
(vmovlbq_m_s16): Remove.
(vmovltq_m_s16): Remove.
(vmovlbq_m_u16): Remove.
(vmovltq_m_u16): Remove.
(vmovlbq_x_s8): Remove.
(vmovlbq_x_s16): Remove.
(vmovlbq_x_u8): Remove.
(vmovlbq_x_u16): Remove.
(vmovltq_x_s8): Remove.
(vmovltq_x_s16): Remove.
(vmovltq_x_u8): Remove.
(vmovltq_x_u16): Remove.
(__arm_vmovlbq_s8): Remove.
(__arm_vmovlbq_s16): Remove.
(__arm_vmovltq_s8): Remove.
(__arm_vmovltq_s16): Remove.
(__arm_vmovltq_u8): Remove.
(__arm_vmovltq_u16): Remove.
(__arm_vmovlbq_u8): Remove.
(__arm_vmovlbq_u16): Remove.
(__arm_vmovlbq_m_s8): Remove.
(__arm_vmovltq_m_s8): Remove.
(__arm_vmovlbq_m_u8): Remove.
(__arm_vmovltq_m_u8): Remove.
(__arm_vmovlbq_m_s16): Remove.
(__arm_vmovltq_m_s16): Remove.
(__arm_vmovlbq_m_u16): Remove.
(__arm_vmovltq_m_u16): Remove.
(__arm_vmovlbq_x_s8): Remove.
(__arm_vmovlbq_x_s16): Remove.
(__arm_vmovlbq_x_u8): Remove.
(__arm_vmovlbq_x_u16): Remove.
(__arm_vmovltq_x_s8): Remove.
(__arm_vmovltq_x_s16): Remove.
(__arm_vmovltq_x_u8): Remove.
(__arm_vmovltq_x_u16): Remove.
(__arm_vmovlbq): Remove.
(__arm_vmovltq): Remove.
(__arm_vmovlbq_m): Remove.
(__arm_vmovltq_m): Remove.
(__arm_vmovlbq_x): Remove.
(__arm_vmovltq_x): Remove.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-shapes.cc (unary_widen): New.
* config/arm/arm-mve-builtins-shapes.h (unary_widen): New.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (mve_insn): Add vmovlb, vmovlt.
(VMOVLBQ, VMOVLTQ): Merge into ...
(VMOVLxQ): ... this.
(VMOVLTQ_M, VMOVLBQ_M): Merge into ...
(VMOVLxQ_M): ... this.
* config/arm/mve.md (mve_vmovltq_<supf><mode>)
(mve_vmovlbq_<supf><mode>): Merge into ...
(@mve_<mve_insn>q_<supf><mode>): ... this.
(mve_vmovlbq_m_<supf><mode>, mve_vmovltq_m_<supf><mode>): Merge
into ...
(@mve_<mve_insn>q_m_<supf><mode>): ... this.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (vaddlvq): New.
* config/arm/arm-mve-builtins-base.def (vaddlvq): New.
* config/arm/arm-mve-builtins-base.h (vaddlvq): New.
* config/arm/arm-mve-builtins-functions.h
(unspec_mve_function_exact_insn_pred_p): Handle vaddlvq.
* config/arm/arm_mve.h (vaddlvq): Remove.
(vaddlvq_p): Remove.
(vaddlvq_s32): Remove.
(vaddlvq_u32): Remove.
(vaddlvq_p_s32): Remove.
(vaddlvq_p_u32): Remove.
(__arm_vaddlvq_s32): Remove.
(__arm_vaddlvq_u32): Remove.
(__arm_vaddlvq_p_s32): Remove.
(__arm_vaddlvq_p_u32): Remove.
(__arm_vaddlvq): Remove.
(__arm_vaddlvq_p): Remove.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (mve_insn): Add vaddlv.
* config/arm/mve.md (mve_vaddlvq_<supf>v4si): Rename into ...
(@mve_<mve_insn>q_<supf>v4si): ... this.
(mve_vaddlvq_p_<supf>v4si): Rename into ...
(@mve_<mve_insn>q_p_<supf>v4si): ... this.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-shapes.cc (unary_acc): New.
* config/arm/arm-mve-builtins-shapes.h (unary_acc): New.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (vaddvaq): New.
* config/arm/arm-mve-builtins-base.def (vaddvaq): New.
* config/arm/arm-mve-builtins-base.h (vaddvaq): New.
* config/arm/arm_mve.h (vaddvaq): Remove.
(vaddvaq_p): Remove.
(vaddvaq_u8): Remove.
(vaddvaq_s8): Remove.
(vaddvaq_u16): Remove.
(vaddvaq_s16): Remove.
(vaddvaq_u32): Remove.
(vaddvaq_s32): Remove.
(vaddvaq_p_u8): Remove.
(vaddvaq_p_s8): Remove.
(vaddvaq_p_u16): Remove.
(vaddvaq_p_s16): Remove.
(vaddvaq_p_u32): Remove.
(vaddvaq_p_s32): Remove.
(__arm_vaddvaq_u8): Remove.
(__arm_vaddvaq_s8): Remove.
(__arm_vaddvaq_u16): Remove.
(__arm_vaddvaq_s16): Remove.
(__arm_vaddvaq_u32): Remove.
(__arm_vaddvaq_s32): Remove.
(__arm_vaddvaq_p_u8): Remove.
(__arm_vaddvaq_p_s8): Remove.
(__arm_vaddvaq_p_u16): Remove.
(__arm_vaddvaq_p_s16): Remove.
(__arm_vaddvaq_p_u32): Remove.
(__arm_vaddvaq_p_s32): Remove.
(__arm_vaddvaq): Remove.
(__arm_vaddvaq_p): Remove.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-shapes.cc (unary_int32_acc): New.
* config/arm/arm-mve-builtins-shapes.h (unary_int32_acc): New.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (mve_insn): Add vaddva.
* config/arm/mve.md (mve_vaddvaq_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_<supf><mode>): ... this.
(mve_vaddvaq_p_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_p_<supf><mode>): ... this.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (vaddvq): New.
* config/arm/arm-mve-builtins-base.def (vaddvq): New.
* config/arm/arm-mve-builtins-base.h (vaddvq): New.
* config/arm/arm_mve.h (vaddvq): Remove.
(vaddvq_p): Remove.
(vaddvq_s8): Remove.
(vaddvq_s16): Remove.
(vaddvq_s32): Remove.
(vaddvq_u8): Remove.
(vaddvq_u16): Remove.
(vaddvq_u32): Remove.
(vaddvq_p_u8): Remove.
(vaddvq_p_s8): Remove.
(vaddvq_p_u16): Remove.
(vaddvq_p_s16): Remove.
(vaddvq_p_u32): Remove.
(vaddvq_p_s32): Remove.
(__arm_vaddvq_s8): Remove.
(__arm_vaddvq_s16): Remove.
(__arm_vaddvq_s32): Remove.
(__arm_vaddvq_u8): Remove.
(__arm_vaddvq_u16): Remove.
(__arm_vaddvq_u32): Remove.
(__arm_vaddvq_p_u8): Remove.
(__arm_vaddvq_p_s8): Remove.
(__arm_vaddvq_p_u16): Remove.
(__arm_vaddvq_p_s16): Remove.
(__arm_vaddvq_p_u32): Remove.
(__arm_vaddvq_p_s32): Remove.
(__arm_vaddvq): Remove.
(__arm_vaddvq_p): Remove.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-shapes.cc (unary_int32): New.
* config/arm/arm-mve-builtins-shapes.h (unary_int32): New.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (mve_insn): Add vaddv.
* config/arm/mve.md (@mve_vaddvq_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_<supf><mode>): ... this.
(mve_vaddvq_p_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_p_<supf><mode>): ... this.
* config/arm/vec-common.md: Use gen_mve_q instead of
gen_mve_vaddvq.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (FUNCTION_ONLY_N): New.
(vdupq): New.
* config/arm/arm-mve-builtins-base.def (vdupq): New.
* config/arm/arm-mve-builtins-base.h: (vdupq): New.
* config/arm/arm_mve.h (vdupq_n): Remove.
(vdupq_m): Remove.
(vdupq_n_f16): Remove.
(vdupq_n_f32): Remove.
(vdupq_n_s8): Remove.
(vdupq_n_s16): Remove.
(vdupq_n_s32): Remove.
(vdupq_n_u8): Remove.
(vdupq_n_u16): Remove.
(vdupq_n_u32): Remove.
(vdupq_m_n_u8): Remove.
(vdupq_m_n_s8): Remove.
(vdupq_m_n_u16): Remove.
(vdupq_m_n_s16): Remove.
(vdupq_m_n_u32): Remove.
(vdupq_m_n_s32): Remove.
(vdupq_m_n_f16): Remove.
(vdupq_m_n_f32): Remove.
(vdupq_x_n_s8): Remove.
(vdupq_x_n_s16): Remove.
(vdupq_x_n_s32): Remove.
(vdupq_x_n_u8): Remove.
(vdupq_x_n_u16): Remove.
(vdupq_x_n_u32): Remove.
(vdupq_x_n_f16): Remove.
(vdupq_x_n_f32): Remove.
(__arm_vdupq_n_s8): Remove.
(__arm_vdupq_n_s16): Remove.
(__arm_vdupq_n_s32): Remove.
(__arm_vdupq_n_u8): Remove.
(__arm_vdupq_n_u16): Remove.
(__arm_vdupq_n_u32): Remove.
(__arm_vdupq_m_n_u8): Remove.
(__arm_vdupq_m_n_s8): Remove.
(__arm_vdupq_m_n_u16): Remove.
(__arm_vdupq_m_n_s16): Remove.
(__arm_vdupq_m_n_u32): Remove.
(__arm_vdupq_m_n_s32): Remove.
(__arm_vdupq_x_n_s8): Remove.
(__arm_vdupq_x_n_s16): Remove.
(__arm_vdupq_x_n_s32): Remove.
(__arm_vdupq_x_n_u8): Remove.
(__arm_vdupq_x_n_u16): Remove.
(__arm_vdupq_x_n_u32): Remove.
(__arm_vdupq_n_f16): Remove.
(__arm_vdupq_n_f32): Remove.
(__arm_vdupq_m_n_f16): Remove.
(__arm_vdupq_m_n_f32): Remove.
(__arm_vdupq_x_n_f16): Remove.
(__arm_vdupq_x_n_f32): Remove.
(__arm_vdupq_n): Remove.
(__arm_vdupq_m): Remove.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-shapes.cc (unary_n): New.
* config/arm/arm-mve-builtins-shapes.h (unary_n): New.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (MVE_FP_M_N_VDUPQ_ONLY)
(MVE_FP_N_VDUPQ_ONLY): New.
(mve_insn): Add vdupq.
* config/arm/mve.md (mve_vdupq_n_f<mode>): Rename into ...
(@mve_<mve_insn>q_n_f<mode>): ... this.
(mve_vdupq_n_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_n_<supf><mode>): ... this.
(mve_vdupq_m_n_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
(mve_vdupq_m_n_f<mode>): Rename into ...
(@mve_<mve_insn>q_m_n_f<mode>): ... this.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (vrev16q, vrev32q, vrev64q):
New.
* config/arm/arm-mve-builtins-base.def (vrev16q, vrev32q)
(vrev64q): New.
* config/arm/arm-mve-builtins-base.h (vrev16q, vrev32q)
(vrev64q): New.
* config/arm/arm_mve.h (vrev16q): Remove.
(vrev32q): Remove.
(vrev64q): Remove.
(vrev64q_m): Remove.
(vrev16q_m): Remove.
(vrev32q_m): Remove.
(vrev16q_x): Remove.
(vrev32q_x): Remove.
(vrev64q_x): Remove.
(vrev64q_f16): Remove.
(vrev64q_f32): Remove.
(vrev32q_f16): Remove.
(vrev16q_s8): Remove.
(vrev32q_s8): Remove.
(vrev32q_s16): Remove.
(vrev64q_s8): Remove.
(vrev64q_s16): Remove.
(vrev64q_s32): Remove.
(vrev64q_u8): Remove.
(vrev64q_u16): Remove.
(vrev64q_u32): Remove.
(vrev32q_u8): Remove.
(vrev32q_u16): Remove.
(vrev16q_u8): Remove.
(vrev64q_m_u8): Remove.
(vrev64q_m_s8): Remove.
(vrev64q_m_u16): Remove.
(vrev64q_m_s16): Remove.
(vrev64q_m_u32): Remove.
(vrev64q_m_s32): Remove.
(vrev16q_m_s8): Remove.
(vrev32q_m_f16): Remove.
(vrev16q_m_u8): Remove.
(vrev32q_m_s8): Remove.
(vrev64q_m_f16): Remove.
(vrev32q_m_u8): Remove.
(vrev32q_m_s16): Remove.
(vrev64q_m_f32): Remove.
(vrev32q_m_u16): Remove.
(vrev16q_x_s8): Remove.
(vrev16q_x_u8): Remove.
(vrev32q_x_s8): Remove.
(vrev32q_x_s16): Remove.
(vrev32q_x_u8): Remove.
(vrev32q_x_u16): Remove.
(vrev64q_x_s8): Remove.
(vrev64q_x_s16): Remove.
(vrev64q_x_s32): Remove.
(vrev64q_x_u8): Remove.
(vrev64q_x_u16): Remove.
(vrev64q_x_u32): Remove.
(vrev32q_x_f16): Remove.
(vrev64q_x_f16): Remove.
(vrev64q_x_f32): Remove.
(__arm_vrev16q_s8): Remove.
(__arm_vrev32q_s8): Remove.
(__arm_vrev32q_s16): Remove.
(__arm_vrev64q_s8): Remove.
(__arm_vrev64q_s16): Remove.
(__arm_vrev64q_s32): Remove.
(__arm_vrev64q_u8): Remove.
(__arm_vrev64q_u16): Remove.
(__arm_vrev64q_u32): Remove.
(__arm_vrev32q_u8): Remove.
(__arm_vrev32q_u16): Remove.
(__arm_vrev16q_u8): Remove.
(__arm_vrev64q_m_u8): Remove.
(__arm_vrev64q_m_s8): Remove.
(__arm_vrev64q_m_u16): Remove.
(__arm_vrev64q_m_s16): Remove.
(__arm_vrev64q_m_u32): Remove.
(__arm_vrev64q_m_s32): Remove.
(__arm_vrev16q_m_s8): Remove.
(__arm_vrev16q_m_u8): Remove.
(__arm_vrev32q_m_s8): Remove.
(__arm_vrev32q_m_u8): Remove.
(__arm_vrev32q_m_s16): Remove.
(__arm_vrev32q_m_u16): Remove.
(__arm_vrev16q_x_s8): Remove.
(__arm_vrev16q_x_u8): Remove.
(__arm_vrev32q_x_s8): Remove.
(__arm_vrev32q_x_s16): Remove.
(__arm_vrev32q_x_u8): Remove.
(__arm_vrev32q_x_u16): Remove.
(__arm_vrev64q_x_s8): Remove.
(__arm_vrev64q_x_s16): Remove.
(__arm_vrev64q_x_s32): Remove.
(__arm_vrev64q_x_u8): Remove.
(__arm_vrev64q_x_u16): Remove.
(__arm_vrev64q_x_u32): Remove.
(__arm_vrev64q_f16): Remove.
(__arm_vrev64q_f32): Remove.
(__arm_vrev32q_f16): Remove.
(__arm_vrev32q_m_f16): Remove.
(__arm_vrev64q_m_f16): Remove.
(__arm_vrev64q_m_f32): Remove.
(__arm_vrev32q_x_f16): Remove.
(__arm_vrev64q_x_f16): Remove.
(__arm_vrev64q_x_f32): Remove.
(__arm_vrev16q): Remove.
(__arm_vrev32q): Remove.
(__arm_vrev64q): Remove.
(__arm_vrev64q_m): Remove.
(__arm_vrev16q_m): Remove.
(__arm_vrev32q_m): Remove.
(__arm_vrev16q_x): Remove.
(__arm_vrev32q_x): Remove.
(__arm_vrev64q_x): Remove.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (MVE_V8HF, MVE_V16QI)
(MVE_FP_VREV64Q_ONLY, MVE_FP_M_VREV64Q_ONLY, MVE_FP_VREV32Q_ONLY)
(MVE_FP_M_VREV32Q_ONLY): New iterators.
(mve_insn): Add vrev16q, vrev32q, vrev64q.
* config/arm/mve.md (mve_vrev64q_f<mode>): Rename into ...
(@mve_<mve_insn>q_f<mode>): ... this
(mve_vrev32q_fv8hf): Rename into @mve_<mve_insn>q_f<mode>.
(mve_vrev64q_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_<supf><mode>): ... this.
(mve_vrev32q_<supf><mode>): Rename into
@mve_<mve_insn>q_<supf><mode>.
(mve_vrev16q_<supf>v16qi): Rename into
@mve_<mve_insn>q_<supf><mode>.
(mve_vrev64q_m_<supf><mode>): Rename into
@mve_<mve_insn>q_m_<supf><mode>.
(mve_vrev32q_m_fv8hf): Rename into @mve_<mve_insn>q_m_f<mode>.
(mve_vrev32q_m_<supf><mode>): Rename into
@mve_<mve_insn>q_m_<supf><mode>.
(mve_vrev64q_m_f<mode>): Rename into @mve_<mve_insn>q_m_f<mode>.
(mve_vrev16q_m_<supf>v16qi): Rename into
@mve_<mve_insn>q_m_<supf><mode>.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (vcmpeqq, vcmpneq, vcmpgeq)
(vcmpgtq, vcmpleq, vcmpltq, vcmpcsq, vcmphiq): New.
* config/arm/arm-mve-builtins-base.def (vcmpeqq, vcmpneq, vcmpgeq)
(vcmpgtq, vcmpleq, vcmpltq, vcmpcsq, vcmphiq): New.
* config/arm/arm-mve-builtins-base.h (vcmpeqq, vcmpneq, vcmpgeq)
(vcmpgtq, vcmpleq, vcmpltq, vcmpcsq, vcmphiq): New.
* config/arm/arm-mve-builtins-functions.h (class
unspec_based_mve_function_exact_insn_vcmp): New.
* config/arm/arm-mve-builtins.cc
(function_instance::has_inactive_argument): Handle vcmp.
* config/arm/arm_mve.h (vcmpneq): Remove.
(vcmphiq): Remove.
(vcmpeqq): Remove.
(vcmpcsq): Remove.
(vcmpltq): Remove.
(vcmpleq): Remove.
(vcmpgtq): Remove.
(vcmpgeq): Remove.
(vcmpneq_m): Remove.
(vcmphiq_m): Remove.
(vcmpeqq_m): Remove.
(vcmpcsq_m): Remove.
(vcmpcsq_m_n): Remove.
(vcmpltq_m): Remove.
(vcmpleq_m): Remove.
(vcmpgtq_m): Remove.
(vcmpgeq_m): Remove.
(vcmpneq_s8): Remove.
(vcmpneq_s16): Remove.
(vcmpneq_s32): Remove.
(vcmpneq_u8): Remove.
(vcmpneq_u16): Remove.
(vcmpneq_u32): Remove.
(vcmpneq_n_u8): Remove.
(vcmphiq_u8): Remove.
(vcmphiq_n_u8): Remove.
(vcmpeqq_u8): Remove.
(vcmpeqq_n_u8): Remove.
(vcmpcsq_u8): Remove.
(vcmpcsq_n_u8): Remove.
(vcmpneq_n_s8): Remove.
(vcmpltq_s8): Remove.
(vcmpltq_n_s8): Remove.
(vcmpleq_s8): Remove.
(vcmpleq_n_s8): Remove.
(vcmpgtq_s8): Remove.
(vcmpgtq_n_s8): Remove.
(vcmpgeq_s8): Remove.
(vcmpgeq_n_s8): Remove.
(vcmpeqq_s8): Remove.
(vcmpeqq_n_s8): Remove.
(vcmpneq_n_u16): Remove.
(vcmphiq_u16): Remove.
(vcmphiq_n_u16): Remove.
(vcmpeqq_u16): Remove.
(vcmpeqq_n_u16): Remove.
(vcmpcsq_u16): Remove.
(vcmpcsq_n_u16): Remove.
(vcmpneq_n_s16): Remove.
(vcmpltq_s16): Remove.
(vcmpltq_n_s16): Remove.
(vcmpleq_s16): Remove.
(vcmpleq_n_s16): Remove.
(vcmpgtq_s16): Remove.
(vcmpgtq_n_s16): Remove.
(vcmpgeq_s16): Remove.
(vcmpgeq_n_s16): Remove.
(vcmpeqq_s16): Remove.
(vcmpeqq_n_s16): Remove.
(vcmpneq_n_u32): Remove.
(vcmphiq_u32): Remove.
(vcmphiq_n_u32): Remove.
(vcmpeqq_u32): Remove.
(vcmpeqq_n_u32): Remove.
(vcmpcsq_u32): Remove.
(vcmpcsq_n_u32): Remove.
(vcmpneq_n_s32): Remove.
(vcmpltq_s32): Remove.
(vcmpltq_n_s32): Remove.
(vcmpleq_s32): Remove.
(vcmpleq_n_s32): Remove.
(vcmpgtq_s32): Remove.
(vcmpgtq_n_s32): Remove.
(vcmpgeq_s32): Remove.
(vcmpgeq_n_s32): Remove.
(vcmpeqq_s32): Remove.
(vcmpeqq_n_s32): Remove.
(vcmpneq_n_f16): Remove.
(vcmpneq_f16): Remove.
(vcmpltq_n_f16): Remove.
(vcmpltq_f16): Remove.
(vcmpleq_n_f16): Remove.
(vcmpleq_f16): Remove.
(vcmpgtq_n_f16): Remove.
(vcmpgtq_f16): Remove.
(vcmpgeq_n_f16): Remove.
(vcmpgeq_f16): Remove.
(vcmpeqq_n_f16): Remove.
(vcmpeqq_f16): Remove.
(vcmpneq_n_f32): Remove.
(vcmpneq_f32): Remove.
(vcmpltq_n_f32): Remove.
(vcmpltq_f32): Remove.
(vcmpleq_n_f32): Remove.
(vcmpleq_f32): Remove.
(vcmpgtq_n_f32): Remove.
(vcmpgtq_f32): Remove.
(vcmpgeq_n_f32): Remove.
(vcmpgeq_f32): Remove.
(vcmpeqq_n_f32): Remove.
(vcmpeqq_f32): Remove.
(vcmpeqq_m_f16): Remove.
(vcmpeqq_m_f32): Remove.
(vcmpneq_m_u8): Remove.
(vcmpneq_m_n_u8): Remove.
(vcmphiq_m_u8): Remove.
(vcmphiq_m_n_u8): Remove.
(vcmpeqq_m_u8): Remove.
(vcmpeqq_m_n_u8): Remove.
(vcmpcsq_m_u8): Remove.
(vcmpcsq_m_n_u8): Remove.
(vcmpneq_m_s8): Remove.
(vcmpneq_m_n_s8): Remove.
(vcmpltq_m_s8): Remove.
(vcmpltq_m_n_s8): Remove.
(vcmpleq_m_s8): Remove.
(vcmpleq_m_n_s8): Remove.
(vcmpgtq_m_s8): Remove.
(vcmpgtq_m_n_s8): Remove.
(vcmpgeq_m_s8): Remove.
(vcmpgeq_m_n_s8): Remove.
(vcmpeqq_m_s8): Remove.
(vcmpeqq_m_n_s8): Remove.
(vcmpneq_m_u16): Remove.
(vcmpneq_m_n_u16): Remove.
(vcmphiq_m_u16): Remove.
(vcmphiq_m_n_u16): Remove.
(vcmpeqq_m_u16): Remove.
(vcmpeqq_m_n_u16): Remove.
(vcmpcsq_m_u16): Remove.
(vcmpcsq_m_n_u16): Remove.
(vcmpneq_m_s16): Remove.
(vcmpneq_m_n_s16): Remove.
(vcmpltq_m_s16): Remove.
(vcmpltq_m_n_s16): Remove.
(vcmpleq_m_s16): Remove.
(vcmpleq_m_n_s16): Remove.
(vcmpgtq_m_s16): Remove.
(vcmpgtq_m_n_s16): Remove.
(vcmpgeq_m_s16): Remove.
(vcmpgeq_m_n_s16): Remove.
(vcmpeqq_m_s16): Remove.
(vcmpeqq_m_n_s16): Remove.
(vcmpneq_m_u32): Remove.
(vcmpneq_m_n_u32): Remove.
(vcmphiq_m_u32): Remove.
(vcmphiq_m_n_u32): Remove.
(vcmpeqq_m_u32): Remove.
(vcmpeqq_m_n_u32): Remove.
(vcmpcsq_m_u32): Remove.
(vcmpcsq_m_n_u32): Remove.
(vcmpneq_m_s32): Remove.
(vcmpneq_m_n_s32): Remove.
(vcmpltq_m_s32): Remove.
(vcmpltq_m_n_s32): Remove.
(vcmpleq_m_s32): Remove.
(vcmpleq_m_n_s32): Remove.
(vcmpgtq_m_s32): Remove.
(vcmpgtq_m_n_s32): Remove.
(vcmpgeq_m_s32): Remove.
(vcmpgeq_m_n_s32): Remove.
(vcmpeqq_m_s32): Remove.
(vcmpeqq_m_n_s32): Remove.
(vcmpeqq_m_n_f16): Remove.
(vcmpgeq_m_f16): Remove.
(vcmpgeq_m_n_f16): Remove.
(vcmpgtq_m_f16): Remove.
(vcmpgtq_m_n_f16): Remove.
(vcmpleq_m_f16): Remove.
(vcmpleq_m_n_f16): Remove.
(vcmpltq_m_f16): Remove.
(vcmpltq_m_n_f16): Remove.
(vcmpneq_m_f16): Remove.
(vcmpneq_m_n_f16): Remove.
(vcmpeqq_m_n_f32): Remove.
(vcmpgeq_m_f32): Remove.
(vcmpgeq_m_n_f32): Remove.
(vcmpgtq_m_f32): Remove.
(vcmpgtq_m_n_f32): Remove.
(vcmpleq_m_f32): Remove.
(vcmpleq_m_n_f32): Remove.
(vcmpltq_m_f32): Remove.
(vcmpltq_m_n_f32): Remove.
(vcmpneq_m_f32): Remove.
(vcmpneq_m_n_f32): Remove.
(__arm_vcmpneq_s8): Remove.
(__arm_vcmpneq_s16): Remove.
(__arm_vcmpneq_s32): Remove.
(__arm_vcmpneq_u8): Remove.
(__arm_vcmpneq_u16): Remove.
(__arm_vcmpneq_u32): Remove.
(__arm_vcmpneq_n_u8): Remove.
(__arm_vcmphiq_u8): Remove.
(__arm_vcmphiq_n_u8): Remove.
(__arm_vcmpeqq_u8): Remove.
(__arm_vcmpeqq_n_u8): Remove.
(__arm_vcmpcsq_u8): Remove.
(__arm_vcmpcsq_n_u8): Remove.
(__arm_vcmpneq_n_s8): Remove.
(__arm_vcmpltq_s8): Remove.
(__arm_vcmpltq_n_s8): Remove.
(__arm_vcmpleq_s8): Remove.
(__arm_vcmpleq_n_s8): Remove.
(__arm_vcmpgtq_s8): Remove.
(__arm_vcmpgtq_n_s8): Remove.
(__arm_vcmpgeq_s8): Remove.
(__arm_vcmpgeq_n_s8): Remove.
(__arm_vcmpeqq_s8): Remove.
(__arm_vcmpeqq_n_s8): Remove.
(__arm_vcmpneq_n_u16): Remove.
(__arm_vcmphiq_u16): Remove.
(__arm_vcmphiq_n_u16): Remove.
(__arm_vcmpeqq_u16): Remove.
(__arm_vcmpeqq_n_u16): Remove.
(__arm_vcmpcsq_u16): Remove.
(__arm_vcmpcsq_n_u16): Remove.
(__arm_vcmpneq_n_s16): Remove.
(__arm_vcmpltq_s16): Remove.
(__arm_vcmpltq_n_s16): Remove.
(__arm_vcmpleq_s16): Remove.
(__arm_vcmpleq_n_s16): Remove.
(__arm_vcmpgtq_s16): Remove.
(__arm_vcmpgtq_n_s16): Remove.
(__arm_vcmpgeq_s16): Remove.
(__arm_vcmpgeq_n_s16): Remove.
(__arm_vcmpeqq_s16): Remove.
(__arm_vcmpeqq_n_s16): Remove.
(__arm_vcmpneq_n_u32): Remove.
(__arm_vcmphiq_u32): Remove.
(__arm_vcmphiq_n_u32): Remove.
(__arm_vcmpeqq_u32): Remove.
(__arm_vcmpeqq_n_u32): Remove.
(__arm_vcmpcsq_u32): Remove.
(__arm_vcmpcsq_n_u32): Remove.
(__arm_vcmpneq_n_s32): Remove.
(__arm_vcmpltq_s32): Remove.
(__arm_vcmpltq_n_s32): Remove.
(__arm_vcmpleq_s32): Remove.
(__arm_vcmpleq_n_s32): Remove.
(__arm_vcmpgtq_s32): Remove.
(__arm_vcmpgtq_n_s32): Remove.
(__arm_vcmpgeq_s32): Remove.
(__arm_vcmpgeq_n_s32): Remove.
(__arm_vcmpeqq_s32): Remove.
(__arm_vcmpeqq_n_s32): Remove.
(__arm_vcmpneq_m_u8): Remove.
(__arm_vcmpneq_m_n_u8): Remove.
(__arm_vcmphiq_m_u8): Remove.
(__arm_vcmphiq_m_n_u8): Remove.
(__arm_vcmpeqq_m_u8): Remove.
(__arm_vcmpeqq_m_n_u8): Remove.
(__arm_vcmpcsq_m_u8): Remove.
(__arm_vcmpcsq_m_n_u8): Remove.
(__arm_vcmpneq_m_s8): Remove.
(__arm_vcmpneq_m_n_s8): Remove.
(__arm_vcmpltq_m_s8): Remove.
(__arm_vcmpltq_m_n_s8): Remove.
(__arm_vcmpleq_m_s8): Remove.
(__arm_vcmpleq_m_n_s8): Remove.
(__arm_vcmpgtq_m_s8): Remove.
(__arm_vcmpgtq_m_n_s8): Remove.
(__arm_vcmpgeq_m_s8): Remove.
(__arm_vcmpgeq_m_n_s8): Remove.
(__arm_vcmpeqq_m_s8): Remove.
(__arm_vcmpeqq_m_n_s8): Remove.
(__arm_vcmpneq_m_u16): Remove.
(__arm_vcmpneq_m_n_u16): Remove.
(__arm_vcmphiq_m_u16): Remove.
(__arm_vcmphiq_m_n_u16): Remove.
(__arm_vcmpeqq_m_u16): Remove.
(__arm_vcmpeqq_m_n_u16): Remove.
(__arm_vcmpcsq_m_u16): Remove.
(__arm_vcmpcsq_m_n_u16): Remove.
(__arm_vcmpneq_m_s16): Remove.
(__arm_vcmpneq_m_n_s16): Remove.
(__arm_vcmpltq_m_s16): Remove.
(__arm_vcmpltq_m_n_s16): Remove.
(__arm_vcmpleq_m_s16): Remove.
(__arm_vcmpleq_m_n_s16): Remove.
(__arm_vcmpgtq_m_s16): Remove.
(__arm_vcmpgtq_m_n_s16): Remove.
(__arm_vcmpgeq_m_s16): Remove.
(__arm_vcmpgeq_m_n_s16): Remove.
(__arm_vcmpeqq_m_s16): Remove.
(__arm_vcmpeqq_m_n_s16): Remove.
(__arm_vcmpneq_m_u32): Remove.
(__arm_vcmpneq_m_n_u32): Remove.
(__arm_vcmphiq_m_u32): Remove.
(__arm_vcmphiq_m_n_u32): Remove.
(__arm_vcmpeqq_m_u32): Remove.
(__arm_vcmpeqq_m_n_u32): Remove.
(__arm_vcmpcsq_m_u32): Remove.
(__arm_vcmpcsq_m_n_u32): Remove.
(__arm_vcmpneq_m_s32): Remove.
(__arm_vcmpneq_m_n_s32): Remove.
(__arm_vcmpltq_m_s32): Remove.
(__arm_vcmpltq_m_n_s32): Remove.
(__arm_vcmpleq_m_s32): Remove.
(__arm_vcmpleq_m_n_s32): Remove.
(__arm_vcmpgtq_m_s32): Remove.
(__arm_vcmpgtq_m_n_s32): Remove.
(__arm_vcmpgeq_m_s32): Remove.
(__arm_vcmpgeq_m_n_s32): Remove.
(__arm_vcmpeqq_m_s32): Remove.
(__arm_vcmpeqq_m_n_s32): Remove.
(__arm_vcmpneq_n_f16): Remove.
(__arm_vcmpneq_f16): Remove.
(__arm_vcmpltq_n_f16): Remove.
(__arm_vcmpltq_f16): Remove.
(__arm_vcmpleq_n_f16): Remove.
(__arm_vcmpleq_f16): Remove.
(__arm_vcmpgtq_n_f16): Remove.
(__arm_vcmpgtq_f16): Remove.
(__arm_vcmpgeq_n_f16): Remove.
(__arm_vcmpgeq_f16): Remove.
(__arm_vcmpeqq_n_f16): Remove.
(__arm_vcmpeqq_f16): Remove.
(__arm_vcmpneq_n_f32): Remove.
(__arm_vcmpneq_f32): Remove.
(__arm_vcmpltq_n_f32): Remove.
(__arm_vcmpltq_f32): Remove.
(__arm_vcmpleq_n_f32): Remove.
(__arm_vcmpleq_f32): Remove.
(__arm_vcmpgtq_n_f32): Remove.
(__arm_vcmpgtq_f32): Remove.
(__arm_vcmpgeq_n_f32): Remove.
(__arm_vcmpgeq_f32): Remove.
(__arm_vcmpeqq_n_f32): Remove.
(__arm_vcmpeqq_f32): Remove.
(__arm_vcmpeqq_m_f16): Remove.
(__arm_vcmpeqq_m_f32): Remove.
(__arm_vcmpeqq_m_n_f16): Remove.
(__arm_vcmpgeq_m_f16): Remove.
(__arm_vcmpgeq_m_n_f16): Remove.
(__arm_vcmpgtq_m_f16): Remove.
(__arm_vcmpgtq_m_n_f16): Remove.
(__arm_vcmpleq_m_f16): Remove.
(__arm_vcmpleq_m_n_f16): Remove.
(__arm_vcmpltq_m_f16): Remove.
(__arm_vcmpltq_m_n_f16): Remove.
(__arm_vcmpneq_m_f16): Remove.
(__arm_vcmpneq_m_n_f16): Remove.
(__arm_vcmpeqq_m_n_f32): Remove.
(__arm_vcmpgeq_m_f32): Remove.
(__arm_vcmpgeq_m_n_f32): Remove.
(__arm_vcmpgtq_m_f32): Remove.
(__arm_vcmpgtq_m_n_f32): Remove.
(__arm_vcmpleq_m_f32): Remove.
(__arm_vcmpleq_m_n_f32): Remove.
(__arm_vcmpltq_m_f32): Remove.
(__arm_vcmpltq_m_n_f32): Remove.
(__arm_vcmpneq_m_f32): Remove.
(__arm_vcmpneq_m_n_f32): Remove.
(__arm_vcmpneq): Remove.
(__arm_vcmphiq): Remove.
(__arm_vcmpeqq): Remove.
(__arm_vcmpcsq): Remove.
(__arm_vcmpltq): Remove.
(__arm_vcmpleq): Remove.
(__arm_vcmpgtq): Remove.
(__arm_vcmpgeq): Remove.
(__arm_vcmpneq_m): Remove.
(__arm_vcmphiq_m): Remove.
(__arm_vcmpeqq_m): Remove.
(__arm_vcmpcsq_m): Remove.
(__arm_vcmpltq_m): Remove.
(__arm_vcmpleq_m): Remove.
(__arm_vcmpgtq_m): Remove.
(__arm_vcmpgeq_m): Remove.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-shapes.cc (cmp): New.
* config/arm/arm-mve-builtins-shapes.h (cmp): New.
2023-05-11 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (MVE_CMP_M, MVE_CMP_M_F, MVE_CMP_M_N)
(MVE_CMP_M_N_F, mve_cmp_op1): New.
(isu): Add VCMP*
(supf): Likewise.
* config/arm/mve.md (mve_vcmp<mve_cmp_op>q_n_<mode>): Rename into ...
(@mve_vcmp<mve_cmp_op>q_n_<mode>): ... this.
(mve_vcmpeqq_m_f<mode>, mve_vcmpgeq_m_f<mode>)
(mve_vcmpgtq_m_f<mode>, mve_vcmpleq_m_f<mode>)
(mve_vcmpltq_m_f<mode>, mve_vcmpneq_m_f<mode>): Merge into ...
(@mve_vcmp<mve_cmp_op1>q_m_f<mode>): ... this.
(mve_vcmpcsq_m_u<mode>, mve_vcmpeqq_m_<supf><mode>)
(mve_vcmpgeq_m_s<mode>, mve_vcmpgtq_m_s<mode>)
(mve_vcmphiq_m_u<mode>, mve_vcmpleq_m_s<mode>)
(mve_vcmpltq_m_s<mode>, mve_vcmpneq_m_<supf><mode>): Merge into
...
(@mve_vcmp<mve_cmp_op1>q_m_<supf><mode>): ... this.
(mve_vcmpcsq_m_n_u<mode>, mve_vcmpeqq_m_n_<supf><mode>)
(mve_vcmpgeq_m_n_s<mode>, mve_vcmpgtq_m_n_s<mode>)
(mve_vcmphiq_m_n_u<mode>, mve_vcmpleq_m_n_s<mode>)
(mve_vcmpltq_m_n_s<mode>, mve_vcmpneq_m_n_<supf><mode>): Merge
into ...
(@mve_vcmp<mve_cmp_op1>q_m_n_<supf><mode>): ... this.
(mve_vcmpeqq_m_n_f<mode>, mve_vcmpgeq_m_n_f<mode>)
(mve_vcmpgtq_m_n_f<mode>, mve_vcmpleq_m_n_f<mode>)
(mve_vcmpltq_m_n_f<mode>, mve_vcmpneq_m_n_f<mode>): Merge into ...
(@mve_vcmp<mve_cmp_op1>q_m_n_f<mode>): ... this.
2023-05-11 Roger Sayle <roger@nextmovesoftware.com>
* match.pd <popcount optimizations>: Simplify popcount(X|Y) +
popcount(X&Y) as popcount(X)+popcount(Y). Likewise, simplify
popcount(X)+popcount(Y)-popcount(X&Y) as popcount(X|Y), and
vice versa.
2023-05-11 Roger Sayle <roger@nextmovesoftware.com>
* match.pd <popcount optimizations>: Simplify popcount(bswap(x))
as popcount(x). Simplify popcount(rotate(x,y)) as popcount(x).
<parity optimizations>: Simplify parity(bswap(x)) as parity(x).
Simplify parity(rotate(x,y)) as parity(x).
2023-05-11 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/autovec.md (@vec_series<mode>): New pattern
* config/riscv/riscv-protos.h (expand_vec_series): New function.
* config/riscv/riscv-v.cc (emit_binop): Ditto.
(emit_index_op): Ditto.
(expand_vec_series): Ditto.
(expand_const_vector): Add series vector handling.
* config/riscv/riscv.cc (riscv_const_insns): Enable series vector for testing.
2023-05-10 Roger Sayle <roger@nextmovesoftware.com>
* config/i386/i386.md (*concat<mode><dwi>3_1): Use preferred
[(const_int 0)] idiom, instead of [(clobber (const_int 0))].
(*concat<mode><dwi>3_2): Likewise.
(*concat<mode><dwi>3_3): Likewise.
(*concat<mode><dwi>3_4): Likewise.
(*concat<mode><dwi>3_5): Likewise.
(*concat<mode><dwi>3_6): Likewise.
(*concat<mode><dwi>3_7): Likewise.
2023-05-10 Uros Bizjak <ubizjak@gmail.com>
PR target/92658
* config/i386/mmx.md (sse4_1_<code>v2qiv2si2): New insn pattern.
(<insn>v4qiv4hi2): New expander.
(<insn>v2hiv2si2): Ditto.
(<insn>v2qiv2si2): Ditto.
(<insn>v2qiv2hi2): Ditto.
2023-05-10 Jeff Law <jlaw@ventanamicro>
* config/h8300/constraints.md (Q): Make this a special memory
constraint.
(Zz): Similarly.
2023-05-10 Jakub Jelinek <jakub@redhat.com>
PR fortran/109788
* ipa-prop.cc (ipa_get_callee_param_type): Don't return TREE_VALUE (t)
if t is void_list_node.
2023-05-10 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-simd.md (aarch64_sqmovun<mode>_insn_le): Delete.
(aarch64_sqmovun<mode>_insn_be): Delete.
(aarch64_sqmovun<mode><vczle><vczbe>): New define_insn.
(aarch64_sqmovun<mode>): Delete expander.
2023-05-10 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR target/99195
* config/aarch64/aarch64-simd.md (aarch64_<PERMUTE:perm_insn><mode>):
Rename to...
(aarch64_<PERMUTE:perm_insn><mode><vczle><vczbe>): ... This.
(aarch64_rev<REVERSE:rev_op><mode>): Rename to...
(aarch64_rev<REVERSE:rev_op><mode><vczle><vczbe>): ... This.
2023-05-10 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR target/99195
* config/aarch64/aarch64-simd.md (aarch64_<su_optab>q<addsub><mode>):
Rename to...
(aarch64_<su_optab>q<addsub><mode><vczle><vczbe>): ... This.
(aarch64_<sur>qadd<mode>): Rename to...
(aarch64_<sur>qadd<mode><vczle><vczbe>): ... This.
2023-05-10 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-simd.md
(aarch64_<sur>q<r>shr<u>n_n<mode>_insn_le): Delete.
(aarch64_<sur>q<r>shr<u>n_n<mode>_insn_be): Delete.
(aarch64_<sur>q<r>shr<u>n_n<mode>_insn<vczle><vczbe>): New define_insn.
(aarch64_<sur>q<r>shr<u>n_n<mode>): Simplify expander.
2023-05-10 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR target/99195
* config/aarch64/aarch64-simd.md (aarch64_xtn<mode>_insn_le): Delete.
(aarch64_xtn<mode>_insn_be): Likewise.
(trunc<mode><Vnarrowq>2): Rename to...
(trunc<mode><Vnarrowq>2<vczle><vczbe>): ... This.
(aarch64_xtn<mode>): Move under the above. Just emit the truncate RTL.
(aarch64_<su>qmovn<mode>): Likewise.
(aarch64_<su>qmovn<mode><vczle><vczbe>): New define_insn.
(aarch64_<su>qmovn<mode>_insn_le): Delete.
(aarch64_<su>qmovn<mode>_insn_be): Likewise.
2023-05-10 Li Xu <xuli1@eswincomputing.com>
* config/riscv/riscv-vsetvl.cc (gen_vsetvl_pat): For vfmv.f.s/vmv.x.s
intruction replace null avl with (const_int 0).
2023-05-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv.cc (riscv_support_vector_misalignment): Fix
incorrect codes.
2023-05-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
PR target/109773
* config/riscv/riscv-vsetvl.cc (avl_source_has_vsetvl_p): New function.
(source_equal_p): Fix dead loop in vsetvl avl checking.
2023-05-10 Hans-Peter Nilsson <hp@axis.com>
* config/cris/cris.cc (cris_postdbr_cmpelim): Correct mode
of modeadjusted_dccr.
2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (vmaxaq, vminaq): New.
* config/arm/arm-mve-builtins-base.def (vmaxaq, vminaq): New.
* config/arm/arm-mve-builtins-base.h (vmaxaq, vminaq): New.
* config/arm/arm-mve-builtins.cc
(function_instance::has_inactive_argument): Handle vmaxaq and
vminaq.
* config/arm/arm_mve.h (vminaq): Remove.
(vmaxaq): Remove.
(vminaq_m): Remove.
(vmaxaq_m): Remove.
(vminaq_s8): Remove.
(vmaxaq_s8): Remove.
(vminaq_s16): Remove.
(vmaxaq_s16): Remove.
(vminaq_s32): Remove.
(vmaxaq_s32): Remove.
(vminaq_m_s8): Remove.
(vmaxaq_m_s8): Remove.
(vminaq_m_s16): Remove.
(vmaxaq_m_s16): Remove.
(vminaq_m_s32): Remove.
(vmaxaq_m_s32): Remove.
(__arm_vminaq_s8): Remove.
(__arm_vmaxaq_s8): Remove.
(__arm_vminaq_s16): Remove.
(__arm_vmaxaq_s16): Remove.
(__arm_vminaq_s32): Remove.
(__arm_vmaxaq_s32): Remove.
(__arm_vminaq_m_s8): Remove.
(__arm_vmaxaq_m_s8): Remove.
(__arm_vminaq_m_s16): Remove.
(__arm_vmaxaq_m_s16): Remove.
(__arm_vminaq_m_s32): Remove.
(__arm_vmaxaq_m_s32): Remove.
(__arm_vminaq): Remove.
(__arm_vmaxaq): Remove.
(__arm_vminaq_m): Remove.
(__arm_vmaxaq_m): Remove.
2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (MVE_VMAXAVMINAQ, MVE_VMAXAVMINAQ_M):
New.
(mve_insn): Add vmaxa, vmina.
(supf): Add VMAXAQ_S, VMAXAQ_M_S, VMINAQ_S, VMINAQ_M_S.
* config/arm/mve.md (mve_vmaxaq_s<mode>, mve_vminaq_s<mode>):
Merge into ...
(@mve_<mve_insn>q_<supf><mode>): ... this.
(mve_vmaxaq_m_s<mode>, mve_vminaq_m_s<mode>): Merge into ...
(@mve_<mve_insn>q_m_<supf><mode>): ... this.
2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-shapes.cc (binary_maxamina): New.
* config/arm/arm-mve-builtins-shapes.h (binary_maxamina): New.
2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (vmaxnmaq, vminnmaq): New.
* config/arm/arm-mve-builtins-base.def (vmaxnmaq, vminnmaq): New.
* config/arm/arm-mve-builtins-base.h (vmaxnmaq, vminnmaq): New.
* config/arm/arm-mve-builtins.cc
(function_instance::has_inactive_argument): Handle vmaxnmaq and
vminnmaq.
* config/arm/arm_mve.h (vminnmaq): Remove.
(vmaxnmaq): Remove.
(vmaxnmaq_m): Remove.
(vminnmaq_m): Remove.
(vminnmaq_f16): Remove.
(vmaxnmaq_f16): Remove.
(vminnmaq_f32): Remove.
(vmaxnmaq_f32): Remove.
(vmaxnmaq_m_f16): Remove.
(vminnmaq_m_f16): Remove.
(vmaxnmaq_m_f32): Remove.
(vminnmaq_m_f32): Remove.
(__arm_vminnmaq_f16): Remove.
(__arm_vmaxnmaq_f16): Remove.
(__arm_vminnmaq_f32): Remove.
(__arm_vmaxnmaq_f32): Remove.
(__arm_vmaxnmaq_m_f16): Remove.
(__arm_vminnmaq_m_f16): Remove.
(__arm_vmaxnmaq_m_f32): Remove.
(__arm_vminnmaq_m_f32): Remove.
(__arm_vminnmaq): Remove.
(__arm_vmaxnmaq): Remove.
(__arm_vmaxnmaq_m): Remove.
(__arm_vminnmaq_m): Remove.
2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (MVE_VMAXNMA_VMINNMAQ)
(MVE_VMAXNMA_VMINNMAQ_M): New.
(mve_insn): Add vmaxnma, vminnma.
* config/arm/mve.md (mve_vmaxnmaq_f<mode>, mve_vminnmaq_f<mode>):
Merge into ...
(@mve_<mve_insn>q_f<mode>): ... this.
(mve_vmaxnmaq_m_f<mode>, mve_vminnmaq_m_f<mode>): Merge into ...
(@mve_<mve_insn>q_m_f<mode>): ... this.
2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (FUNCTION_PRED_P_F): New.
(vmaxnmavq, vmaxnmvq, vminnmavq, vminnmvq): New.
* config/arm/arm-mve-builtins-base.def (vmaxnmavq, vmaxnmvq)
(vminnmavq, vminnmvq): New.
* config/arm/arm-mve-builtins-base.h (vmaxnmavq, vmaxnmvq)
(vminnmavq, vminnmvq): New.
* config/arm/arm_mve.h (vminnmvq): Remove.
(vminnmavq): Remove.
(vmaxnmvq): Remove.
(vmaxnmavq): Remove.
(vmaxnmavq_p): Remove.
(vmaxnmvq_p): Remove.
(vminnmavq_p): Remove.
(vminnmvq_p): Remove.
(vminnmvq_f16): Remove.
(vminnmavq_f16): Remove.
(vmaxnmvq_f16): Remove.
(vmaxnmavq_f16): Remove.
(vminnmvq_f32): Remove.
(vminnmavq_f32): Remove.
(vmaxnmvq_f32): Remove.
(vmaxnmavq_f32): Remove.
(vmaxnmavq_p_f16): Remove.
(vmaxnmvq_p_f16): Remove.
(vminnmavq_p_f16): Remove.
(vminnmvq_p_f16): Remove.
(vmaxnmavq_p_f32): Remove.
(vmaxnmvq_p_f32): Remove.
(vminnmavq_p_f32): Remove.
(vminnmvq_p_f32): Remove.
(__arm_vminnmvq_f16): Remove.
(__arm_vminnmavq_f16): Remove.
(__arm_vmaxnmvq_f16): Remove.
(__arm_vmaxnmavq_f16): Remove.
(__arm_vminnmvq_f32): Remove.
(__arm_vminnmavq_f32): Remove.
(__arm_vmaxnmvq_f32): Remove.
(__arm_vmaxnmavq_f32): Remove.
(__arm_vmaxnmavq_p_f16): Remove.
(__arm_vmaxnmvq_p_f16): Remove.
(__arm_vminnmavq_p_f16): Remove.
(__arm_vminnmvq_p_f16): Remove.
(__arm_vmaxnmavq_p_f32): Remove.
(__arm_vmaxnmvq_p_f32): Remove.
(__arm_vminnmavq_p_f32): Remove.
(__arm_vminnmvq_p_f32): Remove.
(__arm_vminnmvq): Remove.
(__arm_vminnmavq): Remove.
(__arm_vmaxnmvq): Remove.
(__arm_vmaxnmavq): Remove.
(__arm_vmaxnmavq_p): Remove.
(__arm_vmaxnmvq_p): Remove.
(__arm_vminnmavq_p): Remove.
(__arm_vminnmvq_p): Remove.
(__arm_vmaxnmavq_m): Remove.
(__arm_vmaxnmvq_m): Remove.
2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-functions.h
(unspec_mve_function_exact_insn_pred_p): Use code_for_mve_q_p_f.
2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (MVE_VMAXNMxV_MINNMxVQ)
(MVE_VMAXNMxV_MINNMxVQ_P): New.
(mve_insn): Add vmaxnmav, vmaxnmv, vminnmav, vminnmv.
* config/arm/mve.md (mve_vmaxnmavq_f<mode>, mve_vmaxnmvq_f<mode>)
(mve_vminnmavq_f<mode>, mve_vminnmvq_f<mode>): Merge into ...
(@mve_<mve_insn>q_f<mode>): ... this.
(mve_vmaxnmavq_p_f<mode>, mve_vmaxnmvq_p_f<mode>)
(mve_vminnmavq_p_f<mode>, mve_vminnmvq_p_f<mode>): Merge into ...
(@mve_<mve_insn>q_p_f<mode>): ... this.
2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (vmaxnmq, vminnmq): New.
* config/arm/arm-mve-builtins-base.def (vmaxnmq, vminnmq): New.
* config/arm/arm-mve-builtins-base.h (vmaxnmq, vminnmq): New.
* config/arm/arm_mve.h (vminnmq): Remove.
(vmaxnmq): Remove.
(vmaxnmq_m): Remove.
(vminnmq_m): Remove.
(vminnmq_x): Remove.
(vmaxnmq_x): Remove.
(vminnmq_f16): Remove.
(vmaxnmq_f16): Remove.
(vminnmq_f32): Remove.
(vmaxnmq_f32): Remove.
(vmaxnmq_m_f32): Remove.
(vmaxnmq_m_f16): Remove.
(vminnmq_m_f32): Remove.
(vminnmq_m_f16): Remove.
(vminnmq_x_f16): Remove.
(vminnmq_x_f32): Remove.
(vmaxnmq_x_f16): Remove.
(vmaxnmq_x_f32): Remove.
(__arm_vminnmq_f16): Remove.
(__arm_vmaxnmq_f16): Remove.
(__arm_vminnmq_f32): Remove.
(__arm_vmaxnmq_f32): Remove.
(__arm_vmaxnmq_m_f32): Remove.
(__arm_vmaxnmq_m_f16): Remove.
(__arm_vminnmq_m_f32): Remove.
(__arm_vminnmq_m_f16): Remove.
(__arm_vminnmq_x_f16): Remove.
(__arm_vminnmq_x_f32): Remove.
(__arm_vmaxnmq_x_f16): Remove.
(__arm_vmaxnmq_x_f32): Remove.
(__arm_vminnmq): Remove.
(__arm_vmaxnmq): Remove.
(__arm_vmaxnmq_m): Remove.
(__arm_vminnmq_m): Remove.
(__arm_vminnmq_x): Remove.
(__arm_vmaxnmq_x): Remove.
2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (MAX_MIN_F): New.
(MVE_FP_M_BINARY): Add VMAXNMQ_M_F, VMINNMQ_M_F.
(mve_insn): Add vmaxnm, vminnm.
(max_min_f_str): New.
* config/arm/mve.md (mve_vmaxnmq_f<mode>, mve_vminnmq_f<mode>):
Merge into ...
(@mve_<max_min_f_str>q_f<mode>): ... this.
(mve_vmaxnmq_m_f<mode>, mve_vminnmq_m_f<mode>): Merge into ...
(@mve_<mve_insn>q_m_f<mode>): ... this.
2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/vec-common.md (smin<mode>3): Use VDQWH iterator.
(smax<mode>3): Likewise.
2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (FUNCTION_PRED_P_S_U)
(FUNCTION_PRED_P_S): New.
(vmaxavq, vminavq, vmaxvq, vminvq): New.
* config/arm/arm-mve-builtins-base.def (vmaxavq, vminavq, vmaxvq)
(vminvq): New.
* config/arm/arm-mve-builtins-base.h (vmaxavq, vminavq, vmaxvq)
(vminvq): New.
* config/arm/arm_mve.h (vminvq): Remove.
(vmaxvq): Remove.
(vminvq_p): Remove.
(vmaxvq_p): Remove.
(vminvq_u8): Remove.
(vmaxvq_u8): Remove.
(vminvq_s8): Remove.
(vmaxvq_s8): Remove.
(vminvq_u16): Remove.
(vmaxvq_u16): Remove.
(vminvq_s16): Remove.
(vmaxvq_s16): Remove.
(vminvq_u32): Remove.
(vmaxvq_u32): Remove.
(vminvq_s32): Remove.
(vmaxvq_s32): Remove.
(vminvq_p_u8): Remove.
(vmaxvq_p_u8): Remove.
(vminvq_p_s8): Remove.
(vmaxvq_p_s8): Remove.
(vminvq_p_u16): Remove.
(vmaxvq_p_u16): Remove.
(vminvq_p_s16): Remove.
(vmaxvq_p_s16): Remove.
(vminvq_p_u32): Remove.
(vmaxvq_p_u32): Remove.
(vminvq_p_s32): Remove.
(vmaxvq_p_s32): Remove.
(__arm_vminvq_u8): Remove.
(__arm_vmaxvq_u8): Remove.
(__arm_vminvq_s8): Remove.
(__arm_vmaxvq_s8): Remove.
(__arm_vminvq_u16): Remove.
(__arm_vmaxvq_u16): Remove.
(__arm_vminvq_s16): Remove.
(__arm_vmaxvq_s16): Remove.
(__arm_vminvq_u32): Remove.
(__arm_vmaxvq_u32): Remove.
(__arm_vminvq_s32): Remove.
(__arm_vmaxvq_s32): Remove.
(__arm_vminvq_p_u8): Remove.
(__arm_vmaxvq_p_u8): Remove.
(__arm_vminvq_p_s8): Remove.
(__arm_vmaxvq_p_s8): Remove.
(__arm_vminvq_p_u16): Remove.
(__arm_vmaxvq_p_u16): Remove.
(__arm_vminvq_p_s16): Remove.
(__arm_vmaxvq_p_s16): Remove.
(__arm_vminvq_p_u32): Remove.
(__arm_vmaxvq_p_u32): Remove.
(__arm_vminvq_p_s32): Remove.
(__arm_vmaxvq_p_s32): Remove.
(__arm_vminvq): Remove.
(__arm_vmaxvq): Remove.
(__arm_vminvq_p): Remove.
(__arm_vmaxvq_p): Remove.
(vminavq): Remove.
(vmaxavq): Remove.
(vminavq_p): Remove.
(vmaxavq_p): Remove.
(vminavq_s8): Remove.
(vmaxavq_s8): Remove.
(vminavq_s16): Remove.
(vmaxavq_s16): Remove.
(vminavq_s32): Remove.
(vmaxavq_s32): Remove.
(vminavq_p_s8): Remove.
(vmaxavq_p_s8): Remove.
(vminavq_p_s16): Remove.
(vmaxavq_p_s16): Remove.
(vminavq_p_s32): Remove.
(vmaxavq_p_s32): Remove.
(__arm_vminavq_s8): Remove.
(__arm_vmaxavq_s8): Remove.
(__arm_vminavq_s16): Remove.
(__arm_vmaxavq_s16): Remove.
(__arm_vminavq_s32): Remove.
(__arm_vmaxavq_s32): Remove.
(__arm_vminavq_p_s8): Remove.
(__arm_vmaxavq_p_s8): Remove.
(__arm_vminavq_p_s16): Remove.
(__arm_vmaxavq_p_s16): Remove.
(__arm_vminavq_p_s32): Remove.
(__arm_vmaxavq_p_s32): Remove.
(__arm_vminavq): Remove.
(__arm_vmaxavq): Remove.
(__arm_vminavq_p): Remove.
(__arm_vmaxavq_p): Remove.
2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (MVE_VMAXVQ_VMINVQ, MVE_VMAXVQ_VMINVQ_P): New.
(mve_insn): Add vmaxav, vmaxv, vminav, vminv.
(supf): Add VMAXAVQ_S, VMAXAVQ_P_S, VMINAVQ_S, VMINAVQ_P_S.
* config/arm/mve.md (mve_vmaxavq_s<mode>, mve_vmaxvq_<supf><mode>)
(mve_vminavq_s<mode>, mve_vminvq_<supf><mode>): Merge into ...
(@mve_<mve_insn>q_<supf><mode>): ... this.
(mve_vmaxavq_p_s<mode>, mve_vmaxvq_p_<supf><mode>)
(mve_vminavq_p_s<mode>, mve_vminvq_p_<supf><mode>): Merge into ...
(@mve_<mve_insn>q_p_<supf><mode>): ... this.
2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-functions.h (class
unspec_mve_function_exact_insn_pred_p): New.
2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-shapes.cc (binary_maxavminav): New.
* config/arm/arm-mve-builtins-shapes.h (binary_maxavminav): New.
2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-shapes.cc (binary_maxvminv): New.
* config/arm/arm-mve-builtins-shapes.h (binary_maxvminv): New.
2023-05-09 Richard Sandiford <richard.sandiford@arm.com>
* config/aarch64/aarch64-protos.h (aarch64_adjust_reg_alloc_order):
Declare.
* config/aarch64/aarch64.h (REG_ALLOC_ORDER): Define.
(ADJUST_REG_ALLOC_ORDER): Likewise.
* config/aarch64/aarch64.cc (aarch64_adjust_reg_alloc_order): New
function.
* config/aarch64/aarch64-sve.md (*vcond_mask_<mode><vpred>): Use
Upa rather than Upl for unpredicated movprfx alternatives.
2023-05-09 Jeff Law <jlaw@ventanamicro>
* config/h8300/testcompare.md: Add peephole2 which uses a memory
load to set flags, thus eliminating a compare against zero.
2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (vshllbq, vshlltq): New.
* config/arm/arm-mve-builtins-base.def (vshllbq, vshlltq): New.
* config/arm/arm-mve-builtins-base.h (vshllbq, vshlltq): New.
* config/arm/arm_mve.h (vshlltq): Remove.
(vshllbq): Remove.
(vshllbq_m): Remove.
(vshlltq_m): Remove.
(vshllbq_x): Remove.
(vshlltq_x): Remove.
(vshlltq_n_u8): Remove.
(vshllbq_n_u8): Remove.
(vshlltq_n_s8): Remove.
(vshllbq_n_s8): Remove.
(vshlltq_n_u16): Remove.
(vshllbq_n_u16): Remove.
(vshlltq_n_s16): Remove.
(vshllbq_n_s16): Remove.
(vshllbq_m_n_s8): Remove.
(vshllbq_m_n_s16): Remove.
(vshllbq_m_n_u8): Remove.
(vshllbq_m_n_u16): Remove.
(vshlltq_m_n_s8): Remove.
(vshlltq_m_n_s16): Remove.
(vshlltq_m_n_u8): Remove.
(vshlltq_m_n_u16): Remove.
(vshllbq_x_n_s8): Remove.
(vshllbq_x_n_s16): Remove.
(vshllbq_x_n_u8): Remove.
(vshllbq_x_n_u16): Remove.
(vshlltq_x_n_s8): Remove.
(vshlltq_x_n_s16): Remove.
(vshlltq_x_n_u8): Remove.
(vshlltq_x_n_u16): Remove.
(__arm_vshlltq_n_u8): Remove.
(__arm_vshllbq_n_u8): Remove.
(__arm_vshlltq_n_s8): Remove.
(__arm_vshllbq_n_s8): Remove.
(__arm_vshlltq_n_u16): Remove.
(__arm_vshllbq_n_u16): Remove.
(__arm_vshlltq_n_s16): Remove.
(__arm_vshllbq_n_s16): Remove.
(__arm_vshllbq_m_n_s8): Remove.
(__arm_vshllbq_m_n_s16): Remove.
(__arm_vshllbq_m_n_u8): Remove.
(__arm_vshllbq_m_n_u16): Remove.
(__arm_vshlltq_m_n_s8): Remove.
(__arm_vshlltq_m_n_s16): Remove.
(__arm_vshlltq_m_n_u8): Remove.
(__arm_vshlltq_m_n_u16): Remove.
(__arm_vshllbq_x_n_s8): Remove.
(__arm_vshllbq_x_n_s16): Remove.
(__arm_vshllbq_x_n_u8): Remove.
(__arm_vshllbq_x_n_u16): Remove.
(__arm_vshlltq_x_n_s8): Remove.
(__arm_vshlltq_x_n_s16): Remove.
(__arm_vshlltq_x_n_u8): Remove.
(__arm_vshlltq_x_n_u16): Remove.
(__arm_vshlltq): Remove.
(__arm_vshllbq): Remove.
(__arm_vshllbq_m): Remove.
(__arm_vshlltq_m): Remove.
(__arm_vshllbq_x): Remove.
(__arm_vshlltq_x): Remove.
2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (mve_insn): Add vshllb, vshllt.
(VSHLLBQ_N, VSHLLTQ_N): Remove.
(VSHLLxQ_N): New.
(VSHLLBQ_M_N, VSHLLTQ_M_N): Remove.
(VSHLLxQ_M_N): New.
* config/arm/mve.md (mve_vshllbq_n_<supf><mode>)
(mve_vshlltq_n_<supf><mode>): Merge into ...
(@mve_<mve_insn>q_n_<supf><mode>): ... this.
(mve_vshllbq_m_n_<supf><mode>, mve_vshlltq_m_n_<supf><mode>):
Merge into ...
(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-shapes.cc (binary_widen_n): New.
* config/arm/arm-mve-builtins-shapes.h (binary_widen_n): New.
2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (vmovnbq, vmovntq, vqmovnbq)
(vqmovntq, vqmovunbq, vqmovuntq): New.
* config/arm/arm-mve-builtins-base.def (vmovnbq, vmovntq)
(vqmovnbq, vqmovntq, vqmovunbq, vqmovuntq): New.
* config/arm/arm-mve-builtins-base.h (vmovnbq, vmovntq, vqmovnbq)
(vqmovntq, vqmovunbq, vqmovuntq): New.
* config/arm/arm-mve-builtins.cc
(function_instance::has_inactive_argument): Handle vmovnbq,
vmovntq, vqmovnbq, vqmovntq, vqmovunbq, vqmovuntq.
* config/arm/arm_mve.h (vqmovntq): Remove.
(vqmovnbq): Remove.
(vqmovnbq_m): Remove.
(vqmovntq_m): Remove.
(vqmovntq_u16): Remove.
(vqmovnbq_u16): Remove.
(vqmovntq_s16): Remove.
(vqmovnbq_s16): Remove.
(vqmovntq_u32): Remove.
(vqmovnbq_u32): Remove.
(vqmovntq_s32): Remove.
(vqmovnbq_s32): Remove.
(vqmovnbq_m_s16): Remove.
(vqmovntq_m_s16): Remove.
(vqmovnbq_m_u16): Remove.
(vqmovntq_m_u16): Remove.
(vqmovnbq_m_s32): Remove.
(vqmovntq_m_s32): Remove.
(vqmovnbq_m_u32): Remove.
(vqmovntq_m_u32): Remove.
(__arm_vqmovntq_u16): Remove.
(__arm_vqmovnbq_u16): Remove.
(__arm_vqmovntq_s16): Remove.
(__arm_vqmovnbq_s16): Remove.
(__arm_vqmovntq_u32): Remove.
(__arm_vqmovnbq_u32): Remove.
(__arm_vqmovntq_s32): Remove.
(__arm_vqmovnbq_s32): Remove.
(__arm_vqmovnbq_m_s16): Remove.
(__arm_vqmovntq_m_s16): Remove.
(__arm_vqmovnbq_m_u16): Remove.
(__arm_vqmovntq_m_u16): Remove.
(__arm_vqmovnbq_m_s32): Remove.
(__arm_vqmovntq_m_s32): Remove.
(__arm_vqmovnbq_m_u32): Remove.
(__arm_vqmovntq_m_u32): Remove.
(__arm_vqmovntq): Remove.
(__arm_vqmovnbq): Remove.
(__arm_vqmovnbq_m): Remove.
(__arm_vqmovntq_m): Remove.
(vmovntq): Remove.
(vmovnbq): Remove.
(vmovnbq_m): Remove.
(vmovntq_m): Remove.
(vmovntq_u16): Remove.
(vmovnbq_u16): Remove.
(vmovntq_s16): Remove.
(vmovnbq_s16): Remove.
(vmovntq_u32): Remove.
(vmovnbq_u32): Remove.
(vmovntq_s32): Remove.
(vmovnbq_s32): Remove.
(vmovnbq_m_s16): Remove.
(vmovntq_m_s16): Remove.
(vmovnbq_m_u16): Remove.
(vmovntq_m_u16): Remove.
(vmovnbq_m_s32): Remove.
(vmovntq_m_s32): Remove.
(vmovnbq_m_u32): Remove.
(vmovntq_m_u32): Remove.
(__arm_vmovntq_u16): Remove.
(__arm_vmovnbq_u16): Remove.
(__arm_vmovntq_s16): Remove.
(__arm_vmovnbq_s16): Remove.
(__arm_vmovntq_u32): Remove.
(__arm_vmovnbq_u32): Remove.
(__arm_vmovntq_s32): Remove.
(__arm_vmovnbq_s32): Remove.
(__arm_vmovnbq_m_s16): Remove.
(__arm_vmovntq_m_s16): Remove.
(__arm_vmovnbq_m_u16): Remove.
(__arm_vmovntq_m_u16): Remove.
(__arm_vmovnbq_m_s32): Remove.
(__arm_vmovntq_m_s32): Remove.
(__arm_vmovnbq_m_u32): Remove.
(__arm_vmovntq_m_u32): Remove.
(__arm_vmovntq): Remove.
(__arm_vmovnbq): Remove.
(__arm_vmovnbq_m): Remove.
(__arm_vmovntq_m): Remove.
(vqmovuntq): Remove.
(vqmovunbq): Remove.
(vqmovunbq_m): Remove.
(vqmovuntq_m): Remove.
(vqmovuntq_s16): Remove.
(vqmovunbq_s16): Remove.
(vqmovuntq_s32): Remove.
(vqmovunbq_s32): Remove.
(vqmovunbq_m_s16): Remove.
(vqmovuntq_m_s16): Remove.
(vqmovunbq_m_s32): Remove.
(vqmovuntq_m_s32): Remove.
(__arm_vqmovuntq_s16): Remove.
(__arm_vqmovunbq_s16): Remove.
(__arm_vqmovuntq_s32): Remove.
(__arm_vqmovunbq_s32): Remove.
(__arm_vqmovunbq_m_s16): Remove.
(__arm_vqmovuntq_m_s16): Remove.
(__arm_vqmovunbq_m_s32): Remove.
(__arm_vqmovuntq_m_s32): Remove.
(__arm_vqmovuntq): Remove.
(__arm_vqmovunbq): Remove.
(__arm_vqmovunbq_m): Remove.
(__arm_vqmovuntq_m): Remove.
2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (MVE_MOVN, MVE_MOVN_M): New.
(mve_insn): Add vmovnb, vmovnt, vqmovnb, vqmovnt, vqmovunb,
vqmovunt.
(isu): Likewise.
(supf): Add VQMOVUNBQ_M_S, VQMOVUNBQ_S, VQMOVUNTQ_M_S,
VQMOVUNTQ_S.
* config/arm/mve.md (mve_vmovnbq_<supf><mode>)
(mve_vmovntq_<supf><mode>, mve_vqmovnbq_<supf><mode>)
(mve_vqmovntq_<supf><mode>, mve_vqmovunbq_s<mode>)
(mve_vqmovuntq_s<mode>): Merge into ...
(@mve_<mve_insn>q_<supf><mode>): ... this.
(mve_vmovnbq_m_<supf><mode>, mve_vmovntq_m_<supf><mode>)
(mve_vqmovnbq_m_<supf><mode>, mve_vqmovntq_m_<supf><mode>)
(mve_vqmovunbq_m_s<mode>, mve_vqmovuntq_m_s<mode>): Merge into ...
(@mve_<mve_insn>q_m_<supf><mode>): ... this.
2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-shapes.cc (binary_move_narrow): New.
(binary_move_narrow_unsigned): New.
* config/arm/arm-mve-builtins-shapes.h (binary_move_narrow): New.
(binary_move_narrow_unsigned): New.
2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (FUNCTION_ONLY_F): New.
(vrndaq, vrndmq, vrndnq, vrndpq, vrndq, vrndxq): New.
* config/arm/arm-mve-builtins-base.def (vrndaq, vrndmq, vrndnq)
(vrndpq, vrndq, vrndxq): New.
* config/arm/arm-mve-builtins-base.h (vrndaq, vrndmq, vrndnq)
(vrndpq, vrndq, vrndxq): New.
* config/arm/arm_mve.h (vrndxq): Remove.
(vrndq): Remove.
(vrndpq): Remove.
(vrndnq): Remove.
(vrndmq): Remove.
(vrndaq): Remove.
(vrndaq_m): Remove.
(vrndmq_m): Remove.
(vrndnq_m): Remove.
(vrndpq_m): Remove.
(vrndq_m): Remove.
(vrndxq_m): Remove.
(vrndq_x): Remove.
(vrndnq_x): Remove.
(vrndmq_x): Remove.
(vrndpq_x): Remove.
(vrndaq_x): Remove.
(vrndxq_x): Remove.
(vrndxq_f16): Remove.
(vrndxq_f32): Remove.
(vrndq_f16): Remove.
(vrndq_f32): Remove.
(vrndpq_f16): Remove.
(vrndpq_f32): Remove.
(vrndnq_f16): Remove.
(vrndnq_f32): Remove.
(vrndmq_f16): Remove.
(vrndmq_f32): Remove.
(vrndaq_f16): Remove.
(vrndaq_f32): Remove.
(vrndaq_m_f16): Remove.
(vrndmq_m_f16): Remove.
(vrndnq_m_f16): Remove.
(vrndpq_m_f16): Remove.
(vrndq_m_f16): Remove.
(vrndxq_m_f16): Remove.
(vrndaq_m_f32): Remove.
(vrndmq_m_f32): Remove.
(vrndnq_m_f32): Remove.
(vrndpq_m_f32): Remove.
(vrndq_m_f32): Remove.
(vrndxq_m_f32): Remove.
(vrndq_x_f16): Remove.
(vrndq_x_f32): Remove.
(vrndnq_x_f16): Remove.
(vrndnq_x_f32): Remove.
(vrndmq_x_f16): Remove.
(vrndmq_x_f32): Remove.
(vrndpq_x_f16): Remove.
(vrndpq_x_f32): Remove.
(vrndaq_x_f16): Remove.
(vrndaq_x_f32): Remove.
(vrndxq_x_f16): Remove.
(vrndxq_x_f32): Remove.
(__arm_vrndxq_f16): Remove.
(__arm_vrndxq_f32): Remove.
(__arm_vrndq_f16): Remove.
(__arm_vrndq_f32): Remove.
(__arm_vrndpq_f16): Remove.
(__arm_vrndpq_f32): Remove.
(__arm_vrndnq_f16): Remove.
(__arm_vrndnq_f32): Remove.
(__arm_vrndmq_f16): Remove.
(__arm_vrndmq_f32): Remove.
(__arm_vrndaq_f16): Remove.
(__arm_vrndaq_f32): Remove.
(__arm_vrndaq_m_f16): Remove.
(__arm_vrndmq_m_f16): Remove.
(__arm_vrndnq_m_f16): Remove.
(__arm_vrndpq_m_f16): Remove.
(__arm_vrndq_m_f16): Remove.
(__arm_vrndxq_m_f16): Remove.
(__arm_vrndaq_m_f32): Remove.
(__arm_vrndmq_m_f32): Remove.
(__arm_vrndnq_m_f32): Remove.
(__arm_vrndpq_m_f32): Remove.
(__arm_vrndq_m_f32): Remove.
(__arm_vrndxq_m_f32): Remove.
(__arm_vrndq_x_f16): Remove.
(__arm_vrndq_x_f32): Remove.
(__arm_vrndnq_x_f16): Remove.
(__arm_vrndnq_x_f32): Remove.
(__arm_vrndmq_x_f16): Remove.
(__arm_vrndmq_x_f32): Remove.
(__arm_vrndpq_x_f16): Remove.
(__arm_vrndpq_x_f32): Remove.
(__arm_vrndaq_x_f16): Remove.
(__arm_vrndaq_x_f32): Remove.
(__arm_vrndxq_x_f16): Remove.
(__arm_vrndxq_x_f32): Remove.
(__arm_vrndxq): Remove.
(__arm_vrndq): Remove.
(__arm_vrndpq): Remove.
(__arm_vrndnq): Remove.
(__arm_vrndmq): Remove.
(__arm_vrndaq): Remove.
(__arm_vrndaq_m): Remove.
(__arm_vrndmq_m): Remove.
(__arm_vrndnq_m): Remove.
(__arm_vrndpq_m): Remove.
(__arm_vrndq_m): Remove.
(__arm_vrndxq_m): Remove.
(__arm_vrndq_x): Remove.
(__arm_vrndnq_x): Remove.
(__arm_vrndmq_x): Remove.
(__arm_vrndpq_x): Remove.
(__arm_vrndaq_x): Remove.
(__arm_vrndxq_x): Remove.
2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (FUNCTION_WITHOUT_N_NO_U_F): New.
(vabsq, vnegq, vclsq, vclzq, vqabsq, vqnegq): New.
* config/arm/arm-mve-builtins-base.def (vabsq, vnegq, vclsq)
(vclzq, vqabsq, vqnegq): New.
* config/arm/arm-mve-builtins-base.h (vabsq, vnegq, vclsq, vclzq)
(vqabsq, vqnegq): New.
* config/arm/arm_mve.h (vabsq): Remove.
(vabsq_m): Remove.
(vabsq_x): Remove.
(vabsq_f16): Remove.
(vabsq_f32): Remove.
(vabsq_s8): Remove.
(vabsq_s16): Remove.
(vabsq_s32): Remove.
(vabsq_m_s8): Remove.
(vabsq_m_s16): Remove.
(vabsq_m_s32): Remove.
(vabsq_m_f16): Remove.
(vabsq_m_f32): Remove.
(vabsq_x_s8): Remove.
(vabsq_x_s16): Remove.
(vabsq_x_s32): Remove.
(vabsq_x_f16): Remove.
(vabsq_x_f32): Remove.
(__arm_vabsq_s8): Remove.
(__arm_vabsq_s16): Remove.
(__arm_vabsq_s32): Remove.
(__arm_vabsq_m_s8): Remove.
(__arm_vabsq_m_s16): Remove.
(__arm_vabsq_m_s32): Remove.
(__arm_vabsq_x_s8): Remove.
(__arm_vabsq_x_s16): Remove.
(__arm_vabsq_x_s32): Remove.
(__arm_vabsq_f16): Remove.
(__arm_vabsq_f32): Remove.
(__arm_vabsq_m_f16): Remove.
(__arm_vabsq_m_f32): Remove.
(__arm_vabsq_x_f16): Remove.
(__arm_vabsq_x_f32): Remove.
(__arm_vabsq): Remove.
(__arm_vabsq_m): Remove.
(__arm_vabsq_x): Remove.
(vnegq): Remove.
(vnegq_m): Remove.
(vnegq_x): Remove.
(vnegq_f16): Remove.
(vnegq_f32): Remove.
(vnegq_s8): Remove.
(vnegq_s16): Remove.
(vnegq_s32): Remove.
(vnegq_m_s8): Remove.
(vnegq_m_s16): Remove.
(vnegq_m_s32): Remove.
(vnegq_m_f16): Remove.
(vnegq_m_f32): Remove.
(vnegq_x_s8): Remove.
(vnegq_x_s16): Remove.
(vnegq_x_s32): Remove.
(vnegq_x_f16): Remove.
(vnegq_x_f32): Remove.
(__arm_vnegq_s8): Remove.
(__arm_vnegq_s16): Remove.
(__arm_vnegq_s32): Remove.
(__arm_vnegq_m_s8): Remove.
(__arm_vnegq_m_s16): Remove.
(__arm_vnegq_m_s32): Remove.
(__arm_vnegq_x_s8): Remove.
(__arm_vnegq_x_s16): Remove.
(__arm_vnegq_x_s32): Remove.
(__arm_vnegq_f16): Remove.
(__arm_vnegq_f32): Remove.
(__arm_vnegq_m_f16): Remove.
(__arm_vnegq_m_f32): Remove.
(__arm_vnegq_x_f16): Remove.
(__arm_vnegq_x_f32): Remove.
(__arm_vnegq): Remove.
(__arm_vnegq_m): Remove.
(__arm_vnegq_x): Remove.
(vclsq): Remove.
(vclsq_m): Remove.
(vclsq_x): Remove.
(vclsq_s8): Remove.
(vclsq_s16): Remove.
(vclsq_s32): Remove.
(vclsq_m_s8): Remove.
(vclsq_m_s16): Remove.
(vclsq_m_s32): Remove.
(vclsq_x_s8): Remove.
(vclsq_x_s16): Remove.
(vclsq_x_s32): Remove.
(__arm_vclsq_s8): Remove.
(__arm_vclsq_s16): Remove.
(__arm_vclsq_s32): Remove.
(__arm_vclsq_m_s8): Remove.
(__arm_vclsq_m_s16): Remove.
(__arm_vclsq_m_s32): Remove.
(__arm_vclsq_x_s8): Remove.
(__arm_vclsq_x_s16): Remove.
(__arm_vclsq_x_s32): Remove.
(__arm_vclsq): Remove.
(__arm_vclsq_m): Remove.
(__arm_vclsq_x): Remove.
(vclzq): Remove.
(vclzq_m): Remove.
(vclzq_x): Remove.
(vclzq_s8): Remove.
(vclzq_s16): Remove.
(vclzq_s32): Remove.
(vclzq_u8): Remove.
(vclzq_u16): Remove.
(vclzq_u32): Remove.
(vclzq_m_u8): Remove.
(vclzq_m_s8): Remove.
(vclzq_m_u16): Remove.
(vclzq_m_s16): Remove.
(vclzq_m_u32): Remove.
(vclzq_m_s32): Remove.
(vclzq_x_s8): Remove.
(vclzq_x_s16): Remove.
(vclzq_x_s32): Remove.
(vclzq_x_u8): Remove.
(vclzq_x_u16): Remove.
(vclzq_x_u32): Remove.
(__arm_vclzq_s8): Remove.
(__arm_vclzq_s16): Remove.
(__arm_vclzq_s32): Remove.
(__arm_vclzq_u8): Remove.
(__arm_vclzq_u16): Remove.
(__arm_vclzq_u32): Remove.
(__arm_vclzq_m_u8): Remove.
(__arm_vclzq_m_s8): Remove.
(__arm_vclzq_m_u16): Remove.
(__arm_vclzq_m_s16): Remove.
(__arm_vclzq_m_u32): Remove.
(__arm_vclzq_m_s32): Remove.
(__arm_vclzq_x_s8): Remove.
(__arm_vclzq_x_s16): Remove.
(__arm_vclzq_x_s32): Remove.
(__arm_vclzq_x_u8): Remove.
(__arm_vclzq_x_u16): Remove.
(__arm_vclzq_x_u32): Remove.
(__arm_vclzq): Remove.
(__arm_vclzq_m): Remove.
(__arm_vclzq_x): Remove.
(vqabsq): Remove.
(vqnegq): Remove.
(vqnegq_m): Remove.
(vqabsq_m): Remove.
(vqabsq_s8): Remove.
(vqabsq_s16): Remove.
(vqabsq_s32): Remove.
(vqnegq_s8): Remove.
(vqnegq_s16): Remove.
(vqnegq_s32): Remove.
(vqnegq_m_s8): Remove.
(vqabsq_m_s8): Remove.
(vqnegq_m_s16): Remove.
(vqabsq_m_s16): Remove.
(vqnegq_m_s32): Remove.
(vqabsq_m_s32): Remove.
(__arm_vqabsq_s8): Remove.
(__arm_vqabsq_s16): Remove.
(__arm_vqabsq_s32): Remove.
(__arm_vqnegq_s8): Remove.
(__arm_vqnegq_s16): Remove.
(__arm_vqnegq_s32): Remove.
(__arm_vqnegq_m_s8): Remove.
(__arm_vqabsq_m_s8): Remove.
(__arm_vqnegq_m_s16): Remove.
(__arm_vqabsq_m_s16): Remove.
(__arm_vqnegq_m_s32): Remove.
(__arm_vqabsq_m_s32): Remove.
(__arm_vqabsq): Remove.
(__arm_vqnegq): Remove.
(__arm_vqnegq_m): Remove.
(__arm_vqabsq_m): Remove.
2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (MVE_INT_M_UNARY, MVE_INT_UNARY)
(MVE_FP_UNARY, MVE_FP_M_UNARY): New.
(mve_insn): Add vabs, vcls, vclz, vneg, vqabs, vqneg, vrnda,
vrndm, vrndn, vrndp, vrnd, vrndx.
(isu): Add VABSQ_M_S, VCLSQ_M_S, VCLZQ_M_S, VCLZQ_M_U, VNEGQ_M_S,
VQABSQ_M_S, VQNEGQ_M_S.
(mve_mnemo): New.
* config/arm/mve.md (mve_vrndq_m_f<mode>, mve_vrndxq_f<mode>)
(mve_vrndq_f<mode>, mve_vrndpq_f<mode>, mve_vrndnq_f<mode>)
(mve_vrndmq_f<mode>, mve_vrndaq_f<mode>): Merge into ...
(@mve_<mve_insn>q_f<mode>): ... this.
(mve_vnegq_f<mode>, mve_vabsq_f<mode>): Merge into ...
(mve_v<absneg_str>q_f<mode>): ... this.
(mve_vnegq_s<mode>, mve_vabsq_s<mode>): Merge into ...
(mve_v<absneg_str>q_s<mode>): ... this.
(mve_vclsq_s<mode>, mve_vqnegq_s<mode>, mve_vqabsq_s<mode>): Merge into ...
(@mve_<mve_insn>q_<supf><mode>): ... this.
(mve_vabsq_m_s<mode>, mve_vclsq_m_s<mode>)
(mve_vclzq_m_<supf><mode>, mve_vnegq_m_s<mode>)
(mve_vqabsq_m_s<mode>, mve_vqnegq_m_s<mode>): Merge into ...
(@mve_<mve_insn>q_m_<supf><mode>): ... this.
(mve_vabsq_m_f<mode>, mve_vnegq_m_f<mode>, mve_vrndaq_m_f<mode>)
(mve_vrndmq_m_f<mode>, mve_vrndnq_m_f<mode>, mve_vrndpq_m_f<mode>)
(mve_vrndxq_m_f<mode>): Merge into ...
(@mve_<mve_insn>q_m_f<mode>): ... this.
2023-05-09 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-shapes.cc (unary): New.
* config/arm/arm-mve-builtins-shapes.h (unary): New.
2023-05-09 Jakub Jelinek <jakub@redhat.com>
* mux-utils.h: Fix comment typo, avoides -> avoids.
2023-05-09 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/109778
* wide-int.h (wi::lrotate, wi::rrotate): Call wi::lrshift on
wi::zext (x, width) rather than x if width != precision, rather
than using wi::zext (right, width) after the shift.
* tree-ssa-ccp.cc (bit_value_binop): Call wi::ext on the results
of wi::lrotate or wi::rrotate.
2023-05-09 Alexander Monakov <amonakov@ispras.ru>
* genmatch.cc (get_out_file): Make static and rename to ...
(choose_output): ... this. Reimplement. Update all uses ...
(decision_tree::gen): ... here and ...
(main): ... here.
2023-05-09 Alexander Monakov <amonakov@ispras.ru>
* genmatch.cc (showUsage): Reimplement as ...
(usage): ...this. Adjust all uses.
(main): Print usage when no arguments. Add missing 'return 1'.
2023-05-09 Alexander Monakov <amonakov@ispras.ru>
* genmatch.cc (header_file): Make static.
(emit_func): Rename to...
(fp_decl): ... this. Adjust all uses.
(fp_decl_done): New function. Use it...
(decision_tree::gen): ... here and...
(write_predicate): ... here.
(main): Adjust.
2023-05-09 Richard Sandiford <richard.sandiford@arm.com>
* ira-conflicts.cc (can_use_same_reg_p): Skip over non-matching
earlyclobbers.
2023-05-08 Roger Sayle <roger@nextmovesoftware.com>
Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (any_or_plus): Move definition earlier.
(*insvti_highpart_1): New define_insn_and_split to overwrite
(insv) the highpart of a TImode register/memory.
2023-05-08 Eugene Rozenfeld <erozen@microsoft.com>
* auto-profile.cc (auto_profile): Check todo from early_inline
to see if cleanup_tree_vfg needs to be called.
(early_inline): Return todo from early_inliner.
2023-05-08 Kito Cheng <kito.cheng@sifive.com>
* config/riscv/riscv-vsetvl.cc (pass_vsetvl::get_vector_info):
New.
(pass_vsetvl::get_block_info): New.
(pass_vsetvl::update_vector_info): New.
(pass_vsetvl::simple_vsetvl): Use get_vector_info.
(pass_vsetvl::compute_local_backward_infos): Ditto.
(pass_vsetvl::transfer_before): Ditto.
(pass_vsetvl::transfer_after): Ditto.
(pass_vsetvl::emit_local_forward_vsetvls): Ditto.
(pass_vsetvl::local_eliminate_vsetvl_insn): Ditto.
(pass_vsetvl::cleanup_insns): Ditto.
(pass_vsetvl::compute_local_backward_infos): Use
update_vector_info.
2023-05-08 Jeff Law <jlaw@ventanamicro>
* config/stormy16/stormy16.md (zero_extendhisi2): Fix length.
2023-05-08 Richard Biener <rguenther@suse.de>
Michael Meissner <meissner@linux.ibm.com>
PR middle-end/108623
* tree-core.h (tree_type_common): Bump up precision field to 16 bits.
Align bit fields > 1 bit to at least an 8-bit boundary.
2023-05-08 Andrew Pinski <apinski@marvell.com>
PR tree-optimization/109424
PR tree-optimization/59424
* tree-ssa-phiopt.cc (factor_out_conditional_conversion): Rename to ...
(factor_out_conditional_operation): This and add support for all unary
operations.
(pass_phiopt::execute): Update call to factor_out_conditional_conversion
to call factor_out_conditional_operation instead.
2023-05-08 Andrew Pinski <apinski@marvell.com>
* tree-ssa-phiopt.cc (pass_phiopt::execute): Loop
over factor_out_conditional_conversion.
2023-05-08 Andrew Pinski <apinski@marvell.com>
PR tree-optimization/49959
PR tree-optimization/103771
* tree-ssa-phiopt.cc (pass_phiopt::execute): Support
Diamond shapped bb form for factor_out_conditional_conversion.
2023-05-08 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/autovec.md (movmisalign<mode>): New pattern.
* config/riscv/riscv-protos.h (riscv_vector_mask_mode_p): Delete.
(riscv_vector_get_mask_mode): Ditto.
(get_mask_policy_no_pred): Ditto.
(get_tail_policy_no_pred): Ditto.
(get_mask_mode): New function.
* config/riscv/riscv-v.cc (get_mask_policy_no_pred): Delete.
(get_tail_policy_no_pred): Ditto.
(riscv_vector_mask_mode_p): Ditto.
(riscv_vector_get_mask_mode): Ditto.
(get_mask_mode): New function.
* config/riscv/riscv-vector-builtins.cc (use_real_merge_p): Remove
global extern.
(get_tail_policy_for_pred): Ditto.
* config/riscv/riscv-vector-builtins.h (get_tail_policy_for_pred): Ditto.
(get_mask_policy_for_pred): Ditto
* config/riscv/riscv.cc (riscv_get_mask_mode): Refine codes.
2023-05-08 Kito Cheng <kito.cheng@sifive.com>
* common/config/riscv/riscv-common.cc (riscv_select_multilib_by_abi): New.
(riscv_select_multilib): New.
(riscv_compute_multilib): Extract logic to riscv_select_multilib and
also handle select_by_abi.
* config/riscv/elf.h (RISCV_USE_CUSTOMISED_MULTI_LIB): Change it
to select_by_abi_arch_cmodel from 1.
* config/riscv/linux.h (RISCV_USE_CUSTOMISED_MULTI_LIB): Define.
* config/riscv/riscv-opts.h (enum riscv_multilib_select_kind): New.
2023-05-08 Alexander Monakov <amonakov@ispras.ru>
* Makefile.in: (gimple-match-head.o-warn): Remove.
(GIMPLE_MATCH_PD_SEQ_SRC): Do not depend on
gimple-match-exports.cc.
(gimple-match-auto.h): Only depend on s-gimple-match.
(generic-match-auto.h): Likewise.
2023-05-08 Andrew Pinski <apinski@marvell.com>
PR tree-optimization/109691
* tree-ssa-dce.cc (simple_dce_from_worklist): Add need_eh_cleanup
argument.
If the removed statement can throw, have need_eh_cleanup
include the bb of that statement.
* tree-ssa-dce.h (simple_dce_from_worklist): Update declaration.
* tree-ssa-propagate.cc (struct prop_stats_d): Remove
num_dce.
(substitute_and_fold_dom_walker::substitute_and_fold_dom_walker):
Initialize dceworklist instead of stmts_to_remove.
(substitute_and_fold_dom_walker::~substitute_and_fold_dom_walker):
Destore dceworklist instead of stmts_to_remove.
(substitute_and_fold_dom_walker::before_dom_children):
Set dceworklist instead of adding to stmts_to_remove.
(substitute_and_fold_engine::substitute_and_fold):
Call simple_dce_from_worklist instead of poping
from the list.
Don't update the stat on removal statements.
2023-05-07 Andrew Pinski <apinski@marvell.com>
PR target/109762
* config/aarch64/aarch64-builtins.cc (aarch64_simd_switcher::aarch64_simd_switcher):
Change argument type to aarch64_feature_flags.
* config/aarch64/aarch64-protos.h (aarch64_simd_switcher): Change
constructor argument type to aarch64_feature_flags.
Change m_old_asm_isa_flags to be aarch64_feature_flags.
2023-05-07 Jiufu Guo <guojiufu@linux.ibm.com>
* config/rs6000/rs6000.cc (rs6000_emit_set_long_const): Generate
more parallel code if can_create_pseudo_p.
2023-05-07 Roger Sayle <roger@nextmovesoftware.com>
PR target/43644
* lower-subreg.cc (resolve_simple_move): Don't emit a clobber
immediately before moving a multi-word register by parts.
2023-05-06 Jeff Law <jlaw@ventanamicro>
* config/riscv/riscv-v.cc (riscv_vector_preferred_simd_mode): Delete.
2023-05-06 Michael Collison <collison@rivosinc.com>
* tree-vect-slp.cc (can_duplicate_and_interleave_p):
Check that GET_MODE_NUNITS is a multiple of 2.
2023-05-06 Michael Collison <collison@rivosinc.com>
* config/riscv/riscv.cc
(riscv_estimated_poly_value): Implement
TARGET_ESTIMATED_POLY_VALUE.
(riscv_preferred_simd_mode): Implement
TARGET_VECTORIZE_PREFERRED_SIMD_MODE.
(riscv_get_mask_mode): Implement TARGET_VECTORIZE_GET_MASK_MODE.
(riscv_empty_mask_is_expensive): Implement
TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE.
(riscv_vectorize_create_costs): Implement
TARGET_VECTORIZE_CREATE_COSTS.
(riscv_support_vector_misalignment): Implement
TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT.
(TARGET_ESTIMATED_POLY_VALUE): Register target macro.
(TARGET_VECTORIZE_GET_MASK_MODE): Ditto.
(TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE): Ditto.
(TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT): Ditto.
2023-05-06 Jeff Law <jlaw@ventanamicro>
* config/riscv/riscv-v.cc (autovec_use_vlmax_p): Remove
duplicate definition.
2023-05-06 Michael Collison <collison@rivosinc.com>
* config/riscv/riscv-v.cc (autovec_use_vlmax_p): New function.
(riscv_vector_preferred_simd_mode): Ditto.
(get_mask_policy_no_pred): Ditto.
(get_tail_policy_no_pred): Ditto.
(riscv_vector_mask_mode_p): Ditto.
(riscv_vector_get_mask_mode): Ditto.
2023-05-06 Michael Collison <collison@rivosinc.com>
* config/riscv/riscv-vector-builtins.cc (get_tail_policy_for_pred):
Remove static declaration to to make externally visible.
(get_mask_policy_for_pred): Ditto.
* config/riscv/riscv-vector-builtins.h (get_tail_policy_for_pred):
New external declaration.
(get_mask_policy_for_pred): Ditto.
2023-05-06 Michael Collison <collison@rivosinc.com>
* config/riscv/riscv-protos.h (riscv_vector_mask_mode_p): New.
(riscv_vector_get_mask_mode): Ditto.
(get_mask_policy_no_pred): Ditto.
(get_tail_policy_no_pred): Ditto.
2023-05-06 Xi Ruoyao <xry111@xry111.site>
* config/loongarch/loongarch.h (struct machine_function): Add
reg_is_wrapped_separately array for register wrapping
information.
* config/loongarch/loongarch.cc
(loongarch_get_separate_components): New function.
(loongarch_components_for_bb): Likewise.
(loongarch_disqualify_components): Likewise.
(loongarch_process_components): Likewise.
(loongarch_emit_prologue_components): Likewise.
(loongarch_emit_epilogue_components): Likewise.
(loongarch_set_handled_components): Likewise.
(TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS): Define.
(TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB): Likewise.
(TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS): Likewise.
(TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS): Likewise.
(TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS): Likewise.
(TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS): Likewise.
(loongarch_for_each_saved_reg): Skip registers that are wrapped
separately.
2023-05-06 Xi Ruoyao <xry111@xry111.site>
PR other/109522
* Makefile.in (s-macro_list): Pass -nostdinc to
$(GCC_FOR_TARGET).
2023-05-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-protos.h (preferred_simd_mode): New function.
* config/riscv/riscv-v.cc (autovec_use_vlmax_p): Ditto.
(preferred_simd_mode): Ditto.
* config/riscv/riscv.cc (riscv_get_arg_info): Handle RVV type in function arg.
(riscv_convert_vector_bits): Adjust for RVV auto-vectorization.
(riscv_preferred_simd_mode): New function.
(TARGET_VECTORIZE_PREFERRED_SIMD_MODE): New target hook support.
* config/riscv/vector.md: Add autovec.md.
* config/riscv/autovec.md: New file.
2023-05-06 Jakub Jelinek <jakub@redhat.com>
* real.h (dconst_pi): Define.
(dconst_e_ptr): Formatting fix.
(dconst_pi_ptr): Declare.
* real.cc (dconst_pi_ptr): New function.
* gimple-range-op.cc (cfn_sincos::fold_range): Intersect the generic
boundaries range with range computed from sin/cos of the particular
bounds if the argument range is shorter than 2*pi.
(cfn_sincos::op1_range): Take bulps into account when determining
which result ranges are always invalid or behave like known NAN.
2023-05-06 Aldy Hernandez <aldyh@redhat.com>
* gimple-range-cache.cc (sbr_sparse_bitmap::set_bb_range): Do not
pass type to vrange_storage::equal_p.
* value-range-storage.cc (vrange_storage::equal_p): Remove type.
(irange_storage::equal_p): Same.
(frange_storage::equal_p): Same.
* value-range-storage.h (class frange_storage): Same.
2023-05-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
PR target/109748
* config/riscv/riscv-vsetvl.cc (local_eliminate_vsetvl_insn): Remove it.
(pass_vsetvl::local_eliminate_vsetvl_insn): New function.
2023-05-06 liuhongt <hongtao.liu@intel.com>
* combine.cc (maybe_swap_commutative_operands): Canonicalize
vec_merge when mask is constant.
* doc/md.texi: Document vec_merge canonicalization.
2023-05-06 Jakub Jelinek <jakub@redhat.com>
* value-range.h (frange_arithmetic): Declare.
* range-op-float.cc (frange_arithmetic): No longer static.
* gimple-range-op.cc (frange_mpfr_arg1): New function.
(cfn_sqrt::fold_range): Intersect the generic boundaries range
with range computed from sqrt of the particular bounds.
(cfn_sqrt::op1_range): Intersect the generic boundaries range
with range computed from squared particular bounds.
2023-05-06 Jakub Jelinek <jakub@redhat.com>
* Makefile.in (check_p_numbers): Rename to one_to_9999, move
earlier with helper variables also renamed.
(MATCH_SPLUT_SEQ): Use $(wordlist 1,$(NUM_MATCH_SPLITS),$(one_to_9999))
instead of $(shell seq 1 $(NUM_MATCH_SPLITS)).
(check_p_subdirs): Use $(one_to_9999) instead of $(check_p_numbers).
2023-05-06 Hans-Peter Nilsson <hp@axis.com>
* config/cris/cris.md (splitop): Add PLUS.
* config/cris/cris.cc (cris_split_constant): Also handle
PLUS when a split into two insns may be useful.
2023-05-05 Hans-Peter Nilsson <hp@axis.com>
* config/cris/cris.md (movandsplit1): New define_peephole2.
2023-05-05 Hans-Peter Nilsson <hp@axis.com>
* config/cris/cris.md (lsrandsplit1): New define_peephole2.
2023-05-05 Hans-Peter Nilsson <hp@axis.com>
* doc/md.texi (define_peephole2): Document order of scanning.
2023-05-05 Pan Li <pan2.li@intel.com>
Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/vector.md: Allow const as the operand of RVV
indexed load/store.
2023-05-05 Pan Li <pan2.li@intel.com>
* config/riscv/riscv.h (VECTOR_STORE_FLAG_VALUE): Add new macro
consumed by simplify_rtx.
2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (vrshrq, vshrq): New.
* config/arm/arm-mve-builtins-base.def (vrshrq, vshrq): New.
* config/arm/arm-mve-builtins-base.h (vrshrq, vshrq): New.
* config/arm/arm_mve.h (vshrq): Remove.
(vrshrq): Remove.
(vrshrq_m): Remove.
(vshrq_m): Remove.
(vrshrq_x): Remove.
(vshrq_x): Remove.
(vshrq_n_s8): Remove.
(vshrq_n_s16): Remove.
(vshrq_n_s32): Remove.
(vshrq_n_u8): Remove.
(vshrq_n_u16): Remove.
(vshrq_n_u32): Remove.
(vrshrq_n_u8): Remove.
(vrshrq_n_s8): Remove.
(vrshrq_n_u16): Remove.
(vrshrq_n_s16): Remove.
(vrshrq_n_u32): Remove.
(vrshrq_n_s32): Remove.
(vrshrq_m_n_s8): Remove.
(vrshrq_m_n_s32): Remove.
(vrshrq_m_n_s16): Remove.
(vrshrq_m_n_u8): Remove.
(vrshrq_m_n_u32): Remove.
(vrshrq_m_n_u16): Remove.
(vshrq_m_n_s8): Remove.
(vshrq_m_n_s32): Remove.
(vshrq_m_n_s16): Remove.
(vshrq_m_n_u8): Remove.
(vshrq_m_n_u32): Remove.
(vshrq_m_n_u16): Remove.
(vrshrq_x_n_s8): Remove.
(vrshrq_x_n_s16): Remove.
(vrshrq_x_n_s32): Remove.
(vrshrq_x_n_u8): Remove.
(vrshrq_x_n_u16): Remove.
(vrshrq_x_n_u32): Remove.
(vshrq_x_n_s8): Remove.
(vshrq_x_n_s16): Remove.
(vshrq_x_n_s32): Remove.
(vshrq_x_n_u8): Remove.
(vshrq_x_n_u16): Remove.
(vshrq_x_n_u32): Remove.
(__arm_vshrq_n_s8): Remove.
(__arm_vshrq_n_s16): Remove.
(__arm_vshrq_n_s32): Remove.
(__arm_vshrq_n_u8): Remove.
(__arm_vshrq_n_u16): Remove.
(__arm_vshrq_n_u32): Remove.
(__arm_vrshrq_n_u8): Remove.
(__arm_vrshrq_n_s8): Remove.
(__arm_vrshrq_n_u16): Remove.
(__arm_vrshrq_n_s16): Remove.
(__arm_vrshrq_n_u32): Remove.
(__arm_vrshrq_n_s32): Remove.
(__arm_vrshrq_m_n_s8): Remove.
(__arm_vrshrq_m_n_s32): Remove.
(__arm_vrshrq_m_n_s16): Remove.
(__arm_vrshrq_m_n_u8): Remove.
(__arm_vrshrq_m_n_u32): Remove.
(__arm_vrshrq_m_n_u16): Remove.
(__arm_vshrq_m_n_s8): Remove.
(__arm_vshrq_m_n_s32): Remove.
(__arm_vshrq_m_n_s16): Remove.
(__arm_vshrq_m_n_u8): Remove.
(__arm_vshrq_m_n_u32): Remove.
(__arm_vshrq_m_n_u16): Remove.
(__arm_vrshrq_x_n_s8): Remove.
(__arm_vrshrq_x_n_s16): Remove.
(__arm_vrshrq_x_n_s32): Remove.
(__arm_vrshrq_x_n_u8): Remove.
(__arm_vrshrq_x_n_u16): Remove.
(__arm_vrshrq_x_n_u32): Remove.
(__arm_vshrq_x_n_s8): Remove.
(__arm_vshrq_x_n_s16): Remove.
(__arm_vshrq_x_n_s32): Remove.
(__arm_vshrq_x_n_u8): Remove.
(__arm_vshrq_x_n_u16): Remove.
(__arm_vshrq_x_n_u32): Remove.
(__arm_vshrq): Remove.
(__arm_vrshrq): Remove.
(__arm_vrshrq_m): Remove.
(__arm_vshrq_m): Remove.
(__arm_vrshrq_x): Remove.
(__arm_vshrq_x): Remove.
2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (MVE_VSHRQ_M_N, MVE_VSHRQ_N): New.
(mve_insn): Add vrshr, vshr.
* config/arm/mve.md (mve_vshrq_n_<supf><mode>)
(mve_vrshrq_n_<supf><mode>): Merge into ...
(@mve_<mve_insn>q_n_<supf><mode>): ... this.
(mve_vrshrq_m_n_<supf><mode>, mve_vshrq_m_n_<supf><mode>): Merge
into ...
(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-shapes.cc (binary_rshift): New.
* config/arm/arm-mve-builtins-shapes.h (binary_rshift): New.
2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (FUNCTION_ONLY_N_NO_U_F): New.
(vqshrunbq, vqshruntq, vqrshrunbq, vqrshruntq): New.
* config/arm/arm-mve-builtins-base.def (vqshrunbq, vqshruntq)
(vqrshrunbq, vqrshruntq): New.
* config/arm/arm-mve-builtins-base.h (vqshrunbq, vqshruntq)
(vqrshrunbq, vqrshruntq): New.
* config/arm/arm-mve-builtins.cc
(function_instance::has_inactive_argument): Handle vqshrunbq,
vqshruntq, vqrshrunbq, vqrshruntq.
* config/arm/arm_mve.h (vqrshrunbq): Remove.
(vqrshruntq): Remove.
(vqrshrunbq_m): Remove.
(vqrshruntq_m): Remove.
(vqrshrunbq_n_s16): Remove.
(vqrshrunbq_n_s32): Remove.
(vqrshruntq_n_s16): Remove.
(vqrshruntq_n_s32): Remove.
(vqrshrunbq_m_n_s32): Remove.
(vqrshrunbq_m_n_s16): Remove.
(vqrshruntq_m_n_s32): Remove.
(vqrshruntq_m_n_s16): Remove.
(__arm_vqrshrunbq_n_s16): Remove.
(__arm_vqrshrunbq_n_s32): Remove.
(__arm_vqrshruntq_n_s16): Remove.
(__arm_vqrshruntq_n_s32): Remove.
(__arm_vqrshrunbq_m_n_s32): Remove.
(__arm_vqrshrunbq_m_n_s16): Remove.
(__arm_vqrshruntq_m_n_s32): Remove.
(__arm_vqrshruntq_m_n_s16): Remove.
(__arm_vqrshrunbq): Remove.
(__arm_vqrshruntq): Remove.
(__arm_vqrshrunbq_m): Remove.
(__arm_vqrshruntq_m): Remove.
(vqshrunbq): Remove.
(vqshruntq): Remove.
(vqshrunbq_m): Remove.
(vqshruntq_m): Remove.
(vqshrunbq_n_s16): Remove.
(vqshruntq_n_s16): Remove.
(vqshrunbq_n_s32): Remove.
(vqshruntq_n_s32): Remove.
(vqshrunbq_m_n_s32): Remove.
(vqshrunbq_m_n_s16): Remove.
(vqshruntq_m_n_s32): Remove.
(vqshruntq_m_n_s16): Remove.
(__arm_vqshrunbq_n_s16): Remove.
(__arm_vqshruntq_n_s16): Remove.
(__arm_vqshrunbq_n_s32): Remove.
(__arm_vqshruntq_n_s32): Remove.
(__arm_vqshrunbq_m_n_s32): Remove.
(__arm_vqshrunbq_m_n_s16): Remove.
(__arm_vqshruntq_m_n_s32): Remove.
(__arm_vqshruntq_m_n_s16): Remove.
(__arm_vqshrunbq): Remove.
(__arm_vqshruntq): Remove.
(__arm_vqshrunbq_m): Remove.
(__arm_vqshruntq_m): Remove.
2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (MVE_SHRN_N): Add VQRSHRUNBQ,
VQRSHRUNTQ, VQSHRUNBQ, VQSHRUNTQ.
(MVE_SHRN_M_N): Likewise.
(mve_insn): Add vqrshrunb, vqrshrunt, vqshrunb, vqshrunt.
(isu): Add VQRSHRUNBQ, VQRSHRUNTQ, VQSHRUNBQ, VQSHRUNTQ.
(supf): Likewise.
* config/arm/mve.md (mve_vqrshrunbq_n_s<mode>): Remove.
(mve_vqrshruntq_n_s<mode>): Remove.
(mve_vqshrunbq_n_s<mode>): Remove.
(mve_vqshruntq_n_s<mode>): Remove.
(mve_vqrshrunbq_m_n_s<mode>): Remove.
(mve_vqrshruntq_m_n_s<mode>): Remove.
(mve_vqshrunbq_m_n_s<mode>): Remove.
(mve_vqshruntq_m_n_s<mode>): Remove.
2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-shapes.cc
(binary_rshift_narrow_unsigned): New.
* config/arm/arm-mve-builtins-shapes.h
(binary_rshift_narrow_unsigned): New.
2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (FUNCTION_ONLY_N_NO_F): New.
(vshrnbq, vshrntq, vrshrnbq, vrshrntq, vqshrnbq, vqshrntq)
(vqrshrnbq, vqrshrntq): New.
* config/arm/arm-mve-builtins-base.def (vshrnbq, vshrntq)
(vrshrnbq, vrshrntq, vqshrnbq, vqshrntq, vqrshrnbq, vqrshrntq):
New.
* config/arm/arm-mve-builtins-base.h (vshrnbq, vshrntq, vrshrnbq)
(vrshrntq, vqshrnbq, vqshrntq, vqrshrnbq, vqrshrntq): New.
* config/arm/arm-mve-builtins.cc
(function_instance::has_inactive_argument): Handle vshrnbq,
vshrntq, vrshrnbq, vrshrntq, vqshrnbq, vqshrntq, vqrshrnbq,
vqrshrntq.
* config/arm/arm_mve.h (vshrnbq): Remove.
(vshrntq): Remove.
(vshrnbq_m): Remove.
(vshrntq_m): Remove.
(vshrnbq_n_s16): Remove.
(vshrntq_n_s16): Remove.
(vshrnbq_n_u16): Remove.
(vshrntq_n_u16): Remove.
(vshrnbq_n_s32): Remove.
(vshrntq_n_s32): Remove.
(vshrnbq_n_u32): Remove.
(vshrntq_n_u32): Remove.
(vshrnbq_m_n_s32): Remove.
(vshrnbq_m_n_s16): Remove.
(vshrnbq_m_n_u32): Remove.
(vshrnbq_m_n_u16): Remove.
(vshrntq_m_n_s32): Remove.
(vshrntq_m_n_s16): Remove.
(vshrntq_m_n_u32): Remove.
(vshrntq_m_n_u16): Remove.
(__arm_vshrnbq_n_s16): Remove.
(__arm_vshrntq_n_s16): Remove.
(__arm_vshrnbq_n_u16): Remove.
(__arm_vshrntq_n_u16): Remove.
(__arm_vshrnbq_n_s32): Remove.
(__arm_vshrntq_n_s32): Remove.
(__arm_vshrnbq_n_u32): Remove.
(__arm_vshrntq_n_u32): Remove.
(__arm_vshrnbq_m_n_s32): Remove.
(__arm_vshrnbq_m_n_s16): Remove.
(__arm_vshrnbq_m_n_u32): Remove.
(__arm_vshrnbq_m_n_u16): Remove.
(__arm_vshrntq_m_n_s32): Remove.
(__arm_vshrntq_m_n_s16): Remove.
(__arm_vshrntq_m_n_u32): Remove.
(__arm_vshrntq_m_n_u16): Remove.
(__arm_vshrnbq): Remove.
(__arm_vshrntq): Remove.
(__arm_vshrnbq_m): Remove.
(__arm_vshrntq_m): Remove.
(vrshrnbq): Remove.
(vrshrntq): Remove.
(vrshrnbq_m): Remove.
(vrshrntq_m): Remove.
(vrshrnbq_n_s16): Remove.
(vrshrntq_n_s16): Remove.
(vrshrnbq_n_u16): Remove.
(vrshrntq_n_u16): Remove.
(vrshrnbq_n_s32): Remove.
(vrshrntq_n_s32): Remove.
(vrshrnbq_n_u32): Remove.
(vrshrntq_n_u32): Remove.
(vrshrnbq_m_n_s32): Remove.
(vrshrnbq_m_n_s16): Remove.
(vrshrnbq_m_n_u32): Remove.
(vrshrnbq_m_n_u16): Remove.
(vrshrntq_m_n_s32): Remove.
(vrshrntq_m_n_s16): Remove.
(vrshrntq_m_n_u32): Remove.
(vrshrntq_m_n_u16): Remove.
(__arm_vrshrnbq_n_s16): Remove.
(__arm_vrshrntq_n_s16): Remove.
(__arm_vrshrnbq_n_u16): Remove.
(__arm_vrshrntq_n_u16): Remove.
(__arm_vrshrnbq_n_s32): Remove.
(__arm_vrshrntq_n_s32): Remove.
(__arm_vrshrnbq_n_u32): Remove.
(__arm_vrshrntq_n_u32): Remove.
(__arm_vrshrnbq_m_n_s32): Remove.
(__arm_vrshrnbq_m_n_s16): Remove.
(__arm_vrshrnbq_m_n_u32): Remove.
(__arm_vrshrnbq_m_n_u16): Remove.
(__arm_vrshrntq_m_n_s32): Remove.
(__arm_vrshrntq_m_n_s16): Remove.
(__arm_vrshrntq_m_n_u32): Remove.
(__arm_vrshrntq_m_n_u16): Remove.
(__arm_vrshrnbq): Remove.
(__arm_vrshrntq): Remove.
(__arm_vrshrnbq_m): Remove.
(__arm_vrshrntq_m): Remove.
(vqshrnbq): Remove.
(vqshrntq): Remove.
(vqshrnbq_m): Remove.
(vqshrntq_m): Remove.
(vqshrnbq_n_s16): Remove.
(vqshrntq_n_s16): Remove.
(vqshrnbq_n_u16): Remove.
(vqshrntq_n_u16): Remove.
(vqshrnbq_n_s32): Remove.
(vqshrntq_n_s32): Remove.
(vqshrnbq_n_u32): Remove.
(vqshrntq_n_u32): Remove.
(vqshrnbq_m_n_s32): Remove.
(vqshrnbq_m_n_s16): Remove.
(vqshrnbq_m_n_u32): Remove.
(vqshrnbq_m_n_u16): Remove.
(vqshrntq_m_n_s32): Remove.
(vqshrntq_m_n_s16): Remove.
(vqshrntq_m_n_u32): Remove.
(vqshrntq_m_n_u16): Remove.
(__arm_vqshrnbq_n_s16): Remove.
(__arm_vqshrntq_n_s16): Remove.
(__arm_vqshrnbq_n_u16): Remove.
(__arm_vqshrntq_n_u16): Remove.
(__arm_vqshrnbq_n_s32): Remove.
(__arm_vqshrntq_n_s32): Remove.
(__arm_vqshrnbq_n_u32): Remove.
(__arm_vqshrntq_n_u32): Remove.
(__arm_vqshrnbq_m_n_s32): Remove.
(__arm_vqshrnbq_m_n_s16): Remove.
(__arm_vqshrnbq_m_n_u32): Remove.
(__arm_vqshrnbq_m_n_u16): Remove.
(__arm_vqshrntq_m_n_s32): Remove.
(__arm_vqshrntq_m_n_s16): Remove.
(__arm_vqshrntq_m_n_u32): Remove.
(__arm_vqshrntq_m_n_u16): Remove.
(__arm_vqshrnbq): Remove.
(__arm_vqshrntq): Remove.
(__arm_vqshrnbq_m): Remove.
(__arm_vqshrntq_m): Remove.
(vqrshrnbq): Remove.
(vqrshrntq): Remove.
(vqrshrnbq_m): Remove.
(vqrshrntq_m): Remove.
(vqrshrnbq_n_s16): Remove.
(vqrshrnbq_n_u16): Remove.
(vqrshrnbq_n_s32): Remove.
(vqrshrnbq_n_u32): Remove.
(vqrshrntq_n_s16): Remove.
(vqrshrntq_n_u16): Remove.
(vqrshrntq_n_s32): Remove.
(vqrshrntq_n_u32): Remove.
(vqrshrnbq_m_n_s32): Remove.
(vqrshrnbq_m_n_s16): Remove.
(vqrshrnbq_m_n_u32): Remove.
(vqrshrnbq_m_n_u16): Remove.
(vqrshrntq_m_n_s32): Remove.
(vqrshrntq_m_n_s16): Remove.
(vqrshrntq_m_n_u32): Remove.
(vqrshrntq_m_n_u16): Remove.
(__arm_vqrshrnbq_n_s16): Remove.
(__arm_vqrshrnbq_n_u16): Remove.
(__arm_vqrshrnbq_n_s32): Remove.
(__arm_vqrshrnbq_n_u32): Remove.
(__arm_vqrshrntq_n_s16): Remove.
(__arm_vqrshrntq_n_u16): Remove.
(__arm_vqrshrntq_n_s32): Remove.
(__arm_vqrshrntq_n_u32): Remove.
(__arm_vqrshrnbq_m_n_s32): Remove.
(__arm_vqrshrnbq_m_n_s16): Remove.
(__arm_vqrshrnbq_m_n_u32): Remove.
(__arm_vqrshrnbq_m_n_u16): Remove.
(__arm_vqrshrntq_m_n_s32): Remove.
(__arm_vqrshrntq_m_n_s16): Remove.
(__arm_vqrshrntq_m_n_u32): Remove.
(__arm_vqrshrntq_m_n_u16): Remove.
(__arm_vqrshrnbq): Remove.
(__arm_vqrshrntq): Remove.
(__arm_vqrshrnbq_m): Remove.
(__arm_vqrshrntq_m): Remove.
2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (MVE_SHRN_N, MVE_SHRN_M_N): New.
(mve_insn): Add vqrshrnb, vqrshrnt, vqshrnb, vqshrnt, vrshrnb,
vrshrnt, vshrnb, vshrnt.
(isu): New.
* config/arm/mve.md (mve_vqrshrnbq_n_<supf><mode>)
(mve_vqrshrntq_n_<supf><mode>, mve_vqshrnbq_n_<supf><mode>)
(mve_vqshrntq_n_<supf><mode>, mve_vrshrnbq_n_<supf><mode>)
(mve_vrshrntq_n_<supf><mode>, mve_vshrnbq_n_<supf><mode>)
(mve_vshrntq_n_<supf><mode>): Merge into ...
(@mve_<mve_insn>q_n_<supf><mode>): ... this.
(mve_vqrshrnbq_m_n_<supf><mode>, mve_vqrshrntq_m_n_<supf><mode>)
(mve_vqshrnbq_m_n_<supf><mode>, mve_vqshrntq_m_n_<supf><mode>)
(mve_vrshrnbq_m_n_<supf><mode>, mve_vrshrntq_m_n_<supf><mode>)
(mve_vshrnbq_m_n_<supf><mode>, mve_vshrntq_m_n_<supf><mode>):
Merge into ...
(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-shapes.cc (binary_rshift_narrow):
New.
* config/arm/arm-mve-builtins-shapes.h (binary_rshift_narrow): New.
2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (FUNCTION_WITH_RTX_M_NO_F): New.
(vmaxq, vminq): New.
* config/arm/arm-mve-builtins-base.def (vmaxq, vminq): New.
* config/arm/arm-mve-builtins-base.h (vmaxq, vminq): New.
* config/arm/arm_mve.h (vminq): Remove.
(vmaxq): Remove.
(vmaxq_m): Remove.
(vminq_m): Remove.
(vminq_x): Remove.
(vmaxq_x): Remove.
(vminq_u8): Remove.
(vmaxq_u8): Remove.
(vminq_s8): Remove.
(vmaxq_s8): Remove.
(vminq_u16): Remove.
(vmaxq_u16): Remove.
(vminq_s16): Remove.
(vmaxq_s16): Remove.
(vminq_u32): Remove.
(vmaxq_u32): Remove.
(vminq_s32): Remove.
(vmaxq_s32): Remove.
(vmaxq_m_s8): Remove.
(vmaxq_m_s32): Remove.
(vmaxq_m_s16): Remove.
(vmaxq_m_u8): Remove.
(vmaxq_m_u32): Remove.
(vmaxq_m_u16): Remove.
(vminq_m_s8): Remove.
(vminq_m_s32): Remove.
(vminq_m_s16): Remove.
(vminq_m_u8): Remove.
(vminq_m_u32): Remove.
(vminq_m_u16): Remove.
(vminq_x_s8): Remove.
(vminq_x_s16): Remove.
(vminq_x_s32): Remove.
(vminq_x_u8): Remove.
(vminq_x_u16): Remove.
(vminq_x_u32): Remove.
(vmaxq_x_s8): Remove.
(vmaxq_x_s16): Remove.
(vmaxq_x_s32): Remove.
(vmaxq_x_u8): Remove.
(vmaxq_x_u16): Remove.
(vmaxq_x_u32): Remove.
(__arm_vminq_u8): Remove.
(__arm_vmaxq_u8): Remove.
(__arm_vminq_s8): Remove.
(__arm_vmaxq_s8): Remove.
(__arm_vminq_u16): Remove.
(__arm_vmaxq_u16): Remove.
(__arm_vminq_s16): Remove.
(__arm_vmaxq_s16): Remove.
(__arm_vminq_u32): Remove.
(__arm_vmaxq_u32): Remove.
(__arm_vminq_s32): Remove.
(__arm_vmaxq_s32): Remove.
(__arm_vmaxq_m_s8): Remove.
(__arm_vmaxq_m_s32): Remove.
(__arm_vmaxq_m_s16): Remove.
(__arm_vmaxq_m_u8): Remove.
(__arm_vmaxq_m_u32): Remove.
(__arm_vmaxq_m_u16): Remove.
(__arm_vminq_m_s8): Remove.
(__arm_vminq_m_s32): Remove.
(__arm_vminq_m_s16): Remove.
(__arm_vminq_m_u8): Remove.
(__arm_vminq_m_u32): Remove.
(__arm_vminq_m_u16): Remove.
(__arm_vminq_x_s8): Remove.
(__arm_vminq_x_s16): Remove.
(__arm_vminq_x_s32): Remove.
(__arm_vminq_x_u8): Remove.
(__arm_vminq_x_u16): Remove.
(__arm_vminq_x_u32): Remove.
(__arm_vmaxq_x_s8): Remove.
(__arm_vmaxq_x_s16): Remove.
(__arm_vmaxq_x_s32): Remove.
(__arm_vmaxq_x_u8): Remove.
(__arm_vmaxq_x_u16): Remove.
(__arm_vmaxq_x_u32): Remove.
(__arm_vminq): Remove.
(__arm_vmaxq): Remove.
(__arm_vmaxq_m): Remove.
(__arm_vminq_m): Remove.
(__arm_vminq_x): Remove.
(__arm_vmaxq_x): Remove.
2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (MAX_MIN_SU): New.
(max_min_su_str): New.
(max_min_supf): New.
* config/arm/mve.md (mve_vmaxq_s<mode>, mve_vmaxq_u<mode>)
(mve_vminq_s<mode>, mve_vminq_u<mode>): Merge into ...
(mve_<max_min_su_str>q_<max_min_supf><mode>): ... this.
2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (FUNCTION_WITH_M_N_R): New.
(vqshlq, vshlq): New.
* config/arm/arm-mve-builtins-base.def (vqshlq, vshlq): New.
* config/arm/arm-mve-builtins-base.h (vqshlq, vshlq): New.
* config/arm/arm_mve.h (vshlq): Remove.
(vshlq_r): Remove.
(vshlq_n): Remove.
(vshlq_m_r): Remove.
(vshlq_m): Remove.
(vshlq_m_n): Remove.
(vshlq_x): Remove.
(vshlq_x_n): Remove.
(vshlq_s8): Remove.
(vshlq_s16): Remove.
(vshlq_s32): Remove.
(vshlq_u8): Remove.
(vshlq_u16): Remove.
(vshlq_u32): Remove.
(vshlq_r_u8): Remove.
(vshlq_n_u8): Remove.
(vshlq_r_s8): Remove.
(vshlq_n_s8): Remove.
(vshlq_r_u16): Remove.
(vshlq_n_u16): Remove.
(vshlq_r_s16): Remove.
(vshlq_n_s16): Remove.
(vshlq_r_u32): Remove.
(vshlq_n_u32): Remove.
(vshlq_r_s32): Remove.
(vshlq_n_s32): Remove.
(vshlq_m_r_u8): Remove.
(vshlq_m_r_s8): Remove.
(vshlq_m_r_u16): Remove.
(vshlq_m_r_s16): Remove.
(vshlq_m_r_u32): Remove.
(vshlq_m_r_s32): Remove.
(vshlq_m_u8): Remove.
(vshlq_m_s8): Remove.
(vshlq_m_u16): Remove.
(vshlq_m_s16): Remove.
(vshlq_m_u32): Remove.
(vshlq_m_s32): Remove.
(vshlq_m_n_s8): Remove.
(vshlq_m_n_s32): Remove.
(vshlq_m_n_s16): Remove.
(vshlq_m_n_u8): Remove.
(vshlq_m_n_u32): Remove.
(vshlq_m_n_u16): Remove.
(vshlq_x_s8): Remove.
(vshlq_x_s16): Remove.
(vshlq_x_s32): Remove.
(vshlq_x_u8): Remove.
(vshlq_x_u16): Remove.
(vshlq_x_u32): Remove.
(vshlq_x_n_s8): Remove.
(vshlq_x_n_s16): Remove.
(vshlq_x_n_s32): Remove.
(vshlq_x_n_u8): Remove.
(vshlq_x_n_u16): Remove.
(vshlq_x_n_u32): Remove.
(__arm_vshlq_s8): Remove.
(__arm_vshlq_s16): Remove.
(__arm_vshlq_s32): Remove.
(__arm_vshlq_u8): Remove.
(__arm_vshlq_u16): Remove.
(__arm_vshlq_u32): Remove.
(__arm_vshlq_r_u8): Remove.
(__arm_vshlq_n_u8): Remove.
(__arm_vshlq_r_s8): Remove.
(__arm_vshlq_n_s8): Remove.
(__arm_vshlq_r_u16): Remove.
(__arm_vshlq_n_u16): Remove.
(__arm_vshlq_r_s16): Remove.
(__arm_vshlq_n_s16): Remove.
(__arm_vshlq_r_u32): Remove.
(__arm_vshlq_n_u32): Remove.
(__arm_vshlq_r_s32): Remove.
(__arm_vshlq_n_s32): Remove.
(__arm_vshlq_m_r_u8): Remove.
(__arm_vshlq_m_r_s8): Remove.
(__arm_vshlq_m_r_u16): Remove.
(__arm_vshlq_m_r_s16): Remove.
(__arm_vshlq_m_r_u32): Remove.
(__arm_vshlq_m_r_s32): Remove.
(__arm_vshlq_m_u8): Remove.
(__arm_vshlq_m_s8): Remove.
(__arm_vshlq_m_u16): Remove.
(__arm_vshlq_m_s16): Remove.
(__arm_vshlq_m_u32): Remove.
(__arm_vshlq_m_s32): Remove.
(__arm_vshlq_m_n_s8): Remove.
(__arm_vshlq_m_n_s32): Remove.
(__arm_vshlq_m_n_s16): Remove.
(__arm_vshlq_m_n_u8): Remove.
(__arm_vshlq_m_n_u32): Remove.
(__arm_vshlq_m_n_u16): Remove.
(__arm_vshlq_x_s8): Remove.
(__arm_vshlq_x_s16): Remove.
(__arm_vshlq_x_s32): Remove.
(__arm_vshlq_x_u8): Remove.
(__arm_vshlq_x_u16): Remove.
(__arm_vshlq_x_u32): Remove.
(__arm_vshlq_x_n_s8): Remove.
(__arm_vshlq_x_n_s16): Remove.
(__arm_vshlq_x_n_s32): Remove.
(__arm_vshlq_x_n_u8): Remove.
(__arm_vshlq_x_n_u16): Remove.
(__arm_vshlq_x_n_u32): Remove.
(__arm_vshlq): Remove.
(__arm_vshlq_r): Remove.
(__arm_vshlq_n): Remove.
(__arm_vshlq_m_r): Remove.
(__arm_vshlq_m): Remove.
(__arm_vshlq_m_n): Remove.
(__arm_vshlq_x): Remove.
(__arm_vshlq_x_n): Remove.
(vqshlq): Remove.
(vqshlq_r): Remove.
(vqshlq_n): Remove.
(vqshlq_m_r): Remove.
(vqshlq_m_n): Remove.
(vqshlq_m): Remove.
(vqshlq_u8): Remove.
(vqshlq_r_u8): Remove.
(vqshlq_n_u8): Remove.
(vqshlq_s8): Remove.
(vqshlq_r_s8): Remove.
(vqshlq_n_s8): Remove.
(vqshlq_u16): Remove.
(vqshlq_r_u16): Remove.
(vqshlq_n_u16): Remove.
(vqshlq_s16): Remove.
(vqshlq_r_s16): Remove.
(vqshlq_n_s16): Remove.
(vqshlq_u32): Remove.
(vqshlq_r_u32): Remove.
(vqshlq_n_u32): Remove.
(vqshlq_s32): Remove.
(vqshlq_r_s32): Remove.
(vqshlq_n_s32): Remove.
(vqshlq_m_r_u8): Remove.
(vqshlq_m_r_s8): Remove.
(vqshlq_m_r_u16): Remove.
(vqshlq_m_r_s16): Remove.
(vqshlq_m_r_u32): Remove.
(vqshlq_m_r_s32): Remove.
(vqshlq_m_n_s8): Remove.
(vqshlq_m_n_s32): Remove.
(vqshlq_m_n_s16): Remove.
(vqshlq_m_n_u8): Remove.
(vqshlq_m_n_u32): Remove.
(vqshlq_m_n_u16): Remove.
(vqshlq_m_s8): Remove.
(vqshlq_m_s32): Remove.
(vqshlq_m_s16): Remove.
(vqshlq_m_u8): Remove.
(vqshlq_m_u32): Remove.
(vqshlq_m_u16): Remove.
(__arm_vqshlq_u8): Remove.
(__arm_vqshlq_r_u8): Remove.
(__arm_vqshlq_n_u8): Remove.
(__arm_vqshlq_s8): Remove.
(__arm_vqshlq_r_s8): Remove.
(__arm_vqshlq_n_s8): Remove.
(__arm_vqshlq_u16): Remove.
(__arm_vqshlq_r_u16): Remove.
(__arm_vqshlq_n_u16): Remove.
(__arm_vqshlq_s16): Remove.
(__arm_vqshlq_r_s16): Remove.
(__arm_vqshlq_n_s16): Remove.
(__arm_vqshlq_u32): Remove.
(__arm_vqshlq_r_u32): Remove.
(__arm_vqshlq_n_u32): Remove.
(__arm_vqshlq_s32): Remove.
(__arm_vqshlq_r_s32): Remove.
(__arm_vqshlq_n_s32): Remove.
(__arm_vqshlq_m_r_u8): Remove.
(__arm_vqshlq_m_r_s8): Remove.
(__arm_vqshlq_m_r_u16): Remove.
(__arm_vqshlq_m_r_s16): Remove.
(__arm_vqshlq_m_r_u32): Remove.
(__arm_vqshlq_m_r_s32): Remove.
(__arm_vqshlq_m_n_s8): Remove.
(__arm_vqshlq_m_n_s32): Remove.
(__arm_vqshlq_m_n_s16): Remove.
(__arm_vqshlq_m_n_u8): Remove.
(__arm_vqshlq_m_n_u32): Remove.
(__arm_vqshlq_m_n_u16): Remove.
(__arm_vqshlq_m_s8): Remove.
(__arm_vqshlq_m_s32): Remove.
(__arm_vqshlq_m_s16): Remove.
(__arm_vqshlq_m_u8): Remove.
(__arm_vqshlq_m_u32): Remove.
(__arm_vqshlq_m_u16): Remove.
(__arm_vqshlq): Remove.
(__arm_vqshlq_r): Remove.
(__arm_vqshlq_n): Remove.
(__arm_vqshlq_m_r): Remove.
(__arm_vqshlq_m_n): Remove.
(__arm_vqshlq_m): Remove.
2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-functions.h (class
unspec_mve_function_exact_insn_vshl): New.
2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-shapes.cc (binary_lshift_r): New.
* config/arm/arm-mve-builtins-shapes.h (binary_lshift_r): New.
2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins.cc (has_inactive_argument)
(finish_opt_n_resolution): Handle MODE_r.
* config/arm/arm-mve-builtins.def (r): New mode.
2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-shapes.cc (binary_lshift): New.
* config/arm/arm-mve-builtins-shapes.h (binary_lshift): New.
2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (FUNCTION_WITHOUT_N): New.
(vabdq): New.
* config/arm/arm-mve-builtins-base.def (vabdq): New.
* config/arm/arm-mve-builtins-base.h (vabdq): New.
* config/arm/arm_mve.h (vabdq): Remove.
(vabdq_m): Remove.
(vabdq_x): Remove.
(vabdq_u8): Remove.
(vabdq_s8): Remove.
(vabdq_u16): Remove.
(vabdq_s16): Remove.
(vabdq_u32): Remove.
(vabdq_s32): Remove.
(vabdq_f16): Remove.
(vabdq_f32): Remove.
(vabdq_m_s8): Remove.
(vabdq_m_s32): Remove.
(vabdq_m_s16): Remove.
(vabdq_m_u8): Remove.
(vabdq_m_u32): Remove.
(vabdq_m_u16): Remove.
(vabdq_m_f32): Remove.
(vabdq_m_f16): Remove.
(vabdq_x_s8): Remove.
(vabdq_x_s16): Remove.
(vabdq_x_s32): Remove.
(vabdq_x_u8): Remove.
(vabdq_x_u16): Remove.
(vabdq_x_u32): Remove.
(vabdq_x_f16): Remove.
(vabdq_x_f32): Remove.
(__arm_vabdq_u8): Remove.
(__arm_vabdq_s8): Remove.
(__arm_vabdq_u16): Remove.
(__arm_vabdq_s16): Remove.
(__arm_vabdq_u32): Remove.
(__arm_vabdq_s32): Remove.
(__arm_vabdq_m_s8): Remove.
(__arm_vabdq_m_s32): Remove.
(__arm_vabdq_m_s16): Remove.
(__arm_vabdq_m_u8): Remove.
(__arm_vabdq_m_u32): Remove.
(__arm_vabdq_m_u16): Remove.
(__arm_vabdq_x_s8): Remove.
(__arm_vabdq_x_s16): Remove.
(__arm_vabdq_x_s32): Remove.
(__arm_vabdq_x_u8): Remove.
(__arm_vabdq_x_u16): Remove.
(__arm_vabdq_x_u32): Remove.
(__arm_vabdq_f16): Remove.
(__arm_vabdq_f32): Remove.
(__arm_vabdq_m_f32): Remove.
(__arm_vabdq_m_f16): Remove.
(__arm_vabdq_x_f16): Remove.
(__arm_vabdq_x_f32): Remove.
(__arm_vabdq): Remove.
(__arm_vabdq_m): Remove.
(__arm_vabdq_x): Remove.
2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (MVE_FP_M_BINARY): Add vabdq.
(MVE_FP_VABDQ_ONLY): New.
(mve_insn): Add vabd.
* config/arm/mve.md (mve_vabdq_f<mode>): Move into ...
(@mve_<mve_insn>q_f<mode>): ... this.
(mve_vabdq_m_f<mode>): Remove.
2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (vqrdmulhq): New.
* config/arm/arm-mve-builtins-base.def (vqrdmulhq): New.
* config/arm/arm-mve-builtins-base.h (vqrdmulhq): New.
* config/arm/arm_mve.h (vqrdmulhq): Remove.
(vqrdmulhq_m): Remove.
(vqrdmulhq_s8): Remove.
(vqrdmulhq_n_s8): Remove.
(vqrdmulhq_s16): Remove.
(vqrdmulhq_n_s16): Remove.
(vqrdmulhq_s32): Remove.
(vqrdmulhq_n_s32): Remove.
(vqrdmulhq_m_n_s8): Remove.
(vqrdmulhq_m_n_s32): Remove.
(vqrdmulhq_m_n_s16): Remove.
(vqrdmulhq_m_s8): Remove.
(vqrdmulhq_m_s32): Remove.
(vqrdmulhq_m_s16): Remove.
(__arm_vqrdmulhq_s8): Remove.
(__arm_vqrdmulhq_n_s8): Remove.
(__arm_vqrdmulhq_s16): Remove.
(__arm_vqrdmulhq_n_s16): Remove.
(__arm_vqrdmulhq_s32): Remove.
(__arm_vqrdmulhq_n_s32): Remove.
(__arm_vqrdmulhq_m_n_s8): Remove.
(__arm_vqrdmulhq_m_n_s32): Remove.
(__arm_vqrdmulhq_m_n_s16): Remove.
(__arm_vqrdmulhq_m_s8): Remove.
(__arm_vqrdmulhq_m_s32): Remove.
(__arm_vqrdmulhq_m_s16): Remove.
(__arm_vqrdmulhq): Remove.
(__arm_vqrdmulhq_m): Remove.
2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (MVE_SHIFT_M_R, MVE_SHIFT_M_N)
(MVE_SHIFT_N, MVE_SHIFT_R): New.
(mve_insn): Add vqshl, vshl.
* config/arm/mve.md (mve_vqshlq_n_<supf><mode>)
(mve_vshlq_n_<supf><mode>): Merge into ...
(@mve_<mve_insn>q_n_<supf><mode>): ... this.
(mve_vqshlq_r_<supf><mode>, mve_vshlq_r_<supf><mode>): Merge into
...
(@mve_<mve_insn>q_r_<supf><mode>): ... this.
(mve_vqshlq_m_r_<supf><mode>, mve_vshlq_m_r_<supf><mode>): Merge
into ...
(@mve_<mve_insn>q_m_r_<supf><mode>): ... this.
(mve_vqshlq_m_n_<supf><mode>, mve_vshlq_m_n_<supf><mode>): Merge
into ...
(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
* config/arm/vec-common.md (mve_vshlq_<supf><mode>): Transform
into ...
(@mve_<mve_insn>q_<supf><mode>): ... this.
2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (vqrshlq, vrshlq): New.
* config/arm/arm-mve-builtins-base.def (vqrshlq, vrshlq): New.
* config/arm/arm-mve-builtins-base.h (vqrshlq, vrshlq): New.
* config/arm/arm-mve-builtins.cc (has_inactive_argument): Handle
vqrshlq, vrshlq.
* config/arm/arm_mve.h (vrshlq): Remove.
(vrshlq_m_n): Remove.
(vrshlq_m): Remove.
(vrshlq_x): Remove.
(vrshlq_u8): Remove.
(vrshlq_n_u8): Remove.
(vrshlq_s8): Remove.
(vrshlq_n_s8): Remove.
(vrshlq_u16): Remove.
(vrshlq_n_u16): Remove.
(vrshlq_s16): Remove.
(vrshlq_n_s16): Remove.
(vrshlq_u32): Remove.
(vrshlq_n_u32): Remove.
(vrshlq_s32): Remove.
(vrshlq_n_s32): Remove.
(vrshlq_m_n_u8): Remove.
(vrshlq_m_n_s8): Remove.
(vrshlq_m_n_u16): Remove.
(vrshlq_m_n_s16): Remove.
(vrshlq_m_n_u32): Remove.
(vrshlq_m_n_s32): Remove.
(vrshlq_m_s8): Remove.
(vrshlq_m_s32): Remove.
(vrshlq_m_s16): Remove.
(vrshlq_m_u8): Remove.
(vrshlq_m_u32): Remove.
(vrshlq_m_u16): Remove.
(vrshlq_x_s8): Remove.
(vrshlq_x_s16): Remove.
(vrshlq_x_s32): Remove.
(vrshlq_x_u8): Remove.
(vrshlq_x_u16): Remove.
(vrshlq_x_u32): Remove.
(__arm_vrshlq_u8): Remove.
(__arm_vrshlq_n_u8): Remove.
(__arm_vrshlq_s8): Remove.
(__arm_vrshlq_n_s8): Remove.
(__arm_vrshlq_u16): Remove.
(__arm_vrshlq_n_u16): Remove.
(__arm_vrshlq_s16): Remove.
(__arm_vrshlq_n_s16): Remove.
(__arm_vrshlq_u32): Remove.
(__arm_vrshlq_n_u32): Remove.
(__arm_vrshlq_s32): Remove.
(__arm_vrshlq_n_s32): Remove.
(__arm_vrshlq_m_n_u8): Remove.
(__arm_vrshlq_m_n_s8): Remove.
(__arm_vrshlq_m_n_u16): Remove.
(__arm_vrshlq_m_n_s16): Remove.
(__arm_vrshlq_m_n_u32): Remove.
(__arm_vrshlq_m_n_s32): Remove.
(__arm_vrshlq_m_s8): Remove.
(__arm_vrshlq_m_s32): Remove.
(__arm_vrshlq_m_s16): Remove.
(__arm_vrshlq_m_u8): Remove.
(__arm_vrshlq_m_u32): Remove.
(__arm_vrshlq_m_u16): Remove.
(__arm_vrshlq_x_s8): Remove.
(__arm_vrshlq_x_s16): Remove.
(__arm_vrshlq_x_s32): Remove.
(__arm_vrshlq_x_u8): Remove.
(__arm_vrshlq_x_u16): Remove.
(__arm_vrshlq_x_u32): Remove.
(__arm_vrshlq): Remove.
(__arm_vrshlq_m_n): Remove.
(__arm_vrshlq_m): Remove.
(__arm_vrshlq_x): Remove.
(vqrshlq): Remove.
(vqrshlq_m_n): Remove.
(vqrshlq_m): Remove.
(vqrshlq_u8): Remove.
(vqrshlq_n_u8): Remove.
(vqrshlq_s8): Remove.
(vqrshlq_n_s8): Remove.
(vqrshlq_u16): Remove.
(vqrshlq_n_u16): Remove.
(vqrshlq_s16): Remove.
(vqrshlq_n_s16): Remove.
(vqrshlq_u32): Remove.
(vqrshlq_n_u32): Remove.
(vqrshlq_s32): Remove.
(vqrshlq_n_s32): Remove.
(vqrshlq_m_n_u8): Remove.
(vqrshlq_m_n_s8): Remove.
(vqrshlq_m_n_u16): Remove.
(vqrshlq_m_n_s16): Remove.
(vqrshlq_m_n_u32): Remove.
(vqrshlq_m_n_s32): Remove.
(vqrshlq_m_s8): Remove.
(vqrshlq_m_s32): Remove.
(vqrshlq_m_s16): Remove.
(vqrshlq_m_u8): Remove.
(vqrshlq_m_u32): Remove.
(vqrshlq_m_u16): Remove.
(__arm_vqrshlq_u8): Remove.
(__arm_vqrshlq_n_u8): Remove.
(__arm_vqrshlq_s8): Remove.
(__arm_vqrshlq_n_s8): Remove.
(__arm_vqrshlq_u16): Remove.
(__arm_vqrshlq_n_u16): Remove.
(__arm_vqrshlq_s16): Remove.
(__arm_vqrshlq_n_s16): Remove.
(__arm_vqrshlq_u32): Remove.
(__arm_vqrshlq_n_u32): Remove.
(__arm_vqrshlq_s32): Remove.
(__arm_vqrshlq_n_s32): Remove.
(__arm_vqrshlq_m_n_u8): Remove.
(__arm_vqrshlq_m_n_s8): Remove.
(__arm_vqrshlq_m_n_u16): Remove.
(__arm_vqrshlq_m_n_s16): Remove.
(__arm_vqrshlq_m_n_u32): Remove.
(__arm_vqrshlq_m_n_s32): Remove.
(__arm_vqrshlq_m_s8): Remove.
(__arm_vqrshlq_m_s32): Remove.
(__arm_vqrshlq_m_s16): Remove.
(__arm_vqrshlq_m_u8): Remove.
(__arm_vqrshlq_m_u32): Remove.
(__arm_vqrshlq_m_u16): Remove.
(__arm_vqrshlq): Remove.
(__arm_vqrshlq_m_n): Remove.
(__arm_vqrshlq_m): Remove.
2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (MVE_RSHIFT_M_N, MVE_RSHIFT_N): New.
(mve_insn): Add vqrshl, vrshl.
* config/arm/mve.md (mve_vqrshlq_n_<supf><mode>)
(mve_vrshlq_n_<supf><mode>): Merge into ...
(@mve_<mve_insn>q_n_<supf><mode>): ... this.
(mve_vqrshlq_m_n_<supf><mode>, mve_vrshlq_m_n_<supf><mode>): Merge
into ...
(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
2023-05-05 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-shapes.cc (binary_round_lshift): New.
* config/arm/arm-mve-builtins-shapes.h (binary_round_lshift): New.
2023-05-05 Juzhe-Zhong <juzhe.zhong@rivai.ai>
PR target/109615
* config/riscv/riscv-vsetvl.cc (avl_info::multiple_source_equal_p): Add
denegrate PHI optmization.
2023-05-05 Uros Bizjak <ubizjak@gmail.com>
* config/i386/predicates.md (register_no_SP_operand):
Rename from index_register_operand.
(call_register_operand): Update for rename.
* config/i386/i386.md (*lea<mode>_general_[1234]): Update for rename.
2023-05-05 Tamar Christina <tamar.christina@arm.com>
PR bootstrap/84402
* Makefile.in (NUM_MATCH_SPLITS, MATCH_SPLITS_SEQ,
GIMPLE_MATCH_PD_SEQ_SRC, GIMPLE_MATCH_PD_SEQ_O,
GENERIC_MATCH_PD_SEQ_SRC, GENERIC_MATCH_PD_SEQ_O): New.
(OBJS, MOSTLYCLEANFILES, .PRECIOUS): Use them.
(s-match): Split into s-generic-match and s-gimple-match.
* configure.ac (with-matchpd-partitions,
DEFAULT_MATCHPD_PARTITIONS): New.
* configure: Regenerate.
2023-05-05 Tamar Christina <tamar.christina@arm.com>
PR bootstrap/84402
* genmatch.cc (emit_func, SIZED_BASED_CHUNKS, get_out_file): New.
(decision_tree::gen): Accept list of files instead of single and update
to write function definition to header and main file.
(write_predicate): Likewise.
(write_header): Emit pragmas and new includes.
(main): Create file buffers and cleanup.
(showUsage, write_header_includes): New.
2023-05-05 Tamar Christina <tamar.christina@arm.com>
PR bootstrap/84402
* Makefile.in (OBJS): Add gimple-match-exports.o.
* genmatch.cc (decision_tree::gen): Export gimple_gimplify helpers.
* gimple-match-head.cc (gimple_simplify, gimple_resimplify1,
gimple_resimplify2, gimple_resimplify3, gimple_resimplify4,
gimple_resimplify5, constant_for_folding, convert_conditional_op,
maybe_resimplify_conditional_op, gimple_match_op::resimplify,
maybe_build_generic_op, build_call_internal, maybe_push_res_to_seq,
do_valueize, try_conditional_simplification, gimple_extract,
gimple_extract_op, canonicalize_code, commutative_binary_op_p,
commutative_ternary_op_p, first_commutative_argument,
associative_binary_op_p, directly_supported_p,
get_conditional_internal_fn): Moved to gimple-match-exports.cc
* gimple-match-exports.cc: New file.
2023-05-05 Tamar Christina <tamar.christina@arm.com>
PR bootstrap/84402
* genmatch.cc (decision_tree::gen, write_predicate): Generate new
debug_dump var.
(dt_simplify::gen_1): Use it.
2023-05-05 Tamar Christina <tamar.christina@arm.com>
PR bootstrap/84402
* genmatch.cc (output_line_directive): Only emit commented directive
when -vv.
2023-05-05 Tamar Christina <tamar.christina@arm.com>
PR bootstrap/84402
* genmatch.cc (dt_simplify::gen_1): Only emit labels if used.
2023-05-05 Tobias Burnus <tobias@codesourcery.com>
* config/gcn/gcn.cc (gcn_vectorize_builtin_vectorized_function): Remove
unused in_mode/in_n variables.
2023-05-05 Richard Biener <rguenther@suse.de>
PR tree-optimization/109735
* tree-vect-stmts.cc (vectorizable_operation): Perform
conversion for POINTER_DIFF_EXPR unconditionally.
2023-05-05 Uros Bizjak <ubizjak@gmail.com>
* config/i386/mmx.md (mulv2si3): New expander.
(*mulv2si3): New insn pattern.
2023-05-05 Tobias Burnus <tobias@codesourcery.com>
Thomas Schwinge <thomas@codesourcery.com>
PR libgomp/108098
* config/nvptx/mkoffload.cc (process): Emit dummy procedure
alongside reverse-offload function table to prevent NULL values
of the function addresses.
2023-05-05 Jakub Jelinek <jakub@redhat.com>
* builtins.cc (do_mpfr_ckconv, do_mpc_ckconv): Fix comment typo,
mpft_t -> mpfr_t.
* fold-const-call.cc (do_mpfr_ckconv, do_mpc_ckconv): Likewise.
2023-05-05 Andrew Pinski <apinski@marvell.com>
PR tree-optimization/109732
* tree-ssa-phiopt.cc (match_simplify_replacement): Fix the selection
of the argtrue/argfalse.
2023-05-05 Andrew Pinski <apinski@marvell.com>
PR tree-optimization/109722
* match.pd: Extend the `ABS<a> == 0` pattern
to cover `ABSU<a> == 0` too.
2023-05-04 Uros Bizjak <ubizjak@gmail.com>
PR target/109733
* config/i386/predicates.md (index_reg_operand): New predicate.
* config/i386/i386.md (ashift to lea spliter): Use
general_reg_operand and index_reg_operand predicates.
2023-05-04 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-simd.md (aarch64_<sur><addsub>hn2<mode>_insn_le):
Rename and reimplement with RTL codes to...
(aarch64_<optab>hn2<mode>_insn_le): .. This.
(aarch64_r<optab>hn2<mode>_insn_le): New pattern.
(aarch64_<sur><addsub>hn2<mode>_insn_be): Rename and reimplement with RTL
codes to...
(aarch64_<optab>hn2<mode>_insn_be): ... This.
(aarch64_r<optab>hn2<mode>_insn_be): New pattern.
(aarch64_<sur><addsub>hn2<mode>): Rename and adjust expander to...
(aarch64_<optab>hn2<mode>): ... This.
(aarch64_r<optab>hn2<mode>): New expander.
* config/aarch64/iterators.md (UNSPEC_ADDHN, UNSPEC_RADDHN,
UNSPEC_SUBHN, UNSPEC_RSUBHN): Delete unspecs.
(ADDSUBHN): Delete.
(sur): Remove handling of the above.
(addsub): Likewise.
2023-05-04 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-simd.md (aarch64_<sur><addsub>hn<mode>_insn_le):
Delete.
(aarch64_<optab>hn<mode>_insn<vczle><vczbe>): New define_insn.
(aarch64_<sur><addsub>hn<mode>_insn_be): Delete.
(aarch64_r<optab>hn<mode>_insn<vczle><vczbe>): New define_insn.
(aarch64_<sur><addsub>hn<mode>): Delete.
(aarch64_<optab>hn<mode>): New define_expand.
(aarch64_r<optab>hn<mode>): Likewise.
* config/aarch64/predicates.md (aarch64_simd_raddsubhn_imm_vec):
New predicate.
2023-05-04 Andrew Pinski <apinski@marvell.com>
* tree-ssa-phiopt.cc (replace_phi_edge_with_variable): Handle
diamond form bb with forwarder only empty blocks better.
2023-05-04 Andrew Pinski <apinski@marvell.com>
* tree-ssa-threadupdate.cc (copy_phi_arg_into_existing_phi): Move to ...
* tree-cfg.cc (copy_phi_arg_into_existing_phi): Here and remove static.
(gimple_duplicate_sese_tail): Use copy_phi_arg_into_existing_phi instead
of an inline version of it.
* tree-cfgcleanup.cc (remove_forwarder_block): Likewise.
* tree-cfg.h (copy_phi_arg_into_existing_phi): New declaration.
2023-05-04 Andrew Pinski <apinski@marvell.com>
* tree-ssa-phiopt.cc (replace_phi_edge_with_variable): Change
the default argument value for dce_ssa_names to nullptr.
Check to make sure dce_ssa_names is a non-nullptr before
calling simple_dce_from_worklist.
2023-05-04 Uros Bizjak <ubizjak@gmail.com>
* config/i386/predicates.md (index_register_operand): Reject
arg_pointer_rtx, frame_pointer_rtx, stack_pointer_rtx and
VIRTUAL_REGISTER_P operands. Allow subregs of memory before reload.
(call_register_no_elim_operand): Rewrite as ...
(call_register_operand): ... this.
(call_insn_operand): Use call_register_operand predicate.
2023-05-04 Richard Biener <rguenther@suse.de>
PR tree-optimization/109721
* tree-vect-stmts.cc (vectorizable_operation): Make sure
to test word_mode for all !target_support_p operations.
2023-05-04 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR target/99195
* config/aarch64/aarch64-simd.md (aarch64_<su>aba<mode>): Rename to...
(aarch64_<su>aba<mode><vczle><vczbe>): ... This.
(aarch64_mla<mode>): Rename to...
(aarch64_mla<mode><vczle><vczbe>): ... This.
(*aarch64_mla_elt<mode>): Rename to...
(*aarch64_mla_elt<mode><vczle><vczbe>): ... This.
(*aarch64_mla_elt_<vswap_width_name><mode>): Rename to...
(*aarch64_mla_elt_<vswap_width_name><mode><vczle><vczbe>): ... This.
(aarch64_mla_n<mode>): Rename to...
(aarch64_mla_n<mode><vczle><vczbe>): ... This.
(aarch64_mls<mode>): Rename to...
(aarch64_mls<mode><vczle><vczbe>): ... This.
(*aarch64_mls_elt<mode>): Rename to...
(*aarch64_mls_elt<mode><vczle><vczbe>): ... This.
(*aarch64_mls_elt_<vswap_width_name><mode>): Rename to...
(*aarch64_mls_elt_<vswap_width_name><mode><vczle><vczbe>): ... This.
(aarch64_mls_n<mode>): Rename to...
(aarch64_mls_n<mode><vczle><vczbe>): ... This.
(fma<mode>4): Rename to...
(fma<mode>4<vczle><vczbe>): ... This.
(*aarch64_fma4_elt<mode>): Rename to...
(*aarch64_fma4_elt<mode><vczle><vczbe>): ... This.
(*aarch64_fma4_elt_<vswap_width_name><mode>): Rename to...
(*aarch64_fma4_elt_<vswap_width_name><mode><vczle><vczbe>): ... This.
(*aarch64_fma4_elt_from_dup<mode>): Rename to...
(*aarch64_fma4_elt_from_dup<mode><vczle><vczbe>): ... This.
(fnma<mode>4): Rename to...
(fnma<mode>4<vczle><vczbe>): ... This.
(*aarch64_fnma4_elt<mode>): Rename to...
(*aarch64_fnma4_elt<mode><vczle><vczbe>): ... This.
(*aarch64_fnma4_elt_<vswap_width_name><mode>): Rename to...
(*aarch64_fnma4_elt_<vswap_width_name><mode><vczle><vczbe>): ... This.
(*aarch64_fnma4_elt_from_dup<mode>): Rename to...
(*aarch64_fnma4_elt_from_dup<mode><vczle><vczbe>): ... This.
(aarch64_simd_bsl<mode>_internal): Rename to...
(aarch64_simd_bsl<mode>_internal<vczle><vczbe>): ... This.
(*aarch64_simd_bsl<mode>_alt): Rename to...
(*aarch64_simd_bsl<mode>_alt<vczle><vczbe>): ... This.
2023-05-04 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR target/99195
* config/aarch64/aarch64-simd.md (aarch64_<su>abd<mode>): Rename to...
(aarch64_<su>abd<mode><vczle><vczbe>): ... This.
(fabd<mode>3): Rename to...
(fabd<mode>3<vczle><vczbe>): ... This.
(aarch64_<optab>p<mode>): Rename to...
(aarch64_<optab>p<mode><vczle><vczbe>): ... This.
(aarch64_faddp<mode>): Rename to...
(aarch64_faddp<mode><vczle><vczbe>): ... This.
2023-05-04 Martin Liska <mliska@suse.cz>
* gcov.cc (GCOV_JSON_FORMAT_VERSION): New definition.
(print_version): Use it.
(generate_results): Likewise.
2023-05-04 Richard Biener <rguenther@suse.de>
* tree-cfg.h (last_stmt): Rename to ...
(last_nondebug_stmt): ... this.
* tree-cfg.cc (last_stmt): Rename to ...
(last_nondebug_stmt): ... this.
(assign_discriminators): Adjust.
(group_case_labels_stmt): Likewise.
(gimple_can_duplicate_bb_p): Likewise.
(execute_fixup_cfg): Likewise.
* auto-profile.cc (afdo_propagate_circuit): Likewise.
* gimple-range.cc (gimple_ranger::range_on_exit): Likewise.
* omp-expand.cc (workshare_safe_to_combine_p): Likewise.
(determine_parallel_type): Likewise.
(adjust_context_and_scope): Likewise.
(expand_task_call): Likewise.
(remove_exit_barrier): Likewise.
(expand_omp_taskreg): Likewise.
(expand_omp_for_init_counts): Likewise.
(expand_omp_for_init_vars): Likewise.
(expand_omp_for_static_chunk): Likewise.
(expand_omp_simd): Likewise.
(expand_oacc_for): Likewise.
(expand_omp_for): Likewise.
(expand_omp_sections): Likewise.
(expand_omp_atomic_fetch_op): Likewise.
(expand_omp_atomic_cas): Likewise.
(expand_omp_atomic): Likewise.
(expand_omp_target): Likewise.
(expand_omp): Likewise.
(omp_make_gimple_edges): Likewise.
* trans-mem.cc (tm_region_init): Likewise.
* tree-inline.cc (redirect_all_calls): Likewise.
* tree-parloops.cc (gen_parallel_loop): Likewise.
* tree-ssa-loop-ch.cc (do_while_loop_p): Likewise.
* tree-ssa-loop-ivcanon.cc (canonicalize_loop_induction_variables):
Likewise.
* tree-ssa-loop-ivopts.cc (stmt_after_ip_normal_pos): Likewise.
(may_eliminate_iv): Likewise.
* tree-ssa-loop-manip.cc (standard_iv_increment_position): Likewise.
* tree-ssa-loop-niter.cc (do_warn_aggressive_loop_optimizations):
Likewise.
(estimate_numbers_of_iterations): Likewise.
* tree-ssa-loop-split.cc (compute_added_num_insns): Likewise.
* tree-ssa-loop-unswitch.cc (get_predicates_for_bb): Likewise.
(set_predicates_for_bb): Likewise.
(init_loop_unswitch_info): Likewise.
(hoist_guard): Likewise.
* tree-ssa-phiopt.cc (match_simplify_replacement): Likewise.
(minmax_replacement): Likewise.
* tree-ssa-reassoc.cc (update_range_test): Likewise.
(optimize_range_tests_to_bit_test): Likewise.
(optimize_range_tests_var_bound): Likewise.
(optimize_range_tests): Likewise.
(no_side_effect_bb): Likewise.
(suitable_cond_bb): Likewise.
(maybe_optimize_range_tests): Likewise.
(reassociate_bb): Likewise.
* tree-vrp.cc (rvrp_folder::pre_fold_bb): Likewise.
2023-05-04 Jakub Jelinek <jakub@redhat.com>
PR debug/109676
* config/i386/i386-features.cc (timode_scalar_chain::convert_insn):
If src is REG, change its mode to V1TImode and call fix_debug_reg_uses
for it only if it still has TImode. Don't decide whether to call
fix_debug_reg_uses based on whether SRC is ever set or not.
2023-05-04 Hans-Peter Nilsson <hp@axis.com>
* config/cris/cris.cc (cris_split_constant): New function.
* config/cris/cris.md (splitop): New iterator.
(opsplit1): New define_peephole2.
* config/cris/cris-protos.h (cris_split_constant): Declare.
(cris_splittable_constant_p): New macro.
2023-05-04 Hans-Peter Nilsson <hp@axis.com>
* config/cris/cris.cc (TARGET_SPILL_CLASS): Define
to ALL_REGS.
2023-05-04 Hans-Peter Nilsson <hp@axis.com>
* config/cris/cris.cc (cris_side_effect_mode_ok): Use
lra_in_progress, not reload_in_progress.
* config/cris/cris.md ("movdi", "*addi_reload"): Ditto.
* config/cris/constraints.md ("Q"): Ditto.
2023-05-03 Andrew Pinski <apinski@marvell.com>
* tree-ssa-dce.cc (simple_dce_from_worklist): Record
stats on removed number of statements and phis.
2023-05-03 Aldy Hernandez <aldyh@redhat.com>
PR tree-optimization/109711
* value-range.cc (irange::verify_range): Allow types of
error_mark_node.
2023-05-03 Alexander Monakov <amonakov@ispras.ru>
PR sanitizer/90746
* calls.cc (can_implement_as_sibling_call_p): Reject calls
to __sanitizer_cov_trace_pc.
2023-05-03 Richard Sandiford <richard.sandiford@arm.com>
PR target/109661
* config/aarch64/aarch64.cc (aarch64_function_arg_alignment): Add
a new ABI break parameter for GCC 14. Set it to the alignment
of enums that have an underlying type. Take the true alignment
of such enums from the TYPE_ALIGN of the underlying type's
TYPE_MAIN_VARIANT.
(aarch64_function_arg_boundary): Update accordingly.
(aarch64_layout_arg, aarch64_gimplify_va_arg_expr): Likewise.
Warn about ABI differences.
2023-05-03 Richard Sandiford <richard.sandiford@arm.com>
PR target/109661
* config/aarch64/aarch64.cc (aarch64_function_arg_alignment): Rename
ABI break variables to abi_break_gcc_9 and abi_break_gcc_13.
(aarch64_layout_arg, aarch64_function_arg_boundary): Likewise.
(aarch64_gimplify_va_arg_expr): Likewise.
2023-05-03 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (FUNCTION_WITH_M_N_NO_F)
(FUNCTION_WITHOUT_N_NO_F, FUNCTION_WITH_M_N_NO_U_F): New.
(vhaddq, vhsubq, vmulhq, vqaddq, vqsubq, vqdmulhq, vrhaddq)
(vrmulhq): New.
* config/arm/arm-mve-builtins-base.def (vhaddq, vhsubq, vmulhq)
(vqaddq, vqsubq, vqdmulhq, vrhaddq, vrmulhq): New.
* config/arm/arm-mve-builtins-base.h (vhaddq, vhsubq, vmulhq)
(vqaddq, vqsubq, vqdmulhq, vrhaddq, vrmulhq): New.
* config/arm/arm_mve.h (vhsubq): Remove.
(vhaddq): Remove.
(vhaddq_m): Remove.
(vhsubq_m): Remove.
(vhaddq_x): Remove.
(vhsubq_x): Remove.
(vhsubq_u8): Remove.
(vhsubq_n_u8): Remove.
(vhaddq_u8): Remove.
(vhaddq_n_u8): Remove.
(vhsubq_s8): Remove.
(vhsubq_n_s8): Remove.
(vhaddq_s8): Remove.
(vhaddq_n_s8): Remove.
(vhsubq_u16): Remove.
(vhsubq_n_u16): Remove.
(vhaddq_u16): Remove.
(vhaddq_n_u16): Remove.
(vhsubq_s16): Remove.
(vhsubq_n_s16): Remove.
(vhaddq_s16): Remove.
(vhaddq_n_s16): Remove.
(vhsubq_u32): Remove.
(vhsubq_n_u32): Remove.
(vhaddq_u32): Remove.
(vhaddq_n_u32): Remove.
(vhsubq_s32): Remove.
(vhsubq_n_s32): Remove.
(vhaddq_s32): Remove.
(vhaddq_n_s32): Remove.
(vhaddq_m_n_s8): Remove.
(vhaddq_m_n_s32): Remove.
(vhaddq_m_n_s16): Remove.
(vhaddq_m_n_u8): Remove.
(vhaddq_m_n_u32): Remove.
(vhaddq_m_n_u16): Remove.
(vhaddq_m_s8): Remove.
(vhaddq_m_s32): Remove.
(vhaddq_m_s16): Remove.
(vhaddq_m_u8): Remove.
(vhaddq_m_u32): Remove.
(vhaddq_m_u16): Remove.
(vhsubq_m_n_s8): Remove.
(vhsubq_m_n_s32): Remove.
(vhsubq_m_n_s16): Remove.
(vhsubq_m_n_u8): Remove.
(vhsubq_m_n_u32): Remove.
(vhsubq_m_n_u16): Remove.
(vhsubq_m_s8): Remove.
(vhsubq_m_s32): Remove.
(vhsubq_m_s16): Remove.
(vhsubq_m_u8): Remove.
(vhsubq_m_u32): Remove.
(vhsubq_m_u16): Remove.
(vhaddq_x_n_s8): Remove.
(vhaddq_x_n_s16): Remove.
(vhaddq_x_n_s32): Remove.
(vhaddq_x_n_u8): Remove.
(vhaddq_x_n_u16): Remove.
(vhaddq_x_n_u32): Remove.
(vhaddq_x_s8): Remove.
(vhaddq_x_s16): Remove.
(vhaddq_x_s32): Remove.
(vhaddq_x_u8): Remove.
(vhaddq_x_u16): Remove.
(vhaddq_x_u32): Remove.
(vhsubq_x_n_s8): Remove.
(vhsubq_x_n_s16): Remove.
(vhsubq_x_n_s32): Remove.
(vhsubq_x_n_u8): Remove.
(vhsubq_x_n_u16): Remove.
(vhsubq_x_n_u32): Remove.
(vhsubq_x_s8): Remove.
(vhsubq_x_s16): Remove.
(vhsubq_x_s32): Remove.
(vhsubq_x_u8): Remove.
(vhsubq_x_u16): Remove.
(vhsubq_x_u32): Remove.
(__arm_vhsubq_u8): Remove.
(__arm_vhsubq_n_u8): Remove.
(__arm_vhaddq_u8): Remove.
(__arm_vhaddq_n_u8): Remove.
(__arm_vhsubq_s8): Remove.
(__arm_vhsubq_n_s8): Remove.
(__arm_vhaddq_s8): Remove.
(__arm_vhaddq_n_s8): Remove.
(__arm_vhsubq_u16): Remove.
(__arm_vhsubq_n_u16): Remove.
(__arm_vhaddq_u16): Remove.
(__arm_vhaddq_n_u16): Remove.
(__arm_vhsubq_s16): Remove.
(__arm_vhsubq_n_s16): Remove.
(__arm_vhaddq_s16): Remove.
(__arm_vhaddq_n_s16): Remove.
(__arm_vhsubq_u32): Remove.
(__arm_vhsubq_n_u32): Remove.
(__arm_vhaddq_u32): Remove.
(__arm_vhaddq_n_u32): Remove.
(__arm_vhsubq_s32): Remove.
(__arm_vhsubq_n_s32): Remove.
(__arm_vhaddq_s32): Remove.
(__arm_vhaddq_n_s32): Remove.
(__arm_vhaddq_m_n_s8): Remove.
(__arm_vhaddq_m_n_s32): Remove.
(__arm_vhaddq_m_n_s16): Remove.
(__arm_vhaddq_m_n_u8): Remove.
(__arm_vhaddq_m_n_u32): Remove.
(__arm_vhaddq_m_n_u16): Remove.
(__arm_vhaddq_m_s8): Remove.
(__arm_vhaddq_m_s32): Remove.
(__arm_vhaddq_m_s16): Remove.
(__arm_vhaddq_m_u8): Remove.
(__arm_vhaddq_m_u32): Remove.
(__arm_vhaddq_m_u16): Remove.
(__arm_vhsubq_m_n_s8): Remove.
(__arm_vhsubq_m_n_s32): Remove.
(__arm_vhsubq_m_n_s16): Remove.
(__arm_vhsubq_m_n_u8): Remove.
(__arm_vhsubq_m_n_u32): Remove.
(__arm_vhsubq_m_n_u16): Remove.
(__arm_vhsubq_m_s8): Remove.
(__arm_vhsubq_m_s32): Remove.
(__arm_vhsubq_m_s16): Remove.
(__arm_vhsubq_m_u8): Remove.
(__arm_vhsubq_m_u32): Remove.
(__arm_vhsubq_m_u16): Remove.
(__arm_vhaddq_x_n_s8): Remove.
(__arm_vhaddq_x_n_s16): Remove.
(__arm_vhaddq_x_n_s32): Remove.
(__arm_vhaddq_x_n_u8): Remove.
(__arm_vhaddq_x_n_u16): Remove.
(__arm_vhaddq_x_n_u32): Remove.
(__arm_vhaddq_x_s8): Remove.
(__arm_vhaddq_x_s16): Remove.
(__arm_vhaddq_x_s32): Remove.
(__arm_vhaddq_x_u8): Remove.
(__arm_vhaddq_x_u16): Remove.
(__arm_vhaddq_x_u32): Remove.
(__arm_vhsubq_x_n_s8): Remove.
(__arm_vhsubq_x_n_s16): Remove.
(__arm_vhsubq_x_n_s32): Remove.
(__arm_vhsubq_x_n_u8): Remove.
(__arm_vhsubq_x_n_u16): Remove.
(__arm_vhsubq_x_n_u32): Remove.
(__arm_vhsubq_x_s8): Remove.
(__arm_vhsubq_x_s16): Remove.
(__arm_vhsubq_x_s32): Remove.
(__arm_vhsubq_x_u8): Remove.
(__arm_vhsubq_x_u16): Remove.
(__arm_vhsubq_x_u32): Remove.
(__arm_vhsubq): Remove.
(__arm_vhaddq): Remove.
(__arm_vhaddq_m): Remove.
(__arm_vhsubq_m): Remove.
(__arm_vhaddq_x): Remove.
(__arm_vhsubq_x): Remove.
(vmulhq): Remove.
(vmulhq_m): Remove.
(vmulhq_x): Remove.
(vmulhq_u8): Remove.
(vmulhq_s8): Remove.
(vmulhq_u16): Remove.
(vmulhq_s16): Remove.
(vmulhq_u32): Remove.
(vmulhq_s32): Remove.
(vmulhq_m_s8): Remove.
(vmulhq_m_s32): Remove.
(vmulhq_m_s16): Remove.
(vmulhq_m_u8): Remove.
(vmulhq_m_u32): Remove.
(vmulhq_m_u16): Remove.
(vmulhq_x_s8): Remove.
(vmulhq_x_s16): Remove.
(vmulhq_x_s32): Remove.
(vmulhq_x_u8): Remove.
(vmulhq_x_u16): Remove.
(vmulhq_x_u32): Remove.
(__arm_vmulhq_u8): Remove.
(__arm_vmulhq_s8): Remove.
(__arm_vmulhq_u16): Remove.
(__arm_vmulhq_s16): Remove.
(__arm_vmulhq_u32): Remove.
(__arm_vmulhq_s32): Remove.
(__arm_vmulhq_m_s8): Remove.
(__arm_vmulhq_m_s32): Remove.
(__arm_vmulhq_m_s16): Remove.
(__arm_vmulhq_m_u8): Remove.
(__arm_vmulhq_m_u32): Remove.
(__arm_vmulhq_m_u16): Remove.
(__arm_vmulhq_x_s8): Remove.
(__arm_vmulhq_x_s16): Remove.
(__arm_vmulhq_x_s32): Remove.
(__arm_vmulhq_x_u8): Remove.
(__arm_vmulhq_x_u16): Remove.
(__arm_vmulhq_x_u32): Remove.
(__arm_vmulhq): Remove.
(__arm_vmulhq_m): Remove.
(__arm_vmulhq_x): Remove.
(vqsubq): Remove.
(vqaddq): Remove.
(vqaddq_m): Remove.
(vqsubq_m): Remove.
(vqsubq_u8): Remove.
(vqsubq_n_u8): Remove.
(vqaddq_u8): Remove.
(vqaddq_n_u8): Remove.
(vqsubq_s8): Remove.
(vqsubq_n_s8): Remove.
(vqaddq_s8): Remove.
(vqaddq_n_s8): Remove.
(vqsubq_u16): Remove.
(vqsubq_n_u16): Remove.
(vqaddq_u16): Remove.
(vqaddq_n_u16): Remove.
(vqsubq_s16): Remove.
(vqsubq_n_s16): Remove.
(vqaddq_s16): Remove.
(vqaddq_n_s16): Remove.
(vqsubq_u32): Remove.
(vqsubq_n_u32): Remove.
(vqaddq_u32): Remove.
(vqaddq_n_u32): Remove.
(vqsubq_s32): Remove.
(vqsubq_n_s32): Remove.
(vqaddq_s32): Remove.
(vqaddq_n_s32): Remove.
(vqaddq_m_n_s8): Remove.
(vqaddq_m_n_s32): Remove.
(vqaddq_m_n_s16): Remove.
(vqaddq_m_n_u8): Remove.
(vqaddq_m_n_u32): Remove.
(vqaddq_m_n_u16): Remove.
(vqaddq_m_s8): Remove.
(vqaddq_m_s32): Remove.
(vqaddq_m_s16): Remove.
(vqaddq_m_u8): Remove.
(vqaddq_m_u32): Remove.
(vqaddq_m_u16): Remove.
(vqsubq_m_n_s8): Remove.
(vqsubq_m_n_s32): Remove.
(vqsubq_m_n_s16): Remove.
(vqsubq_m_n_u8): Remove.
(vqsubq_m_n_u32): Remove.
(vqsubq_m_n_u16): Remove.
(vqsubq_m_s8): Remove.
(vqsubq_m_s32): Remove.
(vqsubq_m_s16): Remove.
(vqsubq_m_u8): Remove.
(vqsubq_m_u32): Remove.
(vqsubq_m_u16): Remove.
(__arm_vqsubq_u8): Remove.
(__arm_vqsubq_n_u8): Remove.
(__arm_vqaddq_u8): Remove.
(__arm_vqaddq_n_u8): Remove.
(__arm_vqsubq_s8): Remove.
(__arm_vqsubq_n_s8): Remove.
(__arm_vqaddq_s8): Remove.
(__arm_vqaddq_n_s8): Remove.
(__arm_vqsubq_u16): Remove.
(__arm_vqsubq_n_u16): Remove.
(__arm_vqaddq_u16): Remove.
(__arm_vqaddq_n_u16): Remove.
(__arm_vqsubq_s16): Remove.
(__arm_vqsubq_n_s16): Remove.
(__arm_vqaddq_s16): Remove.
(__arm_vqaddq_n_s16): Remove.
(__arm_vqsubq_u32): Remove.
(__arm_vqsubq_n_u32): Remove.
(__arm_vqaddq_u32): Remove.
(__arm_vqaddq_n_u32): Remove.
(__arm_vqsubq_s32): Remove.
(__arm_vqsubq_n_s32): Remove.
(__arm_vqaddq_s32): Remove.
(__arm_vqaddq_n_s32): Remove.
(__arm_vqaddq_m_n_s8): Remove.
(__arm_vqaddq_m_n_s32): Remove.
(__arm_vqaddq_m_n_s16): Remove.
(__arm_vqaddq_m_n_u8): Remove.
(__arm_vqaddq_m_n_u32): Remove.
(__arm_vqaddq_m_n_u16): Remove.
(__arm_vqaddq_m_s8): Remove.
(__arm_vqaddq_m_s32): Remove.
(__arm_vqaddq_m_s16): Remove.
(__arm_vqaddq_m_u8): Remove.
(__arm_vqaddq_m_u32): Remove.
(__arm_vqaddq_m_u16): Remove.
(__arm_vqsubq_m_n_s8): Remove.
(__arm_vqsubq_m_n_s32): Remove.
(__arm_vqsubq_m_n_s16): Remove.
(__arm_vqsubq_m_n_u8): Remove.
(__arm_vqsubq_m_n_u32): Remove.
(__arm_vqsubq_m_n_u16): Remove.
(__arm_vqsubq_m_s8): Remove.
(__arm_vqsubq_m_s32): Remove.
(__arm_vqsubq_m_s16): Remove.
(__arm_vqsubq_m_u8): Remove.
(__arm_vqsubq_m_u32): Remove.
(__arm_vqsubq_m_u16): Remove.
(__arm_vqsubq): Remove.
(__arm_vqaddq): Remove.
(__arm_vqaddq_m): Remove.
(__arm_vqsubq_m): Remove.
(vqdmulhq): Remove.
(vqdmulhq_m): Remove.
(vqdmulhq_s8): Remove.
(vqdmulhq_n_s8): Remove.
(vqdmulhq_s16): Remove.
(vqdmulhq_n_s16): Remove.
(vqdmulhq_s32): Remove.
(vqdmulhq_n_s32): Remove.
(vqdmulhq_m_n_s8): Remove.
(vqdmulhq_m_n_s32): Remove.
(vqdmulhq_m_n_s16): Remove.
(vqdmulhq_m_s8): Remove.
(vqdmulhq_m_s32): Remove.
(vqdmulhq_m_s16): Remove.
(__arm_vqdmulhq_s8): Remove.
(__arm_vqdmulhq_n_s8): Remove.
(__arm_vqdmulhq_s16): Remove.
(__arm_vqdmulhq_n_s16): Remove.
(__arm_vqdmulhq_s32): Remove.
(__arm_vqdmulhq_n_s32): Remove.
(__arm_vqdmulhq_m_n_s8): Remove.
(__arm_vqdmulhq_m_n_s32): Remove.
(__arm_vqdmulhq_m_n_s16): Remove.
(__arm_vqdmulhq_m_s8): Remove.
(__arm_vqdmulhq_m_s32): Remove.
(__arm_vqdmulhq_m_s16): Remove.
(__arm_vqdmulhq): Remove.
(__arm_vqdmulhq_m): Remove.
(vrhaddq): Remove.
(vrhaddq_m): Remove.
(vrhaddq_x): Remove.
(vrhaddq_u8): Remove.
(vrhaddq_s8): Remove.
(vrhaddq_u16): Remove.
(vrhaddq_s16): Remove.
(vrhaddq_u32): Remove.
(vrhaddq_s32): Remove.
(vrhaddq_m_s8): Remove.
(vrhaddq_m_s32): Remove.
(vrhaddq_m_s16): Remove.
(vrhaddq_m_u8): Remove.
(vrhaddq_m_u32): Remove.
(vrhaddq_m_u16): Remove.
(vrhaddq_x_s8): Remove.
(vrhaddq_x_s16): Remove.
(vrhaddq_x_s32): Remove.
(vrhaddq_x_u8): Remove.
(vrhaddq_x_u16): Remove.
(vrhaddq_x_u32): Remove.
(__arm_vrhaddq_u8): Remove.
(__arm_vrhaddq_s8): Remove.
(__arm_vrhaddq_u16): Remove.
(__arm_vrhaddq_s16): Remove.
(__arm_vrhaddq_u32): Remove.
(__arm_vrhaddq_s32): Remove.
(__arm_vrhaddq_m_s8): Remove.
(__arm_vrhaddq_m_s32): Remove.
(__arm_vrhaddq_m_s16): Remove.
(__arm_vrhaddq_m_u8): Remove.
(__arm_vrhaddq_m_u32): Remove.
(__arm_vrhaddq_m_u16): Remove.
(__arm_vrhaddq_x_s8): Remove.
(__arm_vrhaddq_x_s16): Remove.
(__arm_vrhaddq_x_s32): Remove.
(__arm_vrhaddq_x_u8): Remove.
(__arm_vrhaddq_x_u16): Remove.
(__arm_vrhaddq_x_u32): Remove.
(__arm_vrhaddq): Remove.
(__arm_vrhaddq_m): Remove.
(__arm_vrhaddq_x): Remove.
(vrmulhq): Remove.
(vrmulhq_m): Remove.
(vrmulhq_x): Remove.
(vrmulhq_u8): Remove.
(vrmulhq_s8): Remove.
(vrmulhq_u16): Remove.
(vrmulhq_s16): Remove.
(vrmulhq_u32): Remove.
(vrmulhq_s32): Remove.
(vrmulhq_m_s8): Remove.
(vrmulhq_m_s32): Remove.
(vrmulhq_m_s16): Remove.
(vrmulhq_m_u8): Remove.
(vrmulhq_m_u32): Remove.
(vrmulhq_m_u16): Remove.
(vrmulhq_x_s8): Remove.
(vrmulhq_x_s16): Remove.
(vrmulhq_x_s32): Remove.
(vrmulhq_x_u8): Remove.
(vrmulhq_x_u16): Remove.
(vrmulhq_x_u32): Remove.
(__arm_vrmulhq_u8): Remove.
(__arm_vrmulhq_s8): Remove.
(__arm_vrmulhq_u16): Remove.
(__arm_vrmulhq_s16): Remove.
(__arm_vrmulhq_u32): Remove.
(__arm_vrmulhq_s32): Remove.
(__arm_vrmulhq_m_s8): Remove.
(__arm_vrmulhq_m_s32): Remove.
(__arm_vrmulhq_m_s16): Remove.
(__arm_vrmulhq_m_u8): Remove.
(__arm_vrmulhq_m_u32): Remove.
(__arm_vrmulhq_m_u16): Remove.
(__arm_vrmulhq_x_s8): Remove.
(__arm_vrmulhq_x_s16): Remove.
(__arm_vrmulhq_x_s32): Remove.
(__arm_vrmulhq_x_u8): Remove.
(__arm_vrmulhq_x_u16): Remove.
(__arm_vrmulhq_x_u32): Remove.
(__arm_vrmulhq): Remove.
(__arm_vrmulhq_m): Remove.
(__arm_vrmulhq_x): Remove.
2023-05-03 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (MVE_INT_SU_BINARY): New.
(mve_insn): Add vabdq, vhaddq, vhsubq, vmulhq, vqaddq, vqdmulhq,
vqrdmulhq, vqrshlq, vqshlq, vqsubq, vrhaddq, vrmulhq, vrshlq.
(supf): Add VQDMULHQ_S, VQRDMULHQ_S.
* config/arm/mve.md (mve_vabdq_<supf><mode>)
(@mve_vhaddq_<supf><mode>, mve_vhsubq_<supf><mode>)
(mve_vmulhq_<supf><mode>, mve_vqaddq_<supf><mode>)
(mve_vqdmulhq_s<mode>, mve_vqrdmulhq_s<mode>)
(mve_vqrshlq_<supf><mode>, mve_vqshlq_<supf><mode>)
(mve_vqsubq_<supf><mode>, @mve_vrhaddq_<supf><mode>)
(mve_vrmulhq_<supf><mode>, mve_vrshlq_<supf><mode>): Merge into
...
(@mve_<mve_insn>q_<supf><mode>): ... this.
* config/arm/vec-common.md (avg<mode>3_floor, uavg<mode>3_floor)
(avg<mode>3_ceil, uavg<mode>3_ceil): Use gen_mve_q instead of
gen_mve_vhaddq / gen_mve_vrhaddq.
2023-05-03 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (MVE_INT_SU_M_N_BINARY): New.
(mve_insn): Add vhaddq, vhsubq, vmlaq, vmlasq, vqaddq, vqdmlahq,
vqdmlashq, vqdmulhq, vqrdmlahq, vqrdmlashq, vqrdmulhq, vqsubq.
(supf): Add VQDMLAHQ_M_N_S, VQDMLASHQ_M_N_S, VQRDMLAHQ_M_N_S,
VQRDMLASHQ_M_N_S, VQDMULHQ_M_N_S, VQRDMULHQ_M_N_S.
* config/arm/mve.md (mve_vhaddq_m_n_<supf><mode>)
(mve_vhsubq_m_n_<supf><mode>, mve_vmlaq_m_n_<supf><mode>)
(mve_vmlasq_m_n_<supf><mode>, mve_vqaddq_m_n_<supf><mode>)
(mve_vqdmlahq_m_n_s<mode>, mve_vqdmlashq_m_n_s<mode>)
(mve_vqrdmlahq_m_n_s<mode>, mve_vqrdmlashq_m_n_s<mode>)
(mve_vqsubq_m_n_<supf><mode>, mve_vqdmulhq_m_n_s<mode>)
(mve_vqrdmulhq_m_n_s<mode>): Merge into ...
(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
2023-05-03 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (MVE_INT_SU_N_BINARY): New.
(mve_insn): Add vhaddq, vhsubq, vqaddq, vqdmulhq, vqrdmulhq,
vqsubq.
(supf): Add VQDMULHQ_N_S, VQRDMULHQ_N_S.
* config/arm/mve.md (mve_vhaddq_n_<supf><mode>)
(mve_vhsubq_n_<supf><mode>, mve_vqaddq_n_<supf><mode>)
(mve_vqdmulhq_n_s<mode>, mve_vqrdmulhq_n_s<mode>)
(mve_vqsubq_n_<supf><mode>): Merge into ...
(@mve_<mve_insn>q_n_<supf><mode>): ... this.
2023-05-03 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (MVE_INT_SU_M_BINARY): New.
(mve_insn): Add vabdq, vhaddq, vhsubq, vmaxq, vminq, vmulhq,
vqaddq, vqdmladhq, vqdmladhxq, vqdmlsdhq, vqdmlsdhxq, vqdmulhq,
vqrdmladhq, vqrdmladhxq, vqrdmlsdhq, vqrdmlsdhxq, vqrdmulhq,
vqrshlq, vqshlq, vqsubq, vrhaddq, vrmulhq, vrshlq, vshlq.
(supf): Add VQDMLADHQ_M_S, VQDMLADHXQ_M_S, VQDMLSDHQ_M_S,
VQDMLSDHXQ_M_S, VQDMULHQ_M_S, VQRDMLADHQ_M_S, VQRDMLADHXQ_M_S,
VQRDMLSDHQ_M_S, VQRDMLSDHXQ_M_S, VQRDMULHQ_M_S.
* config/arm/mve.md (@mve_<mve_insn>q_m_<supf><mode>): New.
(mve_vshlq_m_<supf><mode>): Merged into
@mve_<mve_insn>q_m_<supf><mode>.
(mve_vabdq_m_<supf><mode>): Likewise.
(mve_vhaddq_m_<supf><mode>): Likewise.
(mve_vhsubq_m_<supf><mode>): Likewise.
(mve_vmaxq_m_<supf><mode>): Likewise.
(mve_vminq_m_<supf><mode>): Likewise.
(mve_vmulhq_m_<supf><mode>): Likewise.
(mve_vqaddq_m_<supf><mode>): Likewise.
(mve_vqrshlq_m_<supf><mode>): Likewise.
(mve_vqshlq_m_<supf><mode>): Likewise.
(mve_vqsubq_m_<supf><mode>): Likewise.
(mve_vrhaddq_m_<supf><mode>): Likewise.
(mve_vrmulhq_m_<supf><mode>): Likewise.
(mve_vrshlq_m_<supf><mode>): Likewise.
(mve_vqdmladhq_m_s<mode>): Likewise.
(mve_vqdmladhxq_m_s<mode>): Likewise.
(mve_vqdmlsdhq_m_s<mode>): Likewise.
(mve_vqdmlsdhxq_m_s<mode>): Likewise.
(mve_vqdmulhq_m_s<mode>): Likewise.
(mve_vqrdmladhq_m_s<mode>): Likewise.
(mve_vqrdmladhxq_m_s<mode>): Likewise.
(mve_vqrdmlsdhq_m_s<mode>): Likewise.
(mve_vqrdmlsdhxq_m_s<mode>): Likewise.
(mve_vqrdmulhq_m_s<mode>): Likewise.
2023-05-03 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (FUNCTION_WITHOUT_M_N): New. (vcreateq): New.
* config/arm/arm-mve-builtins-base.def (vcreateq): New.
* config/arm/arm-mve-builtins-base.h (vcreateq): New.
* config/arm/arm_mve.h (vcreateq_f16): Remove.
(vcreateq_f32): Remove.
(vcreateq_u8): Remove.
(vcreateq_u16): Remove.
(vcreateq_u32): Remove.
(vcreateq_u64): Remove.
(vcreateq_s8): Remove.
(vcreateq_s16): Remove.
(vcreateq_s32): Remove.
(vcreateq_s64): Remove.
(__arm_vcreateq_u8): Remove.
(__arm_vcreateq_u16): Remove.
(__arm_vcreateq_u32): Remove.
(__arm_vcreateq_u64): Remove.
(__arm_vcreateq_s8): Remove.
(__arm_vcreateq_s16): Remove.
(__arm_vcreateq_s32): Remove.
(__arm_vcreateq_s64): Remove.
(__arm_vcreateq_f16): Remove.
(__arm_vcreateq_f32): Remove.
2023-05-03 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (MVE_FP_CREATE_ONLY): New.
(mve_insn): Add VCREATEQ_S, VCREATEQ_U, VCREATEQ_F.
* config/arm/mve.md (mve_vcreateq_f<mode>): Rename into ...
(@mve_<mve_insn>q_f<mode>): ... this.
(mve_vcreateq_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_<supf><mode>): ... this.
2023-05-03 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-shapes.cc (create): New.
* config/arm/arm-mve-builtins-shapes.h: (create): New.
2023-05-03 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-functions.h (class
unspec_mve_function_exact_insn): New.
2023-05-03 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (FUNCTION_WITH_RTX_M_N_NO_N_F): New.
(vorrq): New.
* config/arm/arm-mve-builtins-base.def (vorrq): New.
* config/arm/arm-mve-builtins-base.h (vorrq): New.
* config/arm/arm-mve-builtins.cc
(function_instance::has_inactive_argument): Handle vorrq.
* config/arm/arm_mve.h (vorrq): Remove.
(vorrq_m_n): Remove.
(vorrq_m): Remove.
(vorrq_x): Remove.
(vorrq_u8): Remove.
(vorrq_s8): Remove.
(vorrq_u16): Remove.
(vorrq_s16): Remove.
(vorrq_u32): Remove.
(vorrq_s32): Remove.
(vorrq_n_u16): Remove.
(vorrq_f16): Remove.
(vorrq_n_s16): Remove.
(vorrq_n_u32): Remove.
(vorrq_f32): Remove.
(vorrq_n_s32): Remove.
(vorrq_m_n_s16): Remove.
(vorrq_m_n_u16): Remove.
(vorrq_m_n_s32): Remove.
(vorrq_m_n_u32): Remove.
(vorrq_m_s8): Remove.
(vorrq_m_s32): Remove.
(vorrq_m_s16): Remove.
(vorrq_m_u8): Remove.
(vorrq_m_u32): Remove.
(vorrq_m_u16): Remove.
(vorrq_m_f32): Remove.
(vorrq_m_f16): Remove.
(vorrq_x_s8): Remove.
(vorrq_x_s16): Remove.
(vorrq_x_s32): Remove.
(vorrq_x_u8): Remove.
(vorrq_x_u16): Remove.
(vorrq_x_u32): Remove.
(vorrq_x_f16): Remove.
(vorrq_x_f32): Remove.
(__arm_vorrq_u8): Remove.
(__arm_vorrq_s8): Remove.
(__arm_vorrq_u16): Remove.
(__arm_vorrq_s16): Remove.
(__arm_vorrq_u32): Remove.
(__arm_vorrq_s32): Remove.
(__arm_vorrq_n_u16): Remove.
(__arm_vorrq_n_s16): Remove.
(__arm_vorrq_n_u32): Remove.
(__arm_vorrq_n_s32): Remove.
(__arm_vorrq_m_n_s16): Remove.
(__arm_vorrq_m_n_u16): Remove.
(__arm_vorrq_m_n_s32): Remove.
(__arm_vorrq_m_n_u32): Remove.
(__arm_vorrq_m_s8): Remove.
(__arm_vorrq_m_s32): Remove.
(__arm_vorrq_m_s16): Remove.
(__arm_vorrq_m_u8): Remove.
(__arm_vorrq_m_u32): Remove.
(__arm_vorrq_m_u16): Remove.
(__arm_vorrq_x_s8): Remove.
(__arm_vorrq_x_s16): Remove.
(__arm_vorrq_x_s32): Remove.
(__arm_vorrq_x_u8): Remove.
(__arm_vorrq_x_u16): Remove.
(__arm_vorrq_x_u32): Remove.
(__arm_vorrq_f16): Remove.
(__arm_vorrq_f32): Remove.
(__arm_vorrq_m_f32): Remove.
(__arm_vorrq_m_f16): Remove.
(__arm_vorrq_x_f16): Remove.
(__arm_vorrq_x_f32): Remove.
(__arm_vorrq): Remove.
(__arm_vorrq_m_n): Remove.
(__arm_vorrq_m): Remove.
(__arm_vorrq_x): Remove.
2023-05-03 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-shapes.cc (binary_orrq): New.
* config/arm/arm-mve-builtins-shapes.h (binary_orrq): New.
* config/arm/arm-mve-builtins.cc (preds_m_or_none): Remove static.
* config/arm/arm-mve-builtins.h (preds_m_or_none): Declare.
2023-05-03 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (FUNCTION_WITH_RTX_M): New.
(vandq,veorq): New.
* config/arm/arm-mve-builtins-base.def (vandq, veorq): New.
* config/arm/arm-mve-builtins-base.h (vandq, veorq): New.
* config/arm/arm_mve.h (vandq): Remove.
(vandq_m): Remove.
(vandq_x): Remove.
(vandq_u8): Remove.
(vandq_s8): Remove.
(vandq_u16): Remove.
(vandq_s16): Remove.
(vandq_u32): Remove.
(vandq_s32): Remove.
(vandq_f16): Remove.
(vandq_f32): Remove.
(vandq_m_s8): Remove.
(vandq_m_s32): Remove.
(vandq_m_s16): Remove.
(vandq_m_u8): Remove.
(vandq_m_u32): Remove.
(vandq_m_u16): Remove.
(vandq_m_f32): Remove.
(vandq_m_f16): Remove.
(vandq_x_s8): Remove.
(vandq_x_s16): Remove.
(vandq_x_s32): Remove.
(vandq_x_u8): Remove.
(vandq_x_u16): Remove.
(vandq_x_u32): Remove.
(vandq_x_f16): Remove.
(vandq_x_f32): Remove.
(__arm_vandq_u8): Remove.
(__arm_vandq_s8): Remove.
(__arm_vandq_u16): Remove.
(__arm_vandq_s16): Remove.
(__arm_vandq_u32): Remove.
(__arm_vandq_s32): Remove.
(__arm_vandq_m_s8): Remove.
(__arm_vandq_m_s32): Remove.
(__arm_vandq_m_s16): Remove.
(__arm_vandq_m_u8): Remove.
(__arm_vandq_m_u32): Remove.
(__arm_vandq_m_u16): Remove.
(__arm_vandq_x_s8): Remove.
(__arm_vandq_x_s16): Remove.
(__arm_vandq_x_s32): Remove.
(__arm_vandq_x_u8): Remove.
(__arm_vandq_x_u16): Remove.
(__arm_vandq_x_u32): Remove.
(__arm_vandq_f16): Remove.
(__arm_vandq_f32): Remove.
(__arm_vandq_m_f32): Remove.
(__arm_vandq_m_f16): Remove.
(__arm_vandq_x_f16): Remove.
(__arm_vandq_x_f32): Remove.
(__arm_vandq): Remove.
(__arm_vandq_m): Remove.
(__arm_vandq_x): Remove.
(veorq_m): Remove.
(veorq_x): Remove.
(veorq_u8): Remove.
(veorq_s8): Remove.
(veorq_u16): Remove.
(veorq_s16): Remove.
(veorq_u32): Remove.
(veorq_s32): Remove.
(veorq_f16): Remove.
(veorq_f32): Remove.
(veorq_m_s8): Remove.
(veorq_m_s32): Remove.
(veorq_m_s16): Remove.
(veorq_m_u8): Remove.
(veorq_m_u32): Remove.
(veorq_m_u16): Remove.
(veorq_m_f32): Remove.
(veorq_m_f16): Remove.
(veorq_x_s8): Remove.
(veorq_x_s16): Remove.
(veorq_x_s32): Remove.
(veorq_x_u8): Remove.
(veorq_x_u16): Remove.
(veorq_x_u32): Remove.
(veorq_x_f16): Remove.
(veorq_x_f32): Remove.
(__arm_veorq_u8): Remove.
(__arm_veorq_s8): Remove.
(__arm_veorq_u16): Remove.
(__arm_veorq_s16): Remove.
(__arm_veorq_u32): Remove.
(__arm_veorq_s32): Remove.
(__arm_veorq_m_s8): Remove.
(__arm_veorq_m_s32): Remove.
(__arm_veorq_m_s16): Remove.
(__arm_veorq_m_u8): Remove.
(__arm_veorq_m_u32): Remove.
(__arm_veorq_m_u16): Remove.
(__arm_veorq_x_s8): Remove.
(__arm_veorq_x_s16): Remove.
(__arm_veorq_x_s32): Remove.
(__arm_veorq_x_u8): Remove.
(__arm_veorq_x_u16): Remove.
(__arm_veorq_x_u32): Remove.
(__arm_veorq_f16): Remove.
(__arm_veorq_f32): Remove.
(__arm_veorq_m_f32): Remove.
(__arm_veorq_m_f16): Remove.
(__arm_veorq_x_f16): Remove.
(__arm_veorq_x_f32): Remove.
(__arm_veorq): Remove.
(__arm_veorq_m): Remove.
(__arm_veorq_x): Remove.
2023-05-03 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (MVE_INT_M_BINARY_LOGIC)
(MVE_FP_M_BINARY_LOGIC): New.
(MVE_INT_M_N_BINARY_LOGIC): New.
(MVE_INT_N_BINARY_LOGIC): New.
(mve_insn): Add vand, veor, vorr, vbic.
* config/arm/mve.md (mve_vandq_m_<supf><mode>)
(mve_veorq_m_<supf><mode>, mve_vorrq_m_<supf><mode>)
(mve_vbicq_m_<supf><mode>): Merge into ...
(@mve_<mve_insn>q_m_<supf><mode>): ... this.
(mve_vandq_m_f<mode>, mve_veorq_m_f<mode>, mve_vorrq_m_f<mode>)
(mve_vbicq_m_f<mode>): Merge into ...
(@mve_<mve_insn>q_m_f<mode>): ... this.
(mve_vorrq_n_<supf><mode>)
(mve_vbicq_n_<supf><mode>): Merge into ...
(@mve_<mve_insn>q_n_<supf><mode>): ... this.
(mve_vorrq_m_n_<supf><mode>, mve_vbicq_m_n_<supf><mode>): Merge
into ...
(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
2023-05-03 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-shapes.cc (binary): New.
* config/arm/arm-mve-builtins-shapes.h (binary): New.
2023-05-03 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (FUNCTION_WITH_RTX_M_N):
New.
(vaddq, vmulq, vsubq): New.
* config/arm/arm-mve-builtins-base.def (vaddq, vmulq, vsubq): New.
* config/arm/arm-mve-builtins-base.h (vaddq, vmulq, vsubq): New.
* config/arm/arm_mve.h (vaddq): Remove.
(vaddq_m): Remove.
(vaddq_x): Remove.
(vaddq_n_u8): Remove.
(vaddq_n_s8): Remove.
(vaddq_n_u16): Remove.
(vaddq_n_s16): Remove.
(vaddq_n_u32): Remove.
(vaddq_n_s32): Remove.
(vaddq_n_f16): Remove.
(vaddq_n_f32): Remove.
(vaddq_m_n_s8): Remove.
(vaddq_m_n_s32): Remove.
(vaddq_m_n_s16): Remove.
(vaddq_m_n_u8): Remove.
(vaddq_m_n_u32): Remove.
(vaddq_m_n_u16): Remove.
(vaddq_m_s8): Remove.
(vaddq_m_s32): Remove.
(vaddq_m_s16): Remove.
(vaddq_m_u8): Remove.
(vaddq_m_u32): Remove.
(vaddq_m_u16): Remove.
(vaddq_m_f32): Remove.
(vaddq_m_f16): Remove.
(vaddq_m_n_f32): Remove.
(vaddq_m_n_f16): Remove.
(vaddq_s8): Remove.
(vaddq_s16): Remove.
(vaddq_s32): Remove.
(vaddq_u8): Remove.
(vaddq_u16): Remove.
(vaddq_u32): Remove.
(vaddq_f16): Remove.
(vaddq_f32): Remove.
(vaddq_x_s8): Remove.
(vaddq_x_s16): Remove.
(vaddq_x_s32): Remove.
(vaddq_x_n_s8): Remove.
(vaddq_x_n_s16): Remove.
(vaddq_x_n_s32): Remove.
(vaddq_x_u8): Remove.
(vaddq_x_u16): Remove.
(vaddq_x_u32): Remove.
(vaddq_x_n_u8): Remove.
(vaddq_x_n_u16): Remove.
(vaddq_x_n_u32): Remove.
(vaddq_x_f16): Remove.
(vaddq_x_f32): Remove.
(vaddq_x_n_f16): Remove.
(vaddq_x_n_f32): Remove.
(__arm_vaddq_n_u8): Remove.
(__arm_vaddq_n_s8): Remove.
(__arm_vaddq_n_u16): Remove.
(__arm_vaddq_n_s16): Remove.
(__arm_vaddq_n_u32): Remove.
(__arm_vaddq_n_s32): Remove.
(__arm_vaddq_m_n_s8): Remove.
(__arm_vaddq_m_n_s32): Remove.
(__arm_vaddq_m_n_s16): Remove.
(__arm_vaddq_m_n_u8): Remove.
(__arm_vaddq_m_n_u32): Remove.
(__arm_vaddq_m_n_u16): Remove.
(__arm_vaddq_m_s8): Remove.
(__arm_vaddq_m_s32): Remove.
(__arm_vaddq_m_s16): Remove.
(__arm_vaddq_m_u8): Remove.
(__arm_vaddq_m_u32): Remove.
(__arm_vaddq_m_u16): Remove.
(__arm_vaddq_s8): Remove.
(__arm_vaddq_s16): Remove.
(__arm_vaddq_s32): Remove.
(__arm_vaddq_u8): Remove.
(__arm_vaddq_u16): Remove.
(__arm_vaddq_u32): Remove.
(__arm_vaddq_x_s8): Remove.
(__arm_vaddq_x_s16): Remove.
(__arm_vaddq_x_s32): Remove.
(__arm_vaddq_x_n_s8): Remove.
(__arm_vaddq_x_n_s16): Remove.
(__arm_vaddq_x_n_s32): Remove.
(__arm_vaddq_x_u8): Remove.
(__arm_vaddq_x_u16): Remove.
(__arm_vaddq_x_u32): Remove.
(__arm_vaddq_x_n_u8): Remove.
(__arm_vaddq_x_n_u16): Remove.
(__arm_vaddq_x_n_u32): Remove.
(__arm_vaddq_n_f16): Remove.
(__arm_vaddq_n_f32): Remove.
(__arm_vaddq_m_f32): Remove.
(__arm_vaddq_m_f16): Remove.
(__arm_vaddq_m_n_f32): Remove.
(__arm_vaddq_m_n_f16): Remove.
(__arm_vaddq_f16): Remove.
(__arm_vaddq_f32): Remove.
(__arm_vaddq_x_f16): Remove.
(__arm_vaddq_x_f32): Remove.
(__arm_vaddq_x_n_f16): Remove.
(__arm_vaddq_x_n_f32): Remove.
(__arm_vaddq): Remove.
(__arm_vaddq_m): Remove.
(__arm_vaddq_x): Remove.
(vmulq): Remove.
(vmulq_m): Remove.
(vmulq_x): Remove.
(vmulq_u8): Remove.
(vmulq_n_u8): Remove.
(vmulq_s8): Remove.
(vmulq_n_s8): Remove.
(vmulq_u16): Remove.
(vmulq_n_u16): Remove.
(vmulq_s16): Remove.
(vmulq_n_s16): Remove.
(vmulq_u32): Remove.
(vmulq_n_u32): Remove.
(vmulq_s32): Remove.
(vmulq_n_s32): Remove.
(vmulq_n_f16): Remove.
(vmulq_f16): Remove.
(vmulq_n_f32): Remove.
(vmulq_f32): Remove.
(vmulq_m_n_s8): Remove.
(vmulq_m_n_s32): Remove.
(vmulq_m_n_s16): Remove.
(vmulq_m_n_u8): Remove.
(vmulq_m_n_u32): Remove.
(vmulq_m_n_u16): Remove.
(vmulq_m_s8): Remove.
(vmulq_m_s32): Remove.
(vmulq_m_s16): Remove.
(vmulq_m_u8): Remove.
(vmulq_m_u32): Remove.
(vmulq_m_u16): Remove.
(vmulq_m_f32): Remove.
(vmulq_m_f16): Remove.
(vmulq_m_n_f32): Remove.
(vmulq_m_n_f16): Remove.
(vmulq_x_s8): Remove.
(vmulq_x_s16): Remove.
(vmulq_x_s32): Remove.
(vmulq_x_n_s8): Remove.
(vmulq_x_n_s16): Remove.
(vmulq_x_n_s32): Remove.
(vmulq_x_u8): Remove.
(vmulq_x_u16): Remove.
(vmulq_x_u32): Remove.
(vmulq_x_n_u8): Remove.
(vmulq_x_n_u16): Remove.
(vmulq_x_n_u32): Remove.
(vmulq_x_f16): Remove.
(vmulq_x_f32): Remove.
(vmulq_x_n_f16): Remove.
(vmulq_x_n_f32): Remove.
(__arm_vmulq_u8): Remove.
(__arm_vmulq_n_u8): Remove.
(__arm_vmulq_s8): Remove.
(__arm_vmulq_n_s8): Remove.
(__arm_vmulq_u16): Remove.
(__arm_vmulq_n_u16): Remove.
(__arm_vmulq_s16): Remove.
(__arm_vmulq_n_s16): Remove.
(__arm_vmulq_u32): Remove.
(__arm_vmulq_n_u32): Remove.
(__arm_vmulq_s32): Remove.
(__arm_vmulq_n_s32): Remove.
(__arm_vmulq_m_n_s8): Remove.
(__arm_vmulq_m_n_s32): Remove.
(__arm_vmulq_m_n_s16): Remove.
(__arm_vmulq_m_n_u8): Remove.
(__arm_vmulq_m_n_u32): Remove.
(__arm_vmulq_m_n_u16): Remove.
(__arm_vmulq_m_s8): Remove.
(__arm_vmulq_m_s32): Remove.
(__arm_vmulq_m_s16): Remove.
(__arm_vmulq_m_u8): Remove.
(__arm_vmulq_m_u32): Remove.
(__arm_vmulq_m_u16): Remove.
(__arm_vmulq_x_s8): Remove.
(__arm_vmulq_x_s16): Remove.
(__arm_vmulq_x_s32): Remove.
(__arm_vmulq_x_n_s8): Remove.
(__arm_vmulq_x_n_s16): Remove.
(__arm_vmulq_x_n_s32): Remove.
(__arm_vmulq_x_u8): Remove.
(__arm_vmulq_x_u16): Remove.
(__arm_vmulq_x_u32): Remove.
(__arm_vmulq_x_n_u8): Remove.
(__arm_vmulq_x_n_u16): Remove.
(__arm_vmulq_x_n_u32): Remove.
(__arm_vmulq_n_f16): Remove.
(__arm_vmulq_f16): Remove.
(__arm_vmulq_n_f32): Remove.
(__arm_vmulq_f32): Remove.
(__arm_vmulq_m_f32): Remove.
(__arm_vmulq_m_f16): Remove.
(__arm_vmulq_m_n_f32): Remove.
(__arm_vmulq_m_n_f16): Remove.
(__arm_vmulq_x_f16): Remove.
(__arm_vmulq_x_f32): Remove.
(__arm_vmulq_x_n_f16): Remove.
(__arm_vmulq_x_n_f32): Remove.
(__arm_vmulq): Remove.
(__arm_vmulq_m): Remove.
(__arm_vmulq_x): Remove.
(vsubq): Remove.
(vsubq_m): Remove.
(vsubq_x): Remove.
(vsubq_n_f16): Remove.
(vsubq_n_f32): Remove.
(vsubq_u8): Remove.
(vsubq_n_u8): Remove.
(vsubq_s8): Remove.
(vsubq_n_s8): Remove.
(vsubq_u16): Remove.
(vsubq_n_u16): Remove.
(vsubq_s16): Remove.
(vsubq_n_s16): Remove.
(vsubq_u32): Remove.
(vsubq_n_u32): Remove.
(vsubq_s32): Remove.
(vsubq_n_s32): Remove.
(vsubq_f16): Remove.
(vsubq_f32): Remove.
(vsubq_m_s8): Remove.
(vsubq_m_u8): Remove.
(vsubq_m_s16): Remove.
(vsubq_m_u16): Remove.
(vsubq_m_s32): Remove.
(vsubq_m_u32): Remove.
(vsubq_m_n_s8): Remove.
(vsubq_m_n_s32): Remove.
(vsubq_m_n_s16): Remove.
(vsubq_m_n_u8): Remove.
(vsubq_m_n_u32): Remove.
(vsubq_m_n_u16): Remove.
(vsubq_m_f32): Remove.
(vsubq_m_f16): Remove.
(vsubq_m_n_f32): Remove.
(vsubq_m_n_f16): Remove.
(vsubq_x_s8): Remove.
(vsubq_x_s16): Remove.
(vsubq_x_s32): Remove.
(vsubq_x_n_s8): Remove.
(vsubq_x_n_s16): Remove.
(vsubq_x_n_s32): Remove.
(vsubq_x_u8): Remove.
(vsubq_x_u16): Remove.
(vsubq_x_u32): Remove.
(vsubq_x_n_u8): Remove.
(vsubq_x_n_u16): Remove.
(vsubq_x_n_u32): Remove.
(vsubq_x_f16): Remove.
(vsubq_x_f32): Remove.
(vsubq_x_n_f16): Remove.
(vsubq_x_n_f32): Remove.
(__arm_vsubq_u8): Remove.
(__arm_vsubq_n_u8): Remove.
(__arm_vsubq_s8): Remove.
(__arm_vsubq_n_s8): Remove.
(__arm_vsubq_u16): Remove.
(__arm_vsubq_n_u16): Remove.
(__arm_vsubq_s16): Remove.
(__arm_vsubq_n_s16): Remove.
(__arm_vsubq_u32): Remove.
(__arm_vsubq_n_u32): Remove.
(__arm_vsubq_s32): Remove.
(__arm_vsubq_n_s32): Remove.
(__arm_vsubq_m_s8): Remove.
(__arm_vsubq_m_u8): Remove.
(__arm_vsubq_m_s16): Remove.
(__arm_vsubq_m_u16): Remove.
(__arm_vsubq_m_s32): Remove.
(__arm_vsubq_m_u32): Remove.
(__arm_vsubq_m_n_s8): Remove.
(__arm_vsubq_m_n_s32): Remove.
(__arm_vsubq_m_n_s16): Remove.
(__arm_vsubq_m_n_u8): Remove.
(__arm_vsubq_m_n_u32): Remove.
(__arm_vsubq_m_n_u16): Remove.
(__arm_vsubq_x_s8): Remove.
(__arm_vsubq_x_s16): Remove.
(__arm_vsubq_x_s32): Remove.
(__arm_vsubq_x_n_s8): Remove.
(__arm_vsubq_x_n_s16): Remove.
(__arm_vsubq_x_n_s32): Remove.
(__arm_vsubq_x_u8): Remove.
(__arm_vsubq_x_u16): Remove.
(__arm_vsubq_x_u32): Remove.
(__arm_vsubq_x_n_u8): Remove.
(__arm_vsubq_x_n_u16): Remove.
(__arm_vsubq_x_n_u32): Remove.
(__arm_vsubq_n_f16): Remove.
(__arm_vsubq_n_f32): Remove.
(__arm_vsubq_f16): Remove.
(__arm_vsubq_f32): Remove.
(__arm_vsubq_m_f32): Remove.
(__arm_vsubq_m_f16): Remove.
(__arm_vsubq_m_n_f32): Remove.
(__arm_vsubq_m_n_f16): Remove.
(__arm_vsubq_x_f16): Remove.
(__arm_vsubq_x_f32): Remove.
(__arm_vsubq_x_n_f16): Remove.
(__arm_vsubq_x_n_f32): Remove.
(__arm_vsubq): Remove.
(__arm_vsubq_m): Remove.
(__arm_vsubq_x): Remove.
* config/arm/arm_mve_builtins.def (vsubq_u, vsubq_s, vsubq_f):
Remove.
(vmulq_u, vmulq_s, vmulq_f): Remove.
* config/arm/mve.md (mve_vsubq_<supf><mode>): Remove.
(mve_vmulq_<supf><mode>): Remove.
2023-05-03 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/iterators.md (MVE_INT_BINARY_RTX, MVE_INT_M_BINARY)
(MVE_INT_M_N_BINARY, MVE_INT_N_BINARY, MVE_FP_M_BINARY)
(MVE_FP_M_N_BINARY, MVE_FP_N_BINARY, mve_addsubmul, mve_insn): New
iterators.
* config/arm/mve.md
(mve_vsubq_n_f<mode>, mve_vaddq_n_f<mode>, mve_vmulq_n_f<mode>):
Factorize into ...
(@mve_<mve_insn>q_n_f<mode>): ... this.
(mve_vaddq_n_<supf><mode>, mve_vmulq_n_<supf><mode>)
(mve_vsubq_n_<supf><mode>): Factorize into ...
(@mve_<mve_insn>q_n_<supf><mode>): ... this.
(mve_vaddq<mode>, mve_vmulq<mode>, mve_vsubq<mode>): Factorize
into ...
(mve_<mve_addsubmul>q<mode>): ... this.
(mve_vaddq_f<mode>, mve_vmulq_f<mode>, mve_vsubq_f<mode>):
Factorize into ...
(mve_<mve_addsubmul>q_f<mode>): ... this.
(mve_vaddq_m_<supf><mode>, mve_vmulq_m_<supf><mode>)
(mve_vsubq_m_<supf><mode>): Factorize into ...
(@mve_<mve_insn>q_m_<supf><mode>): ... this,
(mve_vaddq_m_n_<supf><mode>, mve_vmulq_m_n_<supf><mode>)
(mve_vsubq_m_n_<supf><mode>): Factorize into ...
(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
(mve_vaddq_m_f<mode>, mve_vmulq_m_f<mode>, mve_vsubq_m_f<mode>):
Factorize into ...
(@mve_<mve_insn>q_m_f<mode>): ... this.
(mve_vaddq_m_n_f<mode>, mve_vmulq_m_n_f<mode>)
(mve_vsubq_m_n_f<mode>): Factorize into ...
(@mve_<mve_insn>q_m_n_f<mode>): ... this.
2023-05-03 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-functions.h (class
unspec_based_mve_function_base): New.
(class unspec_based_mve_function_exact_insn): New.
2023-05-03 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-shapes.cc (binary_opt_n): New.
* config/arm/arm-mve-builtins-shapes.h (binary_opt_n): New.
2023-05-03 Murray Steele <murray.steele@arm.com>
Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (class
vuninitializedq_impl): New.
* config/arm/arm-mve-builtins-base.def (vuninitializedq): New.
* config/arm/arm-mve-builtins-base.h (vuninitializedq): New
declaration.
* config/arm/arm-mve-builtins-shapes.cc (inherent): New.
* config/arm/arm-mve-builtins-shapes.h (inherent): New
declaration.
* config/arm/arm_mve_types.h (__arm_vuninitializedq): Move to ...
* config/arm/arm_mve.h (__arm_vuninitializedq): ... here.
(__arm_vuninitializedq_u8): Remove.
(__arm_vuninitializedq_u16): Remove.
(__arm_vuninitializedq_u32): Remove.
(__arm_vuninitializedq_u64): Remove.
(__arm_vuninitializedq_s8): Remove.
(__arm_vuninitializedq_s16): Remove.
(__arm_vuninitializedq_s32): Remove.
(__arm_vuninitializedq_s64): Remove.
(__arm_vuninitializedq_f16): Remove.
(__arm_vuninitializedq_f32): Remove.
2023-05-03 Murray Steele <murray.steele@arm.com>
Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-mve-builtins-base.cc (vreinterpretq_impl): New class.
* config/arm/arm-mve-builtins-base.def: Define vreinterpretq.
* config/arm/arm-mve-builtins-base.h (vreinterpretq): New declaration.
* config/arm/arm-mve-builtins-shapes.cc (parse_element_type): New function.
(parse_type): Likewise.
(parse_signature): Likewise.
(build_one): Likewise.
(build_all): Likewise.
(overloaded_base): New struct.
(unary_convert_def): Likewise.
* config/arm/arm-mve-builtins-shapes.h (unary_convert): Declare.
* config/arm/arm-mve-builtins.cc (TYPES_reinterpret_signed1): New
macro.
(TYPES_reinterpret_unsigned1): Likewise.
(TYPES_reinterpret_integer): Likewise.
(TYPES_reinterpret_integer1): Likewise.
(TYPES_reinterpret_float1): Likewise.
(TYPES_reinterpret_float): Likewise.
(reinterpret_integer): New.
(reinterpret_float): New.
(handle_arm_mve_h): Register builtins.
* config/arm/arm_mve.h (vreinterpretq_s16): Remove.
(vreinterpretq_s32): Likewise.
(vreinterpretq_s64): Likewise.
(vreinterpretq_s8): Likewise.
(vreinterpretq_u16): Likewise.
(vreinterpretq_u32): Likewise.
(vreinterpretq_u64): Likewise.
(vreinterpretq_u8): Likewise.
(vreinterpretq_f16): Likewise.
(vreinterpretq_f32): Likewise.
(vreinterpretq_s16_s32): Likewise.
(vreinterpretq_s16_s64): Likewise.
(vreinterpretq_s16_s8): Likewise.
(vreinterpretq_s16_u16): Likewise.
(vreinterpretq_s16_u32): Likewise.
(vreinterpretq_s16_u64): Likewise.
(vreinterpretq_s16_u8): Likewise.
(vreinterpretq_s32_s16): Likewise.
(vreinterpretq_s32_s64): Likewise.
(vreinterpretq_s32_s8): Likewise.
(vreinterpretq_s32_u16): Likewise.
(vreinterpretq_s32_u32): Likewise.
(vreinterpretq_s32_u64): Likewise.
(vreinterpretq_s32_u8): Likewise.
(vreinterpretq_s64_s16): Likewise.
(vreinterpretq_s64_s32): Likewise.
(vreinterpretq_s64_s8): Likewise.
(vreinterpretq_s64_u16): Likewise.
(vreinterpretq_s64_u32): Likewise.
(vreinterpretq_s64_u64): Likewise.
(vreinterpretq_s64_u8): Likewise.
(vreinterpretq_s8_s16): Likewise.
(vreinterpretq_s8_s32): Likewise.
(vreinterpretq_s8_s64): Likewise.
(vreinterpretq_s8_u16): Likewise.
(vreinterpretq_s8_u32): Likewise.
(vreinterpretq_s8_u64): Likewise.
(vreinterpretq_s8_u8): Likewise.
(vreinterpretq_u16_s16): Likewise.
(vreinterpretq_u16_s32): Likewise.
(vreinterpretq_u16_s64): Likewise.
(vreinterpretq_u16_s8): Likewise.
(vreinterpretq_u16_u32): Likewise.
(vreinterpretq_u16_u64): Likewise.
(vreinterpretq_u16_u8): Likewise.
(vreinterpretq_u32_s16): Likewise.
(vreinterpretq_u32_s32): Likewise.
(vreinterpretq_u32_s64): Likewise.
(vreinterpretq_u32_s8): Likewise.
(vreinterpretq_u32_u16): Likewise.
(vreinterpretq_u32_u64): Likewise.
(vreinterpretq_u32_u8): Likewise.
(vreinterpretq_u64_s16): Likewise.
(vreinterpretq_u64_s32): Likewise.
(vreinterpretq_u64_s64): Likewise.
(vreinterpretq_u64_s8): Likewise.
(vreinterpretq_u64_u16): Likewise.
(vreinterpretq_u64_u32): Likewise.
(vreinterpretq_u64_u8): Likewise.
(vreinterpretq_u8_s16): Likewise.
(vreinterpretq_u8_s32): Likewise.
(vreinterpretq_u8_s64): Likewise.
(vreinterpretq_u8_s8): Likewise.
(vreinterpretq_u8_u16): Likewise.
(vreinterpretq_u8_u32): Likewise.
(vreinterpretq_u8_u64): Likewise.
(vreinterpretq_s32_f16): Likewise.
(vreinterpretq_s32_f32): Likewise.
(vreinterpretq_u16_f16): Likewise.
(vreinterpretq_u16_f32): Likewise.
(vreinterpretq_u32_f16): Likewise.
(vreinterpretq_u32_f32): Likewise.
(vreinterpretq_u64_f16): Likewise.
(vreinterpretq_u64_f32): Likewise.
(vreinterpretq_u8_f16): Likewise.
(vreinterpretq_u8_f32): Likewise.
(vreinterpretq_f16_f32): Likewise.
(vreinterpretq_f16_s16): Likewise.
(vreinterpretq_f16_s32): Likewise.
(vreinterpretq_f16_s64): Likewise.
(vreinterpretq_f16_s8): Likewise.
(vreinterpretq_f16_u16): Likewise.
(vreinterpretq_f16_u32): Likewise.
(vreinterpretq_f16_u64): Likewise.
(vreinterpretq_f16_u8): Likewise.
(vreinterpretq_f32_f16): Likewise.
(vreinterpretq_f32_s16): Likewise.
(vreinterpretq_f32_s32): Likewise.
(vreinterpretq_f32_s64): Likewise.
(vreinterpretq_f32_s8): Likewise.
(vreinterpretq_f32_u16): Likewise.
(vreinterpretq_f32_u32): Likewise.
(vreinterpretq_f32_u64): Likewise.
(vreinterpretq_f32_u8): Likewise.
(vreinterpretq_s16_f16): Likewise.
(vreinterpretq_s16_f32): Likewise.
(vreinterpretq_s64_f16): Likewise.
(vreinterpretq_s64_f32): Likewise.
(vreinterpretq_s8_f16): Likewise.
(vreinterpretq_s8_f32): Likewise.
(__arm_vreinterpretq_f16): Likewise.
(__arm_vreinterpretq_f32): Likewise.
(__arm_vreinterpretq_s16): Likewise.
(__arm_vreinterpretq_s32): Likewise.
(__arm_vreinterpretq_s64): Likewise.
(__arm_vreinterpretq_s8): Likewise.
(__arm_vreinterpretq_u16): Likewise.
(__arm_vreinterpretq_u32): Likewise.
(__arm_vreinterpretq_u64): Likewise.
(__arm_vreinterpretq_u8): Likewise.
* config/arm/arm_mve_types.h (__arm_vreinterpretq_s16_s32): Remove.
(__arm_vreinterpretq_s16_s64): Likewise.
(__arm_vreinterpretq_s16_s8): Likewise.
(__arm_vreinterpretq_s16_u16): Likewise.
(__arm_vreinterpretq_s16_u32): Likewise.
(__arm_vreinterpretq_s16_u64): Likewise.
(__arm_vreinterpretq_s16_u8): Likewise.
(__arm_vreinterpretq_s32_s16): Likewise.
(__arm_vreinterpretq_s32_s64): Likewise.
(__arm_vreinterpretq_s32_s8): Likewise.
(__arm_vreinterpretq_s32_u16): Likewise.
(__arm_vreinterpretq_s32_u32): Likewise.
(__arm_vreinterpretq_s32_u64): Likewise.
(__arm_vreinterpretq_s32_u8): Likewise.
(__arm_vreinterpretq_s64_s16): Likewise.
(__arm_vreinterpretq_s64_s32): Likewise.
(__arm_vreinterpretq_s64_s8): Likewise.
(__arm_vreinterpretq_s64_u16): Likewise.
(__arm_vreinterpretq_s64_u32): Likewise.
(__arm_vreinterpretq_s64_u64): Likewise.
(__arm_vreinterpretq_s64_u8): Likewise.
(__arm_vreinterpretq_s8_s16): Likewise.
(__arm_vreinterpretq_s8_s32): Likewise.
(__arm_vreinterpretq_s8_s64): Likewise.
(__arm_vreinterpretq_s8_u16): Likewise.
(__arm_vreinterpretq_s8_u32): Likewise.
(__arm_vreinterpretq_s8_u64): Likewise.
(__arm_vreinterpretq_s8_u8): Likewise.
(__arm_vreinterpretq_u16_s16): Likewise.
(__arm_vreinterpretq_u16_s32): Likewise.
(__arm_vreinterpretq_u16_s64): Likewise.
(__arm_vreinterpretq_u16_s8): Likewise.
(__arm_vreinterpretq_u16_u32): Likewise.
(__arm_vreinterpretq_u16_u64): Likewise.
(__arm_vreinterpretq_u16_u8): Likewise.
(__arm_vreinterpretq_u32_s16): Likewise.
(__arm_vreinterpretq_u32_s32): Likewise.
(__arm_vreinterpretq_u32_s64): Likewise.
(__arm_vreinterpretq_u32_s8): Likewise.
(__arm_vreinterpretq_u32_u16): Likewise.
(__arm_vreinterpretq_u32_u64): Likewise.
(__arm_vreinterpretq_u32_u8): Likewise.
(__arm_vreinterpretq_u64_s16): Likewise.
(__arm_vreinterpretq_u64_s32): Likewise.
(__arm_vreinterpretq_u64_s64): Likewise.
(__arm_vreinterpretq_u64_s8): Likewise.
(__arm_vreinterpretq_u64_u16): Likewise.
(__arm_vreinterpretq_u64_u32): Likewise.
(__arm_vreinterpretq_u64_u8): Likewise.
(__arm_vreinterpretq_u8_s16): Likewise.
(__arm_vreinterpretq_u8_s32): Likewise.
(__arm_vreinterpretq_u8_s64): Likewise.
(__arm_vreinterpretq_u8_s8): Likewise.
(__arm_vreinterpretq_u8_u16): Likewise.
(__arm_vreinterpretq_u8_u32): Likewise.
(__arm_vreinterpretq_u8_u64): Likewise.
(__arm_vreinterpretq_s32_f16): Likewise.
(__arm_vreinterpretq_s32_f32): Likewise.
(__arm_vreinterpretq_s16_f16): Likewise.
(__arm_vreinterpretq_s16_f32): Likewise.
(__arm_vreinterpretq_s64_f16): Likewise.
(__arm_vreinterpretq_s64_f32): Likewise.
(__arm_vreinterpretq_s8_f16): Likewise.
(__arm_vreinterpretq_s8_f32): Likewise.
(__arm_vreinterpretq_u16_f16): Likewise.
(__arm_vreinterpretq_u16_f32): Likewise.
(__arm_vreinterpretq_u32_f16): Likewise.
(__arm_vreinterpretq_u32_f32): Likewise.
(__arm_vreinterpretq_u64_f16): Likewise.
(__arm_vreinterpretq_u64_f32): Likewise.
(__arm_vreinterpretq_u8_f16): Likewise.
(__arm_vreinterpretq_u8_f32): Likewise.
(__arm_vreinterpretq_f16_f32): Likewise.
(__arm_vreinterpretq_f16_s16): Likewise.
(__arm_vreinterpretq_f16_s32): Likewise.
(__arm_vreinterpretq_f16_s64): Likewise.
(__arm_vreinterpretq_f16_s8): Likewise.
(__arm_vreinterpretq_f16_u16): Likewise.
(__arm_vreinterpretq_f16_u32): Likewise.
(__arm_vreinterpretq_f16_u64): Likewise.
(__arm_vreinterpretq_f16_u8): Likewise.
(__arm_vreinterpretq_f32_f16): Likewise.
(__arm_vreinterpretq_f32_s16): Likewise.
(__arm_vreinterpretq_f32_s32): Likewise.
(__arm_vreinterpretq_f32_s64): Likewise.
(__arm_vreinterpretq_f32_s8): Likewise.
(__arm_vreinterpretq_f32_u16): Likewise.
(__arm_vreinterpretq_f32_u32): Likewise.
(__arm_vreinterpretq_f32_u64): Likewise.
(__arm_vreinterpretq_f32_u8): Likewise.
(__arm_vreinterpretq_s16): Likewise.
(__arm_vreinterpretq_s32): Likewise.
(__arm_vreinterpretq_s64): Likewise.
(__arm_vreinterpretq_s8): Likewise.
(__arm_vreinterpretq_u16): Likewise.
(__arm_vreinterpretq_u32): Likewise.
(__arm_vreinterpretq_u64): Likewise.
(__arm_vreinterpretq_u8): Likewise.
(__arm_vreinterpretq_f16): Likewise.
(__arm_vreinterpretq_f32): Likewise.
* config/arm/mve.md (@arm_mve_reinterpret<mode>): New pattern.
* config/arm/unspecs.md: (REINTERPRET): New unspec.
2023-05-03 Murray Steele <murray.steele@arm.com>
Christophe Lyon <christophe.lyon@arm.com>
Christophe Lyon <christophe.lyon@arm.com
* config.gcc: Add arm-mve-builtins-base.o and
arm-mve-builtins-shapes.o to extra_objs.
* config/arm/arm-builtins.cc (arm_builtin_decl): Handle MVE builtin
numberspace.
(arm_expand_builtin): Likewise
(arm_check_builtin_call): Likewise
(arm_describe_resolver): Likewise.
* config/arm/arm-builtins.h (enum resolver_ident): Add
arm_mve_resolver.
* config/arm/arm-c.cc (arm_pragma_arm): Handle new pragma.
(arm_resolve_overloaded_builtin): Handle MVE builtins.
(arm_register_target_pragmas): Register arm_check_builtin_call.
* config/arm/arm-mve-builtins.cc (class registered_function): New
class.
(struct registered_function_hasher): New struct.
(pred_suffixes): New table.
(mode_suffixes): New table.
(type_suffix_info): New table.
(TYPES_float16): New.
(TYPES_all_float): New.
(TYPES_integer_8): New.
(TYPES_integer_8_16): New.
(TYPES_integer_16_32): New.
(TYPES_integer_32): New.
(TYPES_signed_16_32): New.
(TYPES_signed_32): New.
(TYPES_all_signed): New.
(TYPES_all_unsigned): New.
(TYPES_all_integer): New.
(TYPES_all_integer_with_64): New.
(DEF_VECTOR_TYPE): New.
(DEF_DOUBLE_TYPE): New.
(DEF_MVE_TYPES_ARRAY): New.
(all_integer): New.
(all_integer_with_64): New.
(float16): New.
(all_float): New.
(all_signed): New.
(all_unsigned): New.
(integer_8): New.
(integer_8_16): New.
(integer_16_32): New.
(integer_32): New.
(signed_16_32): New.
(signed_32): New.
(register_vector_type): Use void_type_node for mve.fp-only types when
mve.fp is not enabled.
(register_builtin_tuple_types): Likewise.
(handle_arm_mve_h): New function..
(matches_type_p): Likewise..
(report_out_of_range): Likewise.
(report_not_enum): Likewise.
(report_missing_float): Likewise.
(report_non_ice): Likewise.
(check_requires_float): Likewise.
(function_instance::hash): Likewise
(function_instance::call_properties): Likewise.
(function_instance::reads_global_state_p): Likewise.
(function_instance::modifies_global_state_p): Likewise.
(function_instance::could_trap_p): Likewise.
(function_instance::has_inactive_argument): Likewise.
(registered_function_hasher::hash): Likewise.
(registered_function_hasher::equal): Likewise.
(function_builder::function_builder): Likewise.
(function_builder::~function_builder): Likewise.
(function_builder::append_name): Likewise.
(function_builder::finish_name): Likewise.
(function_builder::get_name): Likewise.
(add_attribute): Likewise.
(function_builder::get_attributes): Likewise.
(function_builder::add_function): Likewise.
(function_builder::add_unique_function): Likewise.
(function_builder::add_overloaded_function): Likewise.
(function_builder::add_overloaded_functions): Likewise.
(function_builder::register_function_group): Likewise.
(function_call_info::function_call_info): Likewise.
(function_resolver::function_resolver): Likewise.
(function_resolver::get_vector_type): Likewise.
(function_resolver::get_scalar_type_name): Likewise.
(function_resolver::get_argument_type): Likewise.
(function_resolver::scalar_argument_p): Likewise.
(function_resolver::report_no_such_form): Likewise.
(function_resolver::lookup_form): Likewise.
(function_resolver::resolve_to): Likewise.
(function_resolver::infer_vector_or_tuple_type): Likewise.
(function_resolver::infer_vector_type): Likewise.
(function_resolver::require_vector_or_scalar_type): Likewise.
(function_resolver::require_vector_type): Likewise.
(function_resolver::require_matching_vector_type): Likewise.
(function_resolver::require_derived_vector_type): Likewise.
(function_resolver::require_derived_scalar_type): Likewise.
(function_resolver::require_integer_immediate): Likewise.
(function_resolver::require_scalar_type): Likewise.
(function_resolver::check_num_arguments): Likewise.
(function_resolver::check_gp_argument): Likewise.
(function_resolver::finish_opt_n_resolution): Likewise.
(function_resolver::resolve_unary): Likewise.
(function_resolver::resolve_unary_n): Likewise.
(function_resolver::resolve_uniform): Likewise.
(function_resolver::resolve_uniform_opt_n): Likewise.
(function_resolver::resolve): Likewise.
(function_checker::function_checker): Likewise.
(function_checker::argument_exists_p): Likewise.
(function_checker::require_immediate): Likewise.
(function_checker::require_immediate_enum): Likewise.
(function_checker::require_immediate_range): Likewise.
(function_checker::check): Likewise.
(gimple_folder::gimple_folder): Likewise.
(gimple_folder::fold): Likewise.
(function_expander::function_expander): Likewise.
(function_expander::direct_optab_handler): Likewise.
(function_expander::get_fallback_value): Likewise.
(function_expander::get_reg_target): Likewise.
(function_expander::add_output_operand): Likewise.
(function_expander::add_input_operand): Likewise.
(function_expander::add_integer_operand): Likewise.
(function_expander::generate_insn): Likewise.
(function_expander::use_exact_insn): Likewise.
(function_expander::use_unpred_insn): Likewise.
(function_expander::use_pred_x_insn): Likewise.
(function_expander::use_cond_insn): Likewise.
(function_expander::map_to_rtx_codes): Likewise.
(function_expander::expand): Likewise.
(resolve_overloaded_builtin): Likewise.
(check_builtin_call): Likewise.
(gimple_fold_builtin): Likewise.
(expand_builtin): Likewise.
(gt_ggc_mx): Likewise.
(gt_pch_nx): Likewise.
(gt_pch_nx): Likewise.
* config/arm/arm-mve-builtins.def(s8): Define new type suffix.
(s16): Likewise.
(s32): Likewise.
(s64): Likewise.
(u8): Likewise.
(u16): Likewise.
(u32): Likewise.
(u64): Likewise.
(f16): Likewise.
(f32): Likewise.
(n): New mode.
(offset): New mode.
* config/arm/arm-mve-builtins.h (MAX_TUPLE_SIZE): New constant.
(CP_READ_FPCR): Likewise.
(CP_RAISE_FP_EXCEPTIONS): Likewise.
(CP_READ_MEMORY): Likewise.
(CP_WRITE_MEMORY): Likewise.
(enum units_index): New enum.
(enum predication_index): New.
(enum type_class_index): New.
(enum mode_suffix_index): New enum.
(enum type_suffix_index): New.
(struct mode_suffix_info): New struct.
(struct type_suffix_info): New.
(struct function_group_info): Likewise.
(class function_instance): Likewise.
(class registered_function): Likewise.
(class function_builder): Likewise.
(class function_call_info): Likewise.
(class function_resolver): Likewise.
(class function_checker): Likewise.
(class gimple_folder): Likewise.
(class function_expander): Likewise.
(get_mve_pred16_t): Likewise.
(find_mode_suffix): New function.
(class function_base): Likewise.
(class function_shape): Likewise.
(function_instance::operator==): New function.
(function_instance::operator!=): Likewise.
(function_instance::vectors_per_tuple): Likewise.
(function_instance::mode_suffix): Likewise.
(function_instance::type_suffix): Likewise.
(function_instance::scalar_type): Likewise.
(function_instance::vector_type): Likewise.
(function_instance::tuple_type): Likewise.
(function_instance::vector_mode): Likewise.
(function_call_info::function_returns_void_p): Likewise.
(function_base::call_properties): Likewise.
* config/arm/arm-protos.h (enum arm_builtin_class): Add
ARM_BUILTIN_MVE.
(handle_arm_mve_h): New.
(resolve_overloaded_builtin): New.
(check_builtin_call): New.
(gimple_fold_builtin): New.
(expand_builtin): New.
* config/arm/arm.cc (TARGET_GIMPLE_FOLD_BUILTIN): Define as
arm_gimple_fold_builtin.
(arm_gimple_fold_builtin): New function.
* config/arm/arm_mve.h: Use new arm_mve.h pragma.
* config/arm/predicates.md (arm_any_register_operand): New predicate.
* config/arm/t-arm: (arm-mve-builtins.o): Add includes.
(arm-mve-builtins-shapes.o): New target.
(arm-mve-builtins-base.o): New target.
* config/arm/arm-mve-builtins-base.cc: New file.
* config/arm/arm-mve-builtins-base.def: New file.
* config/arm/arm-mve-builtins-base.h: New file.
* config/arm/arm-mve-builtins-functions.h: New file.
* config/arm/arm-mve-builtins-shapes.cc: New file.
* config/arm/arm-mve-builtins-shapes.h: New file.
2023-05-03 Murray Steele <murray.steele@arm.com>
Christophe Lyon <christophe.lyon@arm.com>
Christophe Lyon <christophe.lyon@arm.com>
* config/arm/arm-builtins.cc (arm_general_add_builtin_function):
New function.
(arm_init_builtin): Use arm_general_add_builtin_function instead
of arm_add_builtin_function.
(arm_init_acle_builtins): Likewise.
(arm_init_mve_builtins): Likewise.
(arm_init_crypto_builtins): Likewise.
(arm_init_builtins): Likewise.
(arm_general_builtin_decl): New function.
(arm_builtin_decl): Defer to numberspace-specialized functions.
(arm_expand_builtin_args): Rename into arm_general_expand_builtin_args.
(arm_expand_builtin_1): Rename into arm_general_expand_builtin_1 and ...
(arm_general_expand_builtin_1): ... specialize for general builtins.
(arm_expand_acle_builtin): Use arm_general_expand_builtin
instead of arm_expand_builtin.
(arm_expand_mve_builtin): Likewise.
(arm_expand_neon_builtin): Likewise.
(arm_expand_vfp_builtin): Likewise.
(arm_general_expand_builtin): New function.
(arm_expand_builtin): Specialize for general builtins.
(arm_general_check_builtin_call): New function.
(arm_check_builtin_call): Specialize for general builtins.
(arm_describe_resolver): Validate numberspace.
(arm_cde_end_args): Likewise.
* config/arm/arm-protos.h (enum arm_builtin_class): New enum.
(ARM_BUILTIN_SHIFT, ARM_BUILTIN_CLASS): New constants.
2023-05-03 Martin Liska <mliska@suse.cz>
PR target/109713
* config/riscv/sync.md: Add gcc_unreachable to a switch.
2023-05-03 Richard Biener <rguenther@suse.de>
* tree-ssa-loop-split.cc (split_at_bb_p): Avoid last_stmt.
(patch_loop_exit): Likewise.
(connect_loops): Likewise.
(split_loop): Likewise.
(control_dep_semi_invariant_p): Likewise.
(do_split_loop_on_cond): Likewise.
(split_loop_on_cond): Likewise.
* tree-ssa-loop-unswitch.cc (find_unswitching_predicates_for_bb):
Likewise.
(simplify_loop_version): Likewise.
(evaluate_bbs): Likewise.
(find_loop_guard): Likewise.
(clean_up_after_unswitching): Likewise.
* tree-ssa-math-opts.cc (maybe_optimize_guarding_check):
Likewise.
(optimize_spaceship): Take a gcond * argument, avoid
last_stmt.
(math_opts_dom_walker::after_dom_children): Adjust call to
optimize_spaceship.
* tree-vrp.cc (maybe_set_nonzero_bits): Avoid last_stmt.
* value-pointer-equiv.cc (pointer_equiv_analyzer::visit_edge):
Likewise.
2023-05-03 Andreas Schwab <schwab@suse.de>
* config/riscv/linux.h (LIB_SPEC): Don't redefine.
2023-05-03 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vector-builtins-bases.cc (fold_fault_load):
New function.
(class vlseg): New class.
(class vsseg): Ditto.
(class vlsseg): Ditto.
(class vssseg): Ditto.
(class seg_indexed_load): Ditto.
(class seg_indexed_store): Ditto.
(class vlsegff): Ditto.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def (vlseg):
Ditto.
(vsseg): Ditto.
(vlsseg): Ditto.
(vssseg): Ditto.
(vluxseg): Ditto.
(vloxseg): Ditto.
(vsuxseg): Ditto.
(vsoxseg): Ditto.
(vlsegff): Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc (struct
seg_loadstore_def): Ditto.
(struct seg_indexed_loadstore_def): Ditto.
(struct seg_fault_load_def): Ditto.
(SHAPE): Ditto.
* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
* config/riscv/riscv-vector-builtins.cc
(function_builder::append_nf): New function.
* config/riscv/riscv-vector-builtins.def (vfloat32m1x2_t):
Change ptr from double into float.
(vfloat32m1x3_t): Ditto.
(vfloat32m1x4_t): Ditto.
(vfloat32m1x5_t): Ditto.
(vfloat32m1x6_t): Ditto.
(vfloat32m1x7_t): Ditto.
(vfloat32m1x8_t): Ditto.
(vfloat32m2x2_t): Ditto.
(vfloat32m2x3_t): Ditto.
(vfloat32m2x4_t): Ditto.
(vfloat32m4x2_t): Ditto.
* config/riscv/riscv-vector-builtins.h: Add segment intrinsics.
* config/riscv/riscv-vsetvl.cc (fault_first_load_p): Adapt for
segment ff load.
* config/riscv/riscv.md: Add segment instructions.
* config/riscv/vector-iterators.md: Support segment intrinsics.
* config/riscv/vector.md (@pred_unit_strided_load<mode>): New
pattern.
(@pred_unit_strided_store<mode>): Ditto.
(@pred_strided_load<mode>): Ditto.
(@pred_strided_store<mode>): Ditto.
(@pred_fault_load<mode>): Ditto.
(@pred_indexed_<order>load<V1T:mode><V1I:mode>): Ditto.
(@pred_indexed_<order>load<V2T:mode><V2I:mode>): Ditto.
(@pred_indexed_<order>load<V4T:mode><V4I:mode>): Ditto.
(@pred_indexed_<order>load<V8T:mode><V8I:mode>): Ditto.
(@pred_indexed_<order>load<V16T:mode><V16I:mode>): Ditto.
(@pred_indexed_<order>load<V32T:mode><V32I:mode>): Ditto.
(@pred_indexed_<order>load<V64T:mode><V64I:mode>): Ditto.
(@pred_indexed_<order>store<V1T:mode><V1I:mode>): Ditto.
(@pred_indexed_<order>store<V2T:mode><V2I:mode>): Ditto.
(@pred_indexed_<order>store<V4T:mode><V4I:mode>): Ditto.
(@pred_indexed_<order>store<V8T:mode><V8I:mode>): Ditto.
(@pred_indexed_<order>store<V16T:mode><V16I:mode>): Ditto.
(@pred_indexed_<order>store<V32T:mode><V32I:mode>): Ditto.
(@pred_indexed_<order>store<V64T:mode><V64I:mode>): Ditto.
2023-05-03 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/genrvv-type-indexer.cc (valid_type): Adapt for
tuple type support.
(inttype): Ditto.
(floattype): Ditto.
(main): Ditto.
* config/riscv/riscv-vector-builtins-bases.cc: Ditto.
* config/riscv/riscv-vector-builtins-functions.def (vset): Add
tuple type vset.
(vget): Add tuple type vget.
* config/riscv/riscv-vector-builtins-types.def
(DEF_RVV_TUPLE_OPS): New macro.
(vint8mf8x2_t): Ditto.
(vuint8mf8x2_t): Ditto.
(vint8mf8x3_t): Ditto.
(vuint8mf8x3_t): Ditto.
(vint8mf8x4_t): Ditto.
(vuint8mf8x4_t): Ditto.
(vint8mf8x5_t): Ditto.
(vuint8mf8x5_t): Ditto.
(vint8mf8x6_t): Ditto.
(vuint8mf8x6_t): Ditto.
(vint8mf8x7_t): Ditto.
(vuint8mf8x7_t): Ditto.
(vint8mf8x8_t): Ditto.
(vuint8mf8x8_t): Ditto.
(vint8mf4x2_t): Ditto.
(vuint8mf4x2_t): Ditto.
(vint8mf4x3_t): Ditto.
(vuint8mf4x3_t): Ditto.
(vint8mf4x4_t): Ditto.
(vuint8mf4x4_t): Ditto.
(vint8mf4x5_t): Ditto.
(vuint8mf4x5_t): Ditto.
(vint8mf4x6_t): Ditto.
(vuint8mf4x6_t): Ditto.
(vint8mf4x7_t): Ditto.
(vuint8mf4x7_t): Ditto.
(vint8mf4x8_t): Ditto.
(vuint8mf4x8_t): Ditto.
(vint8mf2x2_t): Ditto.
(vuint8mf2x2_t): Ditto.
(vint8mf2x3_t): Ditto.
(vuint8mf2x3_t): Ditto.
(vint8mf2x4_t): Ditto.
(vuint8mf2x4_t): Ditto.
(vint8mf2x5_t): Ditto.
(vuint8mf2x5_t): Ditto.
(vint8mf2x6_t): Ditto.
(vuint8mf2x6_t): Ditto.
(vint8mf2x7_t): Ditto.
(vuint8mf2x7_t): Ditto.
(vint8mf2x8_t): Ditto.
(vuint8mf2x8_t): Ditto.
(vint8m1x2_t): Ditto.
(vuint8m1x2_t): Ditto.
(vint8m1x3_t): Ditto.
(vuint8m1x3_t): Ditto.
(vint8m1x4_t): Ditto.
(vuint8m1x4_t): Ditto.
(vint8m1x5_t): Ditto.
(vuint8m1x5_t): Ditto.
(vint8m1x6_t): Ditto.
(vuint8m1x6_t): Ditto.
(vint8m1x7_t): Ditto.
(vuint8m1x7_t): Ditto.
(vint8m1x8_t): Ditto.
(vuint8m1x8_t): Ditto.
(vint8m2x2_t): Ditto.
(vuint8m2x2_t): Ditto.
(vint8m2x3_t): Ditto.
(vuint8m2x3_t): Ditto.
(vint8m2x4_t): Ditto.
(vuint8m2x4_t): Ditto.
(vint8m4x2_t): Ditto.
(vuint8m4x2_t): Ditto.
(vint16mf4x2_t): Ditto.
(vuint16mf4x2_t): Ditto.
(vint16mf4x3_t): Ditto.
(vuint16mf4x3_t): Ditto.
(vint16mf4x4_t): Ditto.
(vuint16mf4x4_t): Ditto.
(vint16mf4x5_t): Ditto.
(vuint16mf4x5_t): Ditto.
(vint16mf4x6_t): Ditto.
(vuint16mf4x6_t): Ditto.
(vint16mf4x7_t): Ditto.
(vuint16mf4x7_t): Ditto.
(vint16mf4x8_t): Ditto.
(vuint16mf4x8_t): Ditto.
(vint16mf2x2_t): Ditto.
(vuint16mf2x2_t): Ditto.
(vint16mf2x3_t): Ditto.
(vuint16mf2x3_t): Ditto.
(vint16mf2x4_t): Ditto.
(vuint16mf2x4_t): Ditto.
(vint16mf2x5_t): Ditto.
(vuint16mf2x5_t): Ditto.
(vint16mf2x6_t): Ditto.
(vuint16mf2x6_t): Ditto.
(vint16mf2x7_t): Ditto.
(vuint16mf2x7_t): Ditto.
(vint16mf2x8_t): Ditto.
(vuint16mf2x8_t): Ditto.
(vint16m1x2_t): Ditto.
(vuint16m1x2_t): Ditto.
(vint16m1x3_t): Ditto.
(vuint16m1x3_t): Ditto.
(vint16m1x4_t): Ditto.
(vuint16m1x4_t): Ditto.
(vint16m1x5_t): Ditto.
(vuint16m1x5_t): Ditto.
(vint16m1x6_t): Ditto.
(vuint16m1x6_t): Ditto.
(vint16m1x7_t): Ditto.
(vuint16m1x7_t): Ditto.
(vint16m1x8_t): Ditto.
(vuint16m1x8_t): Ditto.
(vint16m2x2_t): Ditto.
(vuint16m2x2_t): Ditto.
(vint16m2x3_t): Ditto.
(vuint16m2x3_t): Ditto.
(vint16m2x4_t): Ditto.
(vuint16m2x4_t): Ditto.
(vint16m4x2_t): Ditto.
(vuint16m4x2_t): Ditto.
(vint32mf2x2_t): Ditto.
(vuint32mf2x2_t): Ditto.
(vint32mf2x3_t): Ditto.
(vuint32mf2x3_t): Ditto.
(vint32mf2x4_t): Ditto.
(vuint32mf2x4_t): Ditto.
(vint32mf2x5_t): Ditto.
(vuint32mf2x5_t): Ditto.
(vint32mf2x6_t): Ditto.
(vuint32mf2x6_t): Ditto.
(vint32mf2x7_t): Ditto.
(vuint32mf2x7_t): Ditto.
(vint32mf2x8_t): Ditto.
(vuint32mf2x8_t): Ditto.
(vint32m1x2_t): Ditto.
(vuint32m1x2_t): Ditto.
(vint32m1x3_t): Ditto.
(vuint32m1x3_t): Ditto.
(vint32m1x4_t): Ditto.
(vuint32m1x4_t): Ditto.
(vint32m1x5_t): Ditto.
(vuint32m1x5_t): Ditto.
(vint32m1x6_t): Ditto.
(vuint32m1x6_t): Ditto.
(vint32m1x7_t): Ditto.
(vuint32m1x7_t): Ditto.
(vint32m1x8_t): Ditto.
(vuint32m1x8_t): Ditto.
(vint32m2x2_t): Ditto.
(vuint32m2x2_t): Ditto.
(vint32m2x3_t): Ditto.
(vuint32m2x3_t): Ditto.
(vint32m2x4_t): Ditto.
(vuint32m2x4_t): Ditto.
(vint32m4x2_t): Ditto.
(vuint32m4x2_t): Ditto.
(vint64m1x2_t): Ditto.
(vuint64m1x2_t): Ditto.
(vint64m1x3_t): Ditto.
(vuint64m1x3_t): Ditto.
(vint64m1x4_t): Ditto.
(vuint64m1x4_t): Ditto.
(vint64m1x5_t): Ditto.
(vuint64m1x5_t): Ditto.
(vint64m1x6_t): Ditto.
(vuint64m1x6_t): Ditto.
(vint64m1x7_t): Ditto.
(vuint64m1x7_t): Ditto.
(vint64m1x8_t): Ditto.
(vuint64m1x8_t): Ditto.
(vint64m2x2_t): Ditto.
(vuint64m2x2_t): Ditto.
(vint64m2x3_t): Ditto.
(vuint64m2x3_t): Ditto.
(vint64m2x4_t): Ditto.
(vuint64m2x4_t): Ditto.
(vint64m4x2_t): Ditto.
(vuint64m4x2_t): Ditto.
(vfloat32mf2x2_t): Ditto.
(vfloat32mf2x3_t): Ditto.
(vfloat32mf2x4_t): Ditto.
(vfloat32mf2x5_t): Ditto.
(vfloat32mf2x6_t): Ditto.
(vfloat32mf2x7_t): Ditto.
(vfloat32mf2x8_t): Ditto.
(vfloat32m1x2_t): Ditto.
(vfloat32m1x3_t): Ditto.
(vfloat32m1x4_t): Ditto.
(vfloat32m1x5_t): Ditto.
(vfloat32m1x6_t): Ditto.
(vfloat32m1x7_t): Ditto.
(vfloat32m1x8_t): Ditto.
(vfloat32m2x2_t): Ditto.
(vfloat32m2x3_t): Ditto.
(vfloat32m2x4_t): Ditto.
(vfloat32m4x2_t): Ditto.
(vfloat64m1x2_t): Ditto.
(vfloat64m1x3_t): Ditto.
(vfloat64m1x4_t): Ditto.
(vfloat64m1x5_t): Ditto.
(vfloat64m1x6_t): Ditto.
(vfloat64m1x7_t): Ditto.
(vfloat64m1x8_t): Ditto.
(vfloat64m2x2_t): Ditto.
(vfloat64m2x3_t): Ditto.
(vfloat64m2x4_t): Ditto.
(vfloat64m4x2_t): Ditto.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_TUPLE_OPS):
Ditto.
(DEF_RVV_TYPE_INDEX): Ditto.
(rvv_arg_type_info::get_tuple_subpart_type): New function.
(DEF_RVV_TUPLE_TYPE): New macro.
* config/riscv/riscv-vector-builtins.def (DEF_RVV_TYPE_INDEX):
Adapt for tuple vget/vset support.
(vint8mf4_t): Ditto.
(vuint8mf4_t): Ditto.
(vint8mf2_t): Ditto.
(vuint8mf2_t): Ditto.
(vint8m1_t): Ditto.
(vuint8m1_t): Ditto.
(vint8m2_t): Ditto.
(vuint8m2_t): Ditto.
(vint8m4_t): Ditto.
(vuint8m4_t): Ditto.
(vint8m8_t): Ditto.
(vuint8m8_t): Ditto.
(vint16mf4_t): Ditto.
(vuint16mf4_t): Ditto.
(vint16mf2_t): Ditto.
(vuint16mf2_t): Ditto.
(vint16m1_t): Ditto.
(vuint16m1_t): Ditto.
(vint16m2_t): Ditto.
(vuint16m2_t): Ditto.
(vint16m4_t): Ditto.
(vuint16m4_t): Ditto.
(vint16m8_t): Ditto.
(vuint16m8_t): Ditto.
(vint32mf2_t): Ditto.
(vuint32mf2_t): Ditto.
(vint32m1_t): Ditto.
(vuint32m1_t): Ditto.
(vint32m2_t): Ditto.
(vuint32m2_t): Ditto.
(vint32m4_t): Ditto.
(vuint32m4_t): Ditto.
(vint32m8_t): Ditto.
(vuint32m8_t): Ditto.
(vint64m1_t): Ditto.
(vuint64m1_t): Ditto.
(vint64m2_t): Ditto.
(vuint64m2_t): Ditto.
(vint64m4_t): Ditto.
(vuint64m4_t): Ditto.
(vint64m8_t): Ditto.
(vuint64m8_t): Ditto.
(vfloat32mf2_t): Ditto.
(vfloat32m1_t): Ditto.
(vfloat32m2_t): Ditto.
(vfloat32m4_t): Ditto.
(vfloat32m8_t): Ditto.
(vfloat64m1_t): Ditto.
(vfloat64m2_t): Ditto.
(vfloat64m4_t): Ditto.
(vfloat64m8_t): Ditto.
(tuple_subpart): Add tuple subpart base type.
* config/riscv/riscv-vector-builtins.h (struct
rvv_arg_type_info): Ditto.
(tuple_type_field): New function.
2023-05-03 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-modes.def (RVV_TUPLE_MODES): New macro.
(RVV_TUPLE_PARTIAL_MODES): Ditto.
* config/riscv/riscv-protos.h (riscv_v_ext_tuple_mode_p): New
function.
(get_nf): Ditto.
(get_subpart_mode): Ditto.
(get_tuple_mode): Ditto.
(expand_tuple_move): Ditto.
* config/riscv/riscv-v.cc (ENTRY): New macro.
(TUPLE_ENTRY): Ditto.
(get_nf): New function.
(get_subpart_mode): Ditto.
(get_tuple_mode): Ditto.
(expand_tuple_move): Ditto.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_TUPLE_TYPE):
New macro.
(register_tuple_type): New function
* config/riscv/riscv-vector-builtins.def (DEF_RVV_TUPLE_TYPE):
New macro.
(vint8mf8x2_t): New macro.
(vuint8mf8x2_t): Ditto.
(vint8mf8x3_t): Ditto.
(vuint8mf8x3_t): Ditto.
(vint8mf8x4_t): Ditto.
(vuint8mf8x4_t): Ditto.
(vint8mf8x5_t): Ditto.
(vuint8mf8x5_t): Ditto.
(vint8mf8x6_t): Ditto.
(vuint8mf8x6_t): Ditto.
(vint8mf8x7_t): Ditto.
(vuint8mf8x7_t): Ditto.
(vint8mf8x8_t): Ditto.
(vuint8mf8x8_t): Ditto.
(vint8mf4x2_t): Ditto.
(vuint8mf4x2_t): Ditto.
(vint8mf4x3_t): Ditto.
(vuint8mf4x3_t): Ditto.
(vint8mf4x4_t): Ditto.
(vuint8mf4x4_t): Ditto.
(vint8mf4x5_t): Ditto.
(vuint8mf4x5_t): Ditto.
(vint8mf4x6_t): Ditto.
(vuint8mf4x6_t): Ditto.
(vint8mf4x7_t): Ditto.
(vuint8mf4x7_t): Ditto.
(vint8mf4x8_t): Ditto.
(vuint8mf4x8_t): Ditto.
(vint8mf2x2_t): Ditto.
(vuint8mf2x2_t): Ditto.
(vint8mf2x3_t): Ditto.
(vuint8mf2x3_t): Ditto.
(vint8mf2x4_t): Ditto.
(vuint8mf2x4_t): Ditto.
(vint8mf2x5_t): Ditto.
(vuint8mf2x5_t): Ditto.
(vint8mf2x6_t): Ditto.
(vuint8mf2x6_t): Ditto.
(vint8mf2x7_t): Ditto.
(vuint8mf2x7_t): Ditto.
(vint8mf2x8_t): Ditto.
(vuint8mf2x8_t): Ditto.
(vint8m1x2_t): Ditto.
(vuint8m1x2_t): Ditto.
(vint8m1x3_t): Ditto.
(vuint8m1x3_t): Ditto.
(vint8m1x4_t): Ditto.
(vuint8m1x4_t): Ditto.
(vint8m1x5_t): Ditto.
(vuint8m1x5_t): Ditto.
(vint8m1x6_t): Ditto.
(vuint8m1x6_t): Ditto.
(vint8m1x7_t): Ditto.
(vuint8m1x7_t): Ditto.
(vint8m1x8_t): Ditto.
(vuint8m1x8_t): Ditto.
(vint8m2x2_t): Ditto.
(vuint8m2x2_t): Ditto.
(vint8m2x3_t): Ditto.
(vuint8m2x3_t): Ditto.
(vint8m2x4_t): Ditto.
(vuint8m2x4_t): Ditto.
(vint8m4x2_t): Ditto.
(vuint8m4x2_t): Ditto.
(vint16mf4x2_t): Ditto.
(vuint16mf4x2_t): Ditto.
(vint16mf4x3_t): Ditto.
(vuint16mf4x3_t): Ditto.
(vint16mf4x4_t): Ditto.
(vuint16mf4x4_t): Ditto.
(vint16mf4x5_t): Ditto.
(vuint16mf4x5_t): Ditto.
(vint16mf4x6_t): Ditto.
(vuint16mf4x6_t): Ditto.
(vint16mf4x7_t): Ditto.
(vuint16mf4x7_t): Ditto.
(vint16mf4x8_t): Ditto.
(vuint16mf4x8_t): Ditto.
(vint16mf2x2_t): Ditto.
(vuint16mf2x2_t): Ditto.
(vint16mf2x3_t): Ditto.
(vuint16mf2x3_t): Ditto.
(vint16mf2x4_t): Ditto.
(vuint16mf2x4_t): Ditto.
(vint16mf2x5_t): Ditto.
(vuint16mf2x5_t): Ditto.
(vint16mf2x6_t): Ditto.
(vuint16mf2x6_t): Ditto.
(vint16mf2x7_t): Ditto.
(vuint16mf2x7_t): Ditto.
(vint16mf2x8_t): Ditto.
(vuint16mf2x8_t): Ditto.
(vint16m1x2_t): Ditto.
(vuint16m1x2_t): Ditto.
(vint16m1x3_t): Ditto.
(vuint16m1x3_t): Ditto.
(vint16m1x4_t): Ditto.
(vuint16m1x4_t): Ditto.
(vint16m1x5_t): Ditto.
(vuint16m1x5_t): Ditto.
(vint16m1x6_t): Ditto.
(vuint16m1x6_t): Ditto.
(vint16m1x7_t): Ditto.
(vuint16m1x7_t): Ditto.
(vint16m1x8_t): Ditto.
(vuint16m1x8_t): Ditto.
(vint16m2x2_t): Ditto.
(vuint16m2x2_t): Ditto.
(vint16m2x3_t): Ditto.
(vuint16m2x3_t): Ditto.
(vint16m2x4_t): Ditto.
(vuint16m2x4_t): Ditto.
(vint16m4x2_t): Ditto.
(vuint16m4x2_t): Ditto.
(vint32mf2x2_t): Ditto.
(vuint32mf2x2_t): Ditto.
(vint32mf2x3_t): Ditto.
(vuint32mf2x3_t): Ditto.
(vint32mf2x4_t): Ditto.
(vuint32mf2x4_t): Ditto.
(vint32mf2x5_t): Ditto.
(vuint32mf2x5_t): Ditto.
(vint32mf2x6_t): Ditto.
(vuint32mf2x6_t): Ditto.
(vint32mf2x7_t): Ditto.
(vuint32mf2x7_t): Ditto.
(vint32mf2x8_t): Ditto.
(vuint32mf2x8_t): Ditto.
(vint32m1x2_t): Ditto.
(vuint32m1x2_t): Ditto.
(vint32m1x3_t): Ditto.
(vuint32m1x3_t): Ditto.
(vint32m1x4_t): Ditto.
(vuint32m1x4_t): Ditto.
(vint32m1x5_t): Ditto.
(vuint32m1x5_t): Ditto.
(vint32m1x6_t): Ditto.
(vuint32m1x6_t): Ditto.
(vint32m1x7_t): Ditto.
(vuint32m1x7_t): Ditto.
(vint32m1x8_t): Ditto.
(vuint32m1x8_t): Ditto.
(vint32m2x2_t): Ditto.
(vuint32m2x2_t): Ditto.
(vint32m2x3_t): Ditto.
(vuint32m2x3_t): Ditto.
(vint32m2x4_t): Ditto.
(vuint32m2x4_t): Ditto.
(vint32m4x2_t): Ditto.
(vuint32m4x2_t): Ditto.
(vint64m1x2_t): Ditto.
(vuint64m1x2_t): Ditto.
(vint64m1x3_t): Ditto.
(vuint64m1x3_t): Ditto.
(vint64m1x4_t): Ditto.
(vuint64m1x4_t): Ditto.
(vint64m1x5_t): Ditto.
(vuint64m1x5_t): Ditto.
(vint64m1x6_t): Ditto.
(vuint64m1x6_t): Ditto.
(vint64m1x7_t): Ditto.
(vuint64m1x7_t): Ditto.
(vint64m1x8_t): Ditto.
(vuint64m1x8_t): Ditto.
(vint64m2x2_t): Ditto.
(vuint64m2x2_t): Ditto.
(vint64m2x3_t): Ditto.
(vuint64m2x3_t): Ditto.
(vint64m2x4_t): Ditto.
(vuint64m2x4_t): Ditto.
(vint64m4x2_t): Ditto.
(vuint64m4x2_t): Ditto.
(vfloat32mf2x2_t): Ditto.
(vfloat32mf2x3_t): Ditto.
(vfloat32mf2x4_t): Ditto.
(vfloat32mf2x5_t): Ditto.
(vfloat32mf2x6_t): Ditto.
(vfloat32mf2x7_t): Ditto.
(vfloat32mf2x8_t): Ditto.
(vfloat32m1x2_t): Ditto.
(vfloat32m1x3_t): Ditto.
(vfloat32m1x4_t): Ditto.
(vfloat32m1x5_t): Ditto.
(vfloat32m1x6_t): Ditto.
(vfloat32m1x7_t): Ditto.
(vfloat32m1x8_t): Ditto.
(vfloat32m2x2_t): Ditto.
(vfloat32m2x3_t): Ditto.
(vfloat32m2x4_t): Ditto.
(vfloat32m4x2_t): Ditto.
(vfloat64m1x2_t): Ditto.
(vfloat64m1x3_t): Ditto.
(vfloat64m1x4_t): Ditto.
(vfloat64m1x5_t): Ditto.
(vfloat64m1x6_t): Ditto.
(vfloat64m1x7_t): Ditto.
(vfloat64m1x8_t): Ditto.
(vfloat64m2x2_t): Ditto.
(vfloat64m2x3_t): Ditto.
(vfloat64m2x4_t): Ditto.
(vfloat64m4x2_t): Ditto.
* config/riscv/riscv-vector-builtins.h (DEF_RVV_TUPLE_TYPE):
Ditto.
* config/riscv/riscv-vector-switch.def (TUPLE_ENTRY): Ditto.
* config/riscv/riscv.cc (riscv_v_ext_tuple_mode_p): New
function.
(TUPLE_ENTRY): Ditto.
(riscv_v_ext_mode_p): New function.
(riscv_v_adjust_nunits): Add tuple mode adjustment.
(riscv_classify_address): Ditto.
(riscv_binary_cost): Ditto.
(riscv_rtx_costs): Ditto.
(riscv_secondary_memory_needed): Ditto.
(riscv_hard_regno_nregs): Ditto.
(riscv_hard_regno_mode_ok): Ditto.
(riscv_vector_mode_supported_p): Ditto.
(riscv_regmode_natural_size): Ditto.
(riscv_array_mode): New function.
(TARGET_ARRAY_MODE): New target hook.
* config/riscv/riscv.md: Add tuple modes.
* config/riscv/vector-iterators.md: Ditto.
* config/riscv/vector.md (mov<mode>): Add tuple modes data
movement.
(*mov<VT:mode>_<P:mode>): Ditto.
2023-05-03 Richard Biener <rguenther@suse.de>
* cse.cc (cse_insn): Track an equivalence to the destination
separately and delay using src_related for it.
2023-05-03 Richard Biener <rguenther@suse.de>
* cse.cc (HASH): Turn into inline function and mix
in another HASH_SHIFT bits.
(SAFE_HASH): Likewise.
2023-05-03 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR target/99195
* config/aarch64/aarch64-simd.md (aarch64_<sur>h<addsub><mode>): Rename to...
(aarch64_<sur>h<addsub><mode><vczle><vczbe>): ... This.
2023-05-03 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR target/99195
* config/aarch64/aarch64-simd.md (add<mode>3): Rename to...
(add<mode>3<vczle><vczbe>): ... This.
(sub<mode>3): Rename to...
(sub<mode>3<vczle><vczbe>): ... This.
(mul<mode>3): Rename to...
(mul<mode>3<vczle><vczbe>): ... This.
(*div<mode>3): Rename to...
(*div<mode>3<vczle><vczbe>): ... This.
(neg<mode>2): Rename to...
(neg<mode>2<vczle><vczbe>): ... This.
(abs<mode>2): Rename to...
(abs<mode>2<vczle><vczbe>): ... This.
(<frint_pattern><mode>2): Rename to...
(<frint_pattern><mode>2<vczle><vczbe>): ... This.
(<fmaxmin><mode>3): Rename to...
(<fmaxmin><mode>3<vczle><vczbe>): ... This.
(*sqrt<mode>2): Rename to...
(*sqrt<mode>2<vczle><vczbe>): ... This.
2023-05-03 Kito Cheng <kito.cheng@sifive.com>
* doc/md.texi (RISC-V): Add vr, vm, vd constarint.
2023-05-03 Martin Liska <mliska@suse.cz>
PR tree-optimization/109693
* value-range-storage.cc (vrange_allocator::vrange_allocator):
Remove unused field.
* value-range-storage.h: Likewise.
2023-05-02 Andrew Pinski <apinski@marvell.com>
* tree-ssa-phiopt.cc (move_stmt): New function.
(match_simplify_replacement): Use move_stmt instead
of the inlined version.
2023-05-02 Andrew Pinski <apinski@marvell.com>
* match.pd (a != 0 ? CLRSB(a) : CST -> CLRSB(a)): New
pattern.
2023-05-02 Andrew Pinski <apinski@marvell.com>
PR tree-optimization/109702
* match.pd: Fix "a != 0 ? FUNC(a) : CST" patterns
for FUNC of POPCOUNT BSWAP FFS PARITY CLZ and CTZ.
2023-05-02 Andrew Pinski <apinski@marvell.com>
PR target/109657
* config/aarch64/aarch64.md (*cmov<mode>_insn_m1): New
insn_and_split pattern.
2023-05-02 Patrick O'Neill <patrick@rivosinc.com>
* config/riscv/sync.md (atomic_load<mode>): Implement atomic
load mapping.
2023-05-02 Patrick O'Neill <patrick@rivosinc.com>
* config/riscv/sync.md (mem_thread_fence_1): Change fence
depending on the given memory model.
2023-05-02 Patrick O'Neill <patrick@rivosinc.com>
* config/riscv/riscv-protos.h (riscv_union_memmodels): Expose
riscv_union_memmodels function to sync.md.
* config/riscv/riscv.cc (riscv_union_memmodels): Add function to
get the union of two memmodels in sync.md.
(riscv_print_operand): Add %I and %J flags that output the
optimal LR/SC flag bits for a given memory model.
* config/riscv/sync.md: Remove static .aqrl bits on LR op/.rl
bits on SC op and replace with optimized %I, %J flags.
2023-05-02 Patrick O'Neill <patrick@rivosinc.com>
* config/riscv/riscv.cc
(riscv_memmodel_needs_amo_release): Change function name.
(riscv_print_operand): Remove unneeded %F case.
* config/riscv/sync.md: Remove unneeded fences.
2023-05-02 Patrick O'Neill <patrick@rivosinc.com>
PR target/89835
* config/riscv/sync.md (atomic_store<mode>): Use simple store
instruction in combination with fence(s).
2023-05-02 Patrick O'Neill <patrick@rivosinc.com>
* config/riscv/riscv.cc (riscv_print_operand): Change behavior
of %A to include release bits.
2023-05-02 Patrick O'Neill <patrick@rivosinc.com>
* config/riscv/sync.md (atomic_cas_value_strong<mode>): Change
FENCE/LR.aq/SC.aq into sequentially consistent LR.aqrl/SC.rl
pair.
2023-05-02 Patrick O'Neill <patrick@rivosinc.com>
* config/riscv/sync.md: Change LR.aq/SC.rl pairs into
sequentially consistent LR.aqrl/SC.rl pairs.
2023-05-02 Patrick O'Neill <patrick@rivosinc.com>
* config/riscv/riscv.cc: Remove MEMMODEL_SYNC_* cases and
sanitize memmodel input with memmodel_base.
2023-05-02 Yanzhang Wang <yanzhang.wang@intel.com>
Pan Li <pan2.li@intel.com>
PR target/109617
* config/riscv/vector-iterators.md: Support VNx2HI and VNX4DI when MIN_VLEN >= 128.
2023-05-02 Romain Naour <romain.naour@gmail.com>
* config/riscv/genrvv-type-indexer.cc: Use log2 from the C header, without
the namespace.
2023-05-02 Martin Liska <mliska@suse.cz>
* doc/invoke.texi: Update documentation based on param.opt file.
2023-05-02 Richard Biener <rguenther@suse.de>
PR tree-optimization/109672
* tree-vect-stmts.cc (vectorizable_operation): For plus,
minus and negate always check the vector mode is word mode.
2023-05-01 Andrew Pinski <apinski@marvell.com>
* tree-ssa-phiopt.cc: Update comment about
how the transformation are implemented.
2023-05-01 Jeff Law <jlaw@ventanamicro>
* config/stormy16/stormy16.cc (TARGET_LRA_P): Remove defintion.
2023-05-01 Jeff Law <jlaw@ventanamicro>
* config/cris/cris.cc (TARGET_LRA_P): Remove.
* config/epiphany/epiphany.cc (TARGET_LRA_P): Remove.
* config/iq2000/iq2000.cc (TARGET_LRA_P): Remove.
* config/m32r/m32r.cc (TARGET_LRA_P): Remove.
* config/microblaze/microblaze.cc (TARGET_LRA_P): Remove.
* config/mmix/mmix.cc (TARGET_LRA_P): Remove.
2023-05-01 Rasmus Villemoes <rasmus.villemoes@prevas.dk>
* print-tree.h (PRINT_DECL_REMAP_DEBUG): New flag.
* print-tree.cc (print_decl_identifier): Implement it.
* toplev.cc (output_stack_usage_1): Use it.
2023-05-01 Aldy Hernandez <aldyh@redhat.com>
* value-range.h (class int_range): Remove gt_ggc_mx and gt_pch_nx
friends.
2023-05-01 Aldy Hernandez <aldyh@redhat.com>
* value-range.h (irange::set_nonzero): Inline.
2023-05-01 Aldy Hernandez <aldyh@redhat.com>
* gimple-range-op.cc (cfn_ffs::fold_range): Use the correct
precision.
* gimple-ssa-warn-alloca.cc (alloca_call_type): Use <2> for
invalid_range, as it is an inverse range.
* tree-vrp.cc (find_case_label_range): Avoid trees.
* value-range.cc (irange::irange_set): Delete.
(irange::irange_set_1bit_anti_range): Delete.
(irange::irange_set_anti_range): Delete.
(irange::set): Cleanup.
* value-range.h (class irange): Remove irange_set,
irange_set_anti_range, irange_set_1bit_anti_range.
(irange::set_undefined): Remove set to m_type.
2023-05-01 Aldy Hernandez <aldyh@redhat.com>
* range-op.cc (update_known_bitmask): Adjust for irange containing
wide_ints internally.
* tree-ssanames.cc (set_nonzero_bits): Same.
* tree-ssanames.h (set_nonzero_bits): Same.
* value-range-storage.cc (irange_storage::set_irange): Same.
(irange_storage::get_irange): Same.
* value-range.cc (irange::operator=): Same.
(irange::irange_set): Same.
(irange::irange_set_1bit_anti_range): Same.
(irange::irange_set_anti_range): Same.
(irange::set): Same.
(irange::verify_range): Same.
(irange::contains_p): Same.
(irange::irange_single_pair_union): Same.
(irange::union_): Same.
(irange::irange_contains_p): Same.
(irange::intersect): Same.
(irange::invert): Same.
(irange::set_range_from_nonzero_bits): Same.
(irange::set_nonzero_bits): Same.
(mask_to_wi): Same.
(irange::intersect_nonzero_bits): Same.
(irange::union_nonzero_bits): Same.
(gt_ggc_mx): Same.
(gt_pch_nx): Same.
(tree_range): Same.
(range_tests_strict_enum): Same.
(range_tests_misc): Same.
(range_tests_nonzero_bits): Same.
* value-range.h (irange::type): Same.
(irange::varying_compatible_p): Same.
(irange::irange): Same.
(int_range::int_range): Same.
(irange::set_undefined): Same.
(irange::set_varying): Same.
(irange::lower_bound): Same.
(irange::upper_bound): Same.
2023-05-01 Aldy Hernandez <aldyh@redhat.com>
* gimple-range-fold.cc (tree_lower_bound): Delete.
(tree_upper_bound): Delete.
(vrp_val_max): Delete.
(vrp_val_min): Delete.
(fold_using_range::range_of_ssa_name_with_loop_info): Call
range_of_var_in_loop.
* vr-values.cc (valid_value_p): Delete.
(fix_overflow): Delete.
(get_scev_info): New.
(bounds_of_var_in_loop): Refactor into...
(induction_variable_may_overflow_p): ...this,
(range_from_loop_direction): ...and this,
(range_of_var_in_loop): ...and this.
* vr-values.h (bounds_of_var_in_loop): Delete.
(range_of_var_in_loop): New.
2023-05-01 Aldy Hernandez <aldyh@redhat.com>
* gimple-range-fold.cc (adjust_pointer_diff_expr): Rewrite with
irange_val*.
(vrp_val_max): New.
(vrp_val_min): New.
* gimple-range-op.cc (cfn_strlen::fold_range): Use irange_val_*.
* range-op.cc (max_limit): Same.
(min_limit): Same.
(plus_minus_ranges): Same.
(operator_rshift::op1_range): Same.
(operator_cast::inside_domain_p): Same.
* value-range.cc (vrp_val_is_max): Delete.
(vrp_val_is_min): Delete.
(range_tests_misc): Use irange_val_*.
* value-range.h (vrp_val_is_min): Delete.
(vrp_val_is_max): Delete.
(vrp_val_max): Delete.
(irange_val_min): New.
(vrp_val_min): Delete.
(irange_val_max): New.
* vr-values.cc (check_for_binary_op_overflow): Use irange_val_*.
2023-05-01 Aldy Hernandez <aldyh@redhat.com>
* fold-const.cc (expr_not_equal_to): Convert to irange wide_int API.
* gimple-fold.cc (size_must_be_zero_p): Same.
* gimple-loop-versioning.cc
(loop_versioning::prune_loop_conditions): Same.
* gimple-range-edge.cc (gcond_edge_range): Same.
(gimple_outgoing_range::calc_switch_ranges): Same.
* gimple-range-fold.cc (adjust_imagpart_expr): Same.
(adjust_realpart_expr): Same.
(fold_using_range::range_of_address): Same.
(fold_using_range::relation_fold_and_or): Same.
* gimple-range-gori.cc (gori_compute::gori_compute): Same.
(range_is_either_true_or_false): Same.
* gimple-range-op.cc (cfn_toupper_tolower::get_letter_range): Same.
(cfn_clz::fold_range): Same.
(cfn_ctz::fold_range): Same.
* gimple-range-tests.cc (class test_expr_eval): Same.
* gimple-ssa-warn-alloca.cc (alloca_call_type): Same.
* ipa-cp.cc (ipa_value_range_from_jfunc): Same.
(propagate_vr_across_jump_function): Same.
(decide_whether_version_node): Same.
* ipa-prop.cc (ipa_get_value_range): Same.
* ipa-prop.h (ipa_range_set_and_normalize): Same.
* range-op.cc (get_shift_range): Same.
(value_range_from_overflowed_bounds): Same.
(value_range_with_overflow): Same.
(create_possibly_reversed_range): Same.
(equal_op1_op2_relation): Same.
(not_equal_op1_op2_relation): Same.
(lt_op1_op2_relation): Same.
(le_op1_op2_relation): Same.
(gt_op1_op2_relation): Same.
(ge_op1_op2_relation): Same.
(operator_mult::op1_range): Same.
(operator_exact_divide::op1_range): Same.
(operator_lshift::op1_range): Same.
(operator_rshift::op1_range): Same.
(operator_cast::op1_range): Same.
(operator_logical_and::fold_range): Same.
(set_nonzero_range_from_mask): Same.
(operator_bitwise_or::op1_range): Same.
(operator_bitwise_xor::op1_range): Same.
(operator_addr_expr::fold_range): Same.
(pointer_plus_operator::wi_fold): Same.
(pointer_or_operator::op1_range): Same.
(INT): Same.
(UINT): Same.
(INT16): Same.
(UINT16): Same.
(SCHAR): Same.
(UCHAR): Same.
(range_op_cast_tests): Same.
(range_op_lshift_tests): Same.
(range_op_rshift_tests): Same.
(range_op_bitwise_and_tests): Same.
(range_relational_tests): Same.
* range.cc (range_zero): Same.
(range_nonzero): Same.
* range.h (range_true): Same.
(range_false): Same.
(range_true_and_false): Same.
* tree-data-ref.cc (split_constant_offset_1): Same.
* tree-ssa-loop-ch.cc (entry_loop_condition_is_static): Same.
* tree-ssa-loop-unswitch.cc (struct unswitch_predicate): Same.
(find_unswitching_predicates_for_bb): Same.
* tree-ssa-phiopt.cc (value_replacement): Same.
* tree-ssa-threadbackward.cc
(back_threader::find_taken_edge_cond): Same.
* tree-ssanames.cc (ssa_name_has_boolean_range): Same.
* tree-vrp.cc (find_case_label_range): Same.
* value-query.cc (range_query::get_tree_range): Same.
* value-range.cc (irange::set_nonnegative): Same.
(frange::contains_p): Same.
(frange::singleton_p): Same.
(frange::internal_singleton_p): Same.
(irange::irange_set): Same.
(irange::irange_set_1bit_anti_range): Same.
(irange::irange_set_anti_range): Same.
(irange::set): Same.
(irange::operator==): Same.
(irange::singleton_p): Same.
(irange::contains_p): Same.
(irange::set_range_from_nonzero_bits): Same.
(DEFINE_INT_RANGE_INSTANCE): Same.
(INT): Same.
(UINT): Same.
(SCHAR): Same.
(UINT128): Same.
(UCHAR): Same.
(range): New.
(tree_range): New.
(range_int): New.
(range_uint): New.
(range_uint128): New.
(range_uchar): New.
(range_char): New.
(build_range3): Convert to irange wide_int API.
(range_tests_irange3): Same.
(range_tests_int_range_max): Same.
(range_tests_strict_enum): Same.
(range_tests_misc): Same.
(range_tests_nonzero_bits): Same.
(range_tests_nan): Same.
(range_tests_signed_zeros): Same.
* value-range.h (Value_Range::Value_Range): Same.
(irange::set): Same.
(irange::nonzero_p): Same.
(irange::contains_p): Same.
(range_includes_zero_p): Same.
(irange::set_nonzero): Same.
(irange::set_zero): Same.
(contains_zero_p): Same.
(frange::contains_p): Same.
* vr-values.cc
(simplify_using_ranges::op_with_boolean_value_range_p): Same.
(bounds_of_var_in_loop): Same.
(simplify_using_ranges::legacy_fold_cond_overflow): Same.
2023-05-01 Aldy Hernandez <aldyh@redhat.com>
* value-range.cc (irange::irange_union): Rename to...
(irange::union_): ...this.
(irange::irange_intersect): Rename to...
(irange::intersect): ...this.
* value-range.h (irange::union_): Delete.
(irange::intersect): Delete.
2023-05-01 Aldy Hernandez <aldyh@redhat.com>
* vr-values.cc (bounds_of_var_in_loop): Convert to irange API.
2023-05-01 Aldy Hernandez <aldyh@redhat.com>
* vr-values.cc (check_for_binary_op_overflow): Tidy up by using
ranger API.
(compare_ranges): Delete.
(compare_range_with_value): Delete.
(bounds_of_var_in_loop): Tidy up by using ranger API.
(simplify_using_ranges::fold_cond_with_ops): Cleanup and rename
from vrp_evaluate_conditional_warnv_with_ops_using_ranges.
(simplify_using_ranges::legacy_fold_cond_overflow): Remove
strict_overflow_p and only_ranges.
(simplify_using_ranges::legacy_fold_cond): Adjust call to
legacy_fold_cond_overflow.
(simplify_using_ranges::simplify_abs_using_ranges): Adjust for
rename.
(range_fits_type_p): Rename value_range to irange.
* vr-values.h (range_fits_type_p): Adjust prototype.
2023-05-01 Aldy Hernandez <aldyh@redhat.com>
* value-range.cc (irange::irange_set_anti_range): Remove uses of
tree_lower_bound and tree_upper_bound.
(irange::verify_range): Same.
(irange::operator==): Same.
(irange::singleton_p): Same.
* value-range.h (irange::tree_lower_bound): Delete.
(irange::tree_upper_bound): Delete.
(irange::lower_bound): Delete.
(irange::upper_bound): Delete.
(irange::zero_p): Remove uses of tree_lower_bound and
tree_upper_bound.
2023-05-01 Aldy Hernandez <aldyh@redhat.com>
* tree-ssa-loop-niter.cc (refine_value_range_using_guard): Remove
kind() call.
(determine_value_range): Same.
(record_nonwrapping_iv): Same.
(infer_loop_bounds_from_signedness): Same.
(scev_var_range_cant_overflow): Same.
* tree-vrp.cc (operand_less_p): Delete.
* tree-vrp.h (operand_less_p): Delete.
* value-range.cc (get_legacy_range): Remove uses of deprecated API.
(irange::value_inside_range): Delete.
* value-range.h (vrange::kind): Delete.
(irange::num_pairs): Remove check of m_kind.
(irange::min): Delete.
(irange::max): Delete.
2023-05-01 Aldy Hernandez <aldyh@redhat.com>
* gimple-fold.cc (maybe_fold_comparisons_from_match_pd): Adjust
for vrange_storage.
* gimple-range-cache.cc (sbr_vector::sbr_vector): Same.
(sbr_vector::grow): Same.
(sbr_vector::set_bb_range): Same.
(sbr_vector::get_bb_range): Same.
(sbr_sparse_bitmap::sbr_sparse_bitmap): Same.
(sbr_sparse_bitmap::set_bb_range): Same.
(sbr_sparse_bitmap::get_bb_range): Same.
(block_range_cache::block_range_cache): Same.
(ssa_global_cache::ssa_global_cache): Same.
(ssa_global_cache::get_global_range): Same.
(ssa_global_cache::set_global_range): Same.
* gimple-range-cache.h: Same.
* gimple-range-edge.cc
(gimple_outgoing_range::gimple_outgoing_range): Same.
(gimple_outgoing_range::switch_edge_range): Same.
(gimple_outgoing_range::calc_switch_ranges): Same.
* gimple-range-edge.h: Same.
* gimple-range-infer.cc
(infer_range_manager::infer_range_manager): Same.
(infer_range_manager::get_nonzero): Same.
(infer_range_manager::maybe_adjust_range): Same.
(infer_range_manager::add_range): Same.
* gimple-range-infer.h: Rename obstack_vrange_allocator to
vrange_allocator.
* tree-core.h (struct irange_storage_slot): Remove.
(struct tree_ssa_name): Remove irange_info and frange_info. Make
range_info a pointer to vrange_storage.
* tree-ssanames.cc (range_info_fits_p): Adjust for vrange_storage.
(range_info_alloc): Same.
(range_info_free): Same.
(range_info_get_range): Same.
(range_info_set_range): Same.
(get_nonzero_bits): Same.
* value-query.cc (get_ssa_name_range_info): Same.
* value-range-storage.cc (class vrange_internal_alloc): New.
(class vrange_obstack_alloc): New.
(class vrange_ggc_alloc): New.
(vrange_allocator::vrange_allocator): New.
(vrange_allocator::~vrange_allocator): New.
(vrange_storage::alloc_slot): New.
(vrange_allocator::alloc): New.
(vrange_allocator::free): New.
(vrange_allocator::clone): New.
(vrange_allocator::clone_varying): New.
(vrange_allocator::clone_undefined): New.
(vrange_storage::alloc): New.
(vrange_storage::set_vrange): Remove slot argument.
(vrange_storage::get_vrange): Same.
(vrange_storage::fits_p): Same.
(vrange_storage::equal_p): New.
(irange_storage::write_lengths_address): New.
(irange_storage::lengths_address): New.
(irange_storage_slot::alloc_slot): Remove.
(irange_storage::alloc): New.
(irange_storage_slot::irange_storage_slot): Remove.
(irange_storage::irange_storage): New.
(write_wide_int): New.
(irange_storage_slot::set_irange): Remove.
(irange_storage::set_irange): New.
(read_wide_int): New.
(irange_storage_slot::get_irange): Remove.
(irange_storage::get_irange): New.
(irange_storage_slot::size): Remove.
(irange_storage::equal_p): New.
(irange_storage_slot::num_wide_ints_needed): Remove.
(irange_storage::size): New.
(irange_storage_slot::fits_p): Remove.
(irange_storage::fits_p): New.
(irange_storage_slot::dump): Remove.
(irange_storage::dump): New.
(frange_storage_slot::alloc_slot): Remove.
(frange_storage::alloc): New.
(frange_storage_slot::set_frange): Remove.
(frange_storage::set_frange): New.
(frange_storage_slot::get_frange): Remove.
(frange_storage::get_frange): New.
(frange_storage_slot::fits_p): Remove.
(frange_storage::equal_p): New.
(frange_storage::fits_p): New.
(ggc_vrange_allocator): New.
(ggc_alloc_vrange_storage): New.
* value-range-storage.h (class vrange_storage): Rewrite.
(class irange_storage): Rewrite.
(class frange_storage): Rewrite.
(class obstack_vrange_allocator): Remove.
(class ggc_vrange_allocator): Remove.
(vrange_allocator::alloc_vrange): Remove.
(vrange_allocator::alloc_irange): Remove.
(vrange_allocator::alloc_frange): Remove.
(ggc_alloc_vrange_storage): New.
* value-range.h (class irange): Rename vrange_allocator to
irange_storage.
(class frange): Same.
2023-04-30 Roger Sayle <roger@nextmovesoftware.com>
* config/stormy16/stormy16.md (neghi2): Rewrite pattern using
inc to avoid clobbering the carry flag.
2023-04-30 Andrew Pinski <apinski@marvell.com>
* match.pd: Add patterns for "a != 0 ? FUNC(a) : CST"
for FUNC of POPCOUNT BSWAP FFS PARITY CLZ and CTZ.
2023-04-30 Andrew Pinski <apinski@marvell.com>
* tree-ssa-phiopt.cc (empty_bb_or_one_feeding_into_p):
Allow some builtin/internal function calls which
are known not to trap/throw.
(phiopt_worker::match_simplify_replacement):
Use name instead of getting the lhs again.
2023-04-30 Joakim Nohlgård <joakim@nohlgard.se>
* configure: Regenerate.
* configure.ac: Use ld -r in the check for HAVE_LD_RO_RW_SECTION_MIXING
2023-04-29 Hans-Peter Nilsson <hp@axis.com>
* reload1.cc (emit_insn_if_valid_for_reload_1): Rename from
emit_insn_if_valid_for_reload.
(emit_insn_if_valid_for_reload): Call new helper, and if a SET fails
to be recognized, also try emitting a parallel that clobbers
TARGET_FLAGS_REGNUM, as applicable.
2023-04-29 Roger Sayle <roger@nextmovesoftware.com>
* config/stormy16/stormy16.md (neghi2): Convert from a define_expand
to a define_insn.
(*rotatehi_1): New define_insn for efficient 2 insn sequence.
(*rotatehi_8, *rotaterthi_8): New define_insn to emit a swpb.
2023-04-29 Roger Sayle <roger@nextmovesoftware.com>
* config/stormy16/stormy16.md (any_lshift): New code iterator.
(any_or_plus): Likewise.
(any_rotate): Likewise.
(*<any_lshift>_and_internal): New define_insn_and_split to
recognize a logical shift followed by an AND, and split it
again after reload.
(*swpn): New define_insn matching xstormy16's swpn.
(*swpn_zext): New define_insn recognizing swpn followed by
zero_extendqihi2, i.e. with the high byte set to zero.
(*swpn_sext): Likewise, for swpn followed by cbw.
(*swpn_sext_2): Likewise, for an alternate RTL form.
(*swpn_zext_ior): A pre-reload splitter so that an swpn+zext+ior
sequence is split in the correct place to recognize the *swpn_zext
followed by any_or_plus (ior, xor or plus) instruction.
2023-04-29 Mikael Pettersson <mikpelinux@gmail.com>
PR target/105525
* config.gcc (vax-*-linux*): Add glibc-stdint.h.
(lm32-*-uclinux*): Likewise.
2023-04-29 Fei Gao <gaofei@eswincomputing.com>
* config/riscv/riscv.cc (riscv_avoid_save_libcall): helper function
for riscv_use_save_libcall.
(riscv_use_save_libcall): call riscv_avoid_save_libcall.
(riscv_compute_frame_info): restructure to decouple stack allocation
for rv32e w/o save-restore.
2023-04-28 Eugene Rozenfeld <erozen@microsoft.com>
* doc/install.texi: Fix documentation typo
2023-04-28 Matevos Mehrabyan <matevosmehrabyan@gmail.com>
* config/riscv/iterators.md (only_div, paired_mod): New iterators.
(u): Add div/udiv cases.
* config/riscv/riscv-protos.h (riscv_use_divmod_expander): Prototype.
* config/riscv/riscv.cc (struct riscv_tune_param): Add field for
divmod expansion.
(rocket_tune_info, sifive_7_tune_info): Initialize new field.
(thead_c906_tune_info): Likewise.
(optimize_size_tune_info): Likewise.
(riscv_use_divmod_expander): New function.
* config/riscv/riscv.md (<u>divmod<mode>4): New expander.
2023-04-28 Karen Sargsyan <karen1999411@gmail.com>
* config/riscv/bitmanip.md: Added clmulr instruction.
* config/riscv/riscv-builtins.cc (AVAIL): Add new.
* config/riscv/riscv.md: (UNSPEC_CLMULR): Add new unspec type.
(type): Add clmul
* config/riscv/riscv-cmo.def: Added built-in function for clmulr.
* config/riscv/crypto.md: Move clmul[h] instructions to bitmanip.md.
* config/riscv/riscv-scalar-crypto.def: Move clmul[h] built-in
functions to riscv-cmo.def.
* config/riscv/generic.md: Add clmul to list of instructions
using the generic_imul reservation.
2023-04-28 Jivan Hakobyan <jivanhakobyan9@gmail.com>
* config/riscv/bitmanip.md: Added expanders for minu/maxu instructions
2023-04-28 Andrew Pinski <apinski@marvell.com>
PR tree-optimization/100958
* tree-ssa-phiopt.cc (two_value_replacement): Remove.
(pass_phiopt::execute): Don't call two_value_replacement.
* match.pd (a !=/== CST1 ? CST2 : CST3): Add pattern to
handle what two_value_replacement did.
2023-04-28 Andrew Pinski <apinski@marvell.com>
* match.pd: Add patterns for
"(A CMP B) ? MIN/MAX<A, C> : MIN/MAX <B, C>".
2023-04-28 Andrew Pinski <apinski@marvell.com>
* match.pd: Factor out the deciding the min/max from
the "(cond (cmp (convert1? x) c1) (convert2? x) c2)"
pattern to ...
* fold-const.cc (minmax_from_comparison): this new function.
* fold-const.h (minmax_from_comparison): New prototype.
2023-04-28 Roger Sayle <roger@nextmovesoftware.com>
PR rtl-optimization/109476
* lower-subreg.cc: Include explow.h for force_reg.
(find_decomposable_shift_zext): Pass an additional SPEED_P argument.
If decomposing a suitable LSHIFTRT and we're not splitting
ZERO_EXTEND (based on the current SPEED_P), then use a ZERO_EXTEND
instead of setting a high part SUBREG to zero, which helps combine.
(decompose_multiword_subregs): Update call to resolve_shift_zext.
2023-04-28 Richard Biener <rguenther@suse.de>
* tree-vect-data-refs.cc (vect_analyze_data_refs): Always
consider scatters.
* tree-vect-stmts.cc (vect_model_store_cost): Pass in the
gather-scatter info and cost emulated scatters accordingly.
(get_load_store_type): Support emulated scatters.
(vectorizable_store): Likewise. Emulate them by extracting
scalar offsets and data, doing scalar stores.
2023-04-28 Richard Biener <rguenther@suse.de>
* config/i386/i386.cc (ix86_vector_costs::add_stmt_cost):
Tame down element extracts and scalar loads for gather/scatter
similar to elementwise strided accesses.
2023-04-28 Pan Li <pan2.li@intel.com>
kito-cheng <kito.cheng@sifive.com>
* config/riscv/vector.md: Add new define split to perform
the simplification.
2023-04-28 Richard Biener <rguenther@suse.de>
PR ipa/109652
* ipa-param-manipulation.cc
(ipa_param_body_adjustments::modify_expression): Allow
conversion of a register to a non-register type. Elide
conversions inside BIT_FIELD_REFs.
2023-04-28 Richard Biener <rguenther@suse.de>
PR tree-optimization/109644
* tree-cfg.cc (verify_types_in_gimple_reference): Check
register constraints on the outermost VIEW_CONVERT_EXPR
only. Do not allow register or invariant bases on
multi-level or possibly variable index handled components.
2023-04-28 Richard Biener <rguenther@suse.de>
* gimplify.cc (gimplify_compound_lval): When there's a
non-register type produced by one of the handled component
operations make sure we get a non-register base.
2023-04-28 Richard Biener <rguenther@suse.de>
PR tree-optimization/108752
* tree-vect-generic.cc (build_replicated_const): Rename
to build_replicated_int_cst and move to tree.{h,cc}.
(do_plus_minus): Adjust.
(do_negate): Likewise.
* tree-vect-stmts.cc (vectorizable_operation): Emit emulated
arithmetic vector operations in lowered form.
* tree.h (build_replicated_int_cst): Declare.
* tree.cc (build_replicated_int_cst): Moved from
tree-vect-generic.cc build_replicated_const.
2023-04-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR target/99195
* config/aarch64/aarch64-simd.md (aarch64_rbit<mode>): Rename to...
(aarch64_rbit<mode><vczle><vczbe>): ... This.
(neg<mode>2): Rename to...
(neg<mode>2<vczle><vczbe>): ... This.
(abs<mode>2): Rename to...
(abs<mode>2<vczle><vczbe>): ... This.
(aarch64_abs<mode>): Rename to...
(aarch64_abs<mode><vczle><vczbe>): ... This.
(one_cmpl<mode>2): Rename to...
(one_cmpl<mode>2<vczle><vczbe>): ... This.
(clrsb<mode>2): Rename to...
(clrsb<mode>2<vczle><vczbe>): ... This.
(clz<mode>2): Rename to...
(clz<mode>2<vczle><vczbe>): ... This.
(popcount<mode>2): Rename to...
(popcount<mode>2<vczle><vczbe>): ... This.
2023-04-28 Jakub Jelinek <jakub@redhat.com>
* gimple-range-op.cc (class cfn_sqrt): New type.
(op_cfn_sqrt): New variable.
(gimple_range_op_handler::maybe_builtin_call): Handle
CASE_CFN_SQRT{,_FN}.
2023-04-28 Aldy Hernandez <aldyh@redhat.com>
Jakub Jelinek <jakub@redhat.com>
* value-range.h (frange_nextafter): Declare.
* gimple-range-op.cc (class cfn_sincos): New.
(op_cfn_sin, op_cfn_cos): New variables.
(gimple_range_op_handler::maybe_builtin_call): Handle
CASE_CFN_{SIN,COS}{,_FN}.
2023-04-28 Jakub Jelinek <jakub@redhat.com>
* target.def (libm_function_max_error): New target hook.
* doc/tm.texi.in (TARGET_LIBM_FUNCTION_MAX_ERROR): Add.
* doc/tm.texi: Regenerated.
* targhooks.h (default_libm_function_max_error,
glibc_linux_libm_function_max_error): Declare.
* targhooks.cc: Include case-cfn-macros.h.
(default_libm_function_max_error,
glibc_linux_libm_function_max_error): New functions.
* config/linux.h (TARGET_LIBM_FUNCTION_MAX_ERROR): Redefine.
* config/linux-protos.h (linux_libm_function_max_error): Declare.
* config/linux.cc: Include target.h and targhooks.h.
(linux_libm_function_max_error): New function.
* config/arc/arc.cc: Include targhooks.h and case-cfn-macros.h.
(arc_libm_function_max_error): New function.
(TARGET_LIBM_FUNCTION_MAX_ERROR): Redefine.
* config/i386/i386.cc (ix86_libc_has_fast_function): Formatting fix.
(ix86_libm_function_max_error): New function.
(TARGET_LIBM_FUNCTION_MAX_ERROR): Redefine.
* config/rs6000/rs6000-protos.h
(rs6000_linux_libm_function_max_error): Declare.
* config/rs6000/rs6000-linux.cc: Include target.h, targhooks.h, tree.h
and case-cfn-macros.h.
(rs6000_linux_libm_function_max_error): New function.
* config/rs6000/linux.h (TARGET_LIBM_FUNCTION_MAX_ERROR): Redefine.
* config/rs6000/linux64.h (TARGET_LIBM_FUNCTION_MAX_ERROR): Redefine.
* config/or1k/or1k.cc: Include targhooks.h and case-cfn-macros.h.
(or1k_libm_function_max_error): New function.
(TARGET_LIBM_FUNCTION_MAX_ERROR): Redefine.
2023-04-28 Alexandre Oliva <oliva@adacore.com>
* gimple-harden-conditionals.cc (insert_edge_check_and_trap):
Move detach value calls...
(pass_harden_conditional_branches::execute): ... here.
(pass_harden_compares::execute): Detach values before
compares.
2023-04-27 Andrew Stubbs <ams@codesourcery.com>
* config/gcn/gcn-valu.md (cmul<conj_op><mode>3): Use gcn_gen_undef.
(cml<addsub_as><mode>4): Likewise.
(vec_addsub<mode>3): Likewise.
(cadd<rot><mode>3): Likewise.
(vec_fmaddsub<mode>4): Likewise.
(vec_fmsubadd<mode>4): Likewise, and use sub for the odd lanes.
2023-04-27 Andrew Pinski <apinski@marvell.com>
* tree-ssa-phiopt.cc (phiopt_early_allow): Allow for
up to 2 min/max expressions in the sequence/match code.
2023-04-27 Andrew Pinski <apinski@marvell.com>
* rtlanal.cc (may_trap_p_1): Treat SMIN/SMAX similar as
COMPARISON.
* tree-eh.cc (operation_could_trap_helper_p): Treate
MIN_EXPR/MAX_EXPR similar as other comparisons.
2023-04-27 Andrew Pinski <apinski@marvell.com>
* tree-ssa-phiopt.cc (cond_store_replacement): Remove
prototype.
(cond_if_else_store_replacement): Likewise.
(get_non_trapping): Likewise.
(store_elim_worker): Move into ...
(pass_cselim::execute): This.
2023-04-27 Andrew Pinski <apinski@marvell.com>
* tree-ssa-phiopt.cc (two_value_replacement): Remove
prototype.
(match_simplify_replacement): Likewise.
(factor_out_conditional_conversion): Likewise.
(value_replacement): Likewise.
(minmax_replacement): Likewise.
(spaceship_replacement): Likewise.
(cond_removal_in_builtin_zero_pattern): Likewise.
(hoist_adjacent_loads): Likewise.
(tree_ssa_phiopt_worker): Move into ...
(pass_phiopt::execute): this.
2023-04-27 Andrew Pinski <apinski@marvell.com>
* tree-ssa-phiopt.cc (tree_ssa_phiopt_worker): Remove
do_store_elim argument and split that part out to ...
(store_elim_worker): This new function.
(pass_cselim::execute): Call store_elim_worker.
(pass_phiopt::execute): Update call to tree_ssa_phiopt_worker.
2023-04-27 Jan Hubicka <jh@suse.cz>
* cfgloopmanip.h (unloop_loops): Export.
* tree-ssa-loop-ch.cc (ch_base::copy_headers): Unloop loops
that no longer loop.
* tree-ssa-loop-ivcanon.cc (unloop_loops): Export; do not free
vectors of loops to unloop.
(canonicalize_induction_variables): Free vectors here.
(tree_unroll_loops_completely): Free vectors here.
2023-04-27 Richard Biener <rguenther@suse.de>
PR tree-optimization/109170
* gimple-range-op.cc (gimple_range_op_handler::maybe_builtin_call):
Handle __builtin_expect and similar via cfn_pass_through_arg1
and inspecting the calls fnspec.
* builtins.cc (builtin_fnspec): Handle BUILT_IN_EXPECT
and BUILT_IN_EXPECT_WITH_PROBABILITY.
2023-04-27 Alexandre Oliva <oliva@adacore.com>
* genmultilib: Use CONFIG_SHELL to run sub-scripts.
2023-04-27 Aldy Hernandez <aldyh@redhat.com>
PR tree-optimization/109639
* ipa-cp.cc (ipa_value_range_from_jfunc): Normalize range.
(propagate_vr_across_jump_function): Same.
* ipa-fnsummary.cc (evaluate_conditions_for_known_args): Same.
* ipa-prop.h (ipa_range_set_and_normalize): New.
* value-range.cc (irange::set): Assert min and max are INTEGER_CST.
2023-04-27 Richard Biener <rguenther@suse.de>
* match.pd (BIT_FIELD_REF CONSTRUCTOR@0 @1 @2): Do not
create a CTOR operand in the result when simplifying GIMPLE.
2023-04-27 Richard Biener <rguenther@suse.de>
* gimplify.cc (gimplify_compound_lval): When the base
gimplified to a register make sure to split up chains
of operations.
2023-04-27 Richard Biener <rguenther@suse.de>
PR ipa/109607
* ipa-param-manipulation.h
(ipa_param_body_adjustments::modify_expression): Add extra_stmts
argument.
* ipa-param-manipulation.cc
(ipa_param_body_adjustments::modify_expression): Likewise.
When we need a conversion and the replacement is a register
split the conversion out.
(ipa_param_body_adjustments::modify_assignment): Pass
extra_stmts to RHS modify_expression.
2023-04-27 Jonathan Wakely <jwakely@redhat.com>
* doc/extend.texi (Zero Length): Describe example.
2023-04-27 Richard Biener <rguenther@suse.de>
PR tree-optimization/109594
* tree-ssa.cc (non_rewritable_mem_ref_base): Constrain
what we rewrite to a register based on the above.
2023-04-26 Patrick O'Neill <patrick@rivosinc.com>
* config/riscv/riscv.cc: Fix whitespace.
* config/riscv/sync.md: Fix whitespace.
2023-04-26 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/108697
* gimple-range-cache.cc (ssa_global_cache::clear_range): Do
not clear the vector on an out of range query.
(ssa_cache::dump): Use dump_range_query instead of get_range.
(ssa_cache::dump_range_query): New.
(ssa_lazy_cache::dump_range_query): New.
(ssa_lazy_cache::set_range): New.
* gimple-range-cache.h (ssa_cache::dump_range_query): New.
(class ssa_lazy_cache): New.
(ssa_lazy_cache::ssa_lazy_cache): New.
(ssa_lazy_cache::~ssa_lazy_cache): New.
(ssa_lazy_cache::get_range): New.
(ssa_lazy_cache::clear_range): New.
(ssa_lazy_cache::clear): New.
(ssa_lazy_cache::dump): New.
* gimple-range-path.cc (path_range_query::path_range_query): Do
not allocate a ssa_cache object nor has_cache bitmap.
(path_range_query::~path_range_query): Do not free objects.
(path_range_query::clear_cache): Remove.
(path_range_query::get_cache): Adjust.
(path_range_query::set_cache): Remove.
(path_range_query::dump): Don't call through a pointer.
(path_range_query::internal_range_of_expr): Set cache directly.
(path_range_query::reset_path): Clear cache directly.
(path_range_query::ssa_range_in_phi): Fold with globals only.
(path_range_query::compute_ranges_in_phis): Simply set range.
(path_range_query::compute_ranges_in_block): Call cache directly.
* gimple-range-path.h (class path_range_query): Replace bitmap
and cache pointer with lazy cache object.
* gimple-range.h (class assume_query): Use ssa_lazy_cache.
2023-04-26 Andrew MacLeod <amacleod@redhat.com>
* gimple-range-cache.cc (ssa_cache::ssa_cache): Rename.
(ssa_cache::~ssa_cache): Rename.
(ssa_cache::has_range): New.
(ssa_cache::get_range): Rename.
(ssa_cache::set_range): Rename.
(ssa_cache::clear_range): Rename.
(ssa_cache::clear): Rename.
(ssa_cache::dump): Rename and use get_range.
(ranger_cache::get_global_range): Use get_range and set_range.
(ranger_cache::range_of_def): Use get_range.
* gimple-range-cache.h (class ssa_cache): Rename class and methods.
(class ranger_cache): Use ssa_cache.
* gimple-range-path.cc (path_range_query::path_range_query): Use
ssa_cache.
(path_range_query::get_cache): Use get_range.
(path_range_query::set_cache): Use set_range.
* gimple-range-path.h (class path_range_query): Use ssa_cache.
* gimple-range.cc (assume_query::assume_range_p): Use get_range.
(assume_query::range_of_expr): Use get_range.
(assume_query::assume_query): Use set_range.
(assume_query::calculate_op): Use get_range and set_range.
* gimple-range.h (class assume_query): Use ssa_cache.
2023-04-26 Andrew MacLeod <amacleod@redhat.com>
* gimple-range-cache.cc (sbr_vector::sbr_vector): Add parameter
and local to optionally zero memory.
(br_vector::grow): Only zero memory if flag is set.
(class sbr_lazy_vector): New.
(sbr_lazy_vector::sbr_lazy_vector): New.
(sbr_lazy_vector::set_bb_range): New.
(sbr_lazy_vector::get_bb_range): New.
(sbr_lazy_vector::bb_range_p): New.
(block_range_cache::set_bb_range): Check flags and Use sbr_lazy_vector.
* gimple-range-gori.cc (gori_map::calculate_gori): Use
param_vrp_switch_limit.
(gori_compute::gori_compute): Use param_vrp_switch_limit.
* params.opt (vrp_sparse_threshold): Rename from evrp_sparse_threshold.
(vrp_switch_limit): Rename from evrp_switch_limit.
(vrp_vector_threshold): New.
2023-04-26 Andrew MacLeod <amacleod@redhat.com>
* value-relation.cc (dom_oracle::query_relation): Check early for lack
of any relation.
* value-relation.h (equiv_oracle::has_equiv_p): New.
2023-04-26 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/109417
* gimple-range-gori.cc (range_def_chain::register_dependency):
Save the ssa version number, not the pointer.
(gori_compute::may_recompute_p): No need to check if a dependency
is in the free list.
* gimple-range-gori.h (class range_def_chain): Change ssa1 and ssa2
fields to be unsigned int instead of trees.
(ange_def_chain::depend1): Adjust.
(ange_def_chain::depend2): Adjust.
* gimple-range.h: Include "ssa.h" to inline ssa_name().
2023-04-26 David Edelsohn <dje.gcc@gmail.com>
* config/rs6000/aix72.h (TARGET_DEFAULT): Use ISA_2_6_MASKS_SERVER.
* config/rs6000/aix73.h (TARGET_DEFAULT): Use ISA_2_7_MASKS_SERVER.
(PROCESSOR_DEFAULT): Use PROCESSOR_POWER8.
2023-04-26 Patrick O'Neill <patrick@rivosinc.com>
PR target/104338
* config/riscv/riscv-protos.h: Add helper function stubs.
* config/riscv/riscv.cc: Add helper functions for subword masking.
* config/riscv/riscv.opt: Add command-line flags -minline-atomics and
-mno-inline-atomics.
* config/riscv/sync.md: Add masking logic and inline asm for fetch_and_op,
fetch_and_nand, CAS, and exchange ops.
* doc/invoke.texi: Add blurb regarding new command-line flags
-minline-atomics and -mno-inline-atomics.
2023-04-26 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-simd.md (aarch64_rshrn2<mode>_insn_le):
Reimplement using standard RTL codes instead of unspec.
(aarch64_rshrn2<mode>_insn_be): Likewise.
(aarch64_rshrn2<mode>): Adjust for the above.
* config/aarch64/aarch64.md (UNSPEC_RSHRN): Delete.
2023-04-26 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-simd.md (aarch64_rshrn<mode>_insn_le): Reimplement
with standard RTL codes instead of an UNSPEC.
(aarch64_rshrn<mode>_insn_be): Likewise.
(aarch64_rshrn<mode>): Adjust for the above.
* config/aarch64/predicates.md (aarch64_simd_rshrn_imm_vec): Define.
2023-04-26 Pan Li <pan2.li@intel.com>
Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv.cc (riscv_classify_address): Allow
const0_rtx for the RVV load/store.
2023-04-26 Aldy Hernandez <aldyh@redhat.com>
* range-op.cc (range_op_cast_tests): Remove legacy support.
* value-range-storage.h (vrange_allocator::alloc_irange): Same.
* value-range.cc (irange::operator=): Same.
(get_legacy_range): Same.
(irange::copy_legacy_to_multi_range): Delete.
(irange::copy_to_legacy): Delete.
(irange::irange_set_anti_range): Delete.
(irange::set): Remove legacy support.
(irange::verify_range): Same.
(irange::legacy_lower_bound): Delete.
(irange::legacy_upper_bound): Delete.
(irange::legacy_equal_p): Delete.
(irange::operator==): Remove legacy support.
(irange::singleton_p): Same.
(irange::value_inside_range): Same.
(irange::contains_p): Same.
(intersect_ranges): Delete.
(irange::legacy_intersect): Delete.
(union_ranges): Delete.
(irange::legacy_union): Delete.
(irange::legacy_verbose_union_): Delete.
(irange::legacy_verbose_intersect): Delete.
(irange::irange_union): Remove legacy support.
(irange::irange_intersect): Same.
(irange::intersect): Same.
(irange::invert): Same.
(ranges_from_anti_range): Delete.
(gt_pch_nx): Adjust for legacy removal.
(gt_ggc_mx): Same.
(range_tests_legacy): Delete.
(range_tests_misc): Adjust for legacy removal.
(range_tests): Same.
* value-range.h (class irange): Same.
(irange::legacy_mode_p): Delete.
(ranges_from_anti_range): Delete.
(irange::nonzero_p): Adjust for legacy removal.
(irange::lower_bound): Same.
(irange::upper_bound): Same.
(irange::union_): Same.
(irange::intersect): Same.
(irange::set_nonzero): Same.
(irange::set_zero): Same.
* vr-values.cc (simplify_using_ranges::legacy_fold_cond_overflow): Same.
2023-04-26 Aldy Hernandez <aldyh@redhat.com>
* value-range.cc (irange::copy_legacy_to_multi_range): Rewrite use
of range_has_numeric_bounds_p with irange API.
(range_has_numeric_bounds_p): Delete.
* value-range.h (range_has_numeric_bounds_p): Delete.
2023-04-26 Aldy Hernandez <aldyh@redhat.com>
* tree-data-ref.cc (compute_distributive_range): Replace uses of
range_int_cst_p with irange API.
* tree-ssa-strlen.cc (get_range_strlen_dynamic): Same.
* tree-vrp.h (range_int_cst_p): Delete.
* vr-values.cc (check_for_binary_op_overflow): Replace usees of
range_int_cst_p with irange API.
(vr_set_zero_nonzero_bits): Same.
(range_fits_type_p): Same.
(simplify_using_ranges::simplify_casted_cond): Same.
* tree-vrp.cc (range_int_cst_p): Remove.
2023-04-26 Aldy Hernandez <aldyh@redhat.com>
* tree-ssa-strlen.cc (compare_nonzero_chars): Convert to wide_ints.
2023-04-26 Aldy Hernandez <aldyh@redhat.com>
* builtins.cc (expand_builtin_strnlen): Rewrite deprecated irange
API uses to new API.
* gimple-predicate-analysis.cc (find_var_cmp_const): Same.
* internal-fn.cc (get_min_precision): Same.
* match.pd: Same.
* tree-affine.cc (expr_to_aff_combination): Same.
* tree-data-ref.cc (dr_step_indicator): Same.
* tree-dfa.cc (get_ref_base_and_extent): Same.
* tree-scalar-evolution.cc (iv_can_overflow_p): Same.
* tree-ssa-phiopt.cc (two_value_replacement): Same.
* tree-ssa-pre.cc (insert_into_preds_of_block): Same.
* tree-ssa-reassoc.cc (optimize_range_tests_to_bit_test): Same.
* tree-ssa-strlen.cc (compare_nonzero_chars): Same.
* tree-switch-conversion.cc (bit_test_cluster::emit): Same.
* tree-vect-patterns.cc (vect_recog_divmod_pattern): Same.
* tree.cc (get_range_pos_neg): Same.
2023-04-26 Aldy Hernandez <aldyh@redhat.com>
* ipa-prop.cc (ipa_print_node_jump_functions_for_edge): Use
vrange::dump instead of ad-hoc dumper.
* tree-ssa-strlen.cc (dump_strlen_info): Same.
* value-range-pretty-print.cc (visit): Pass TDF_NOUID to
dump_generic_node.
2023-04-26 Aldy Hernandez <aldyh@redhat.com>
* range-op.cc (operator_cast::op1_range): Use
create_possibly_reversed_range.
(operator_bitwise_and::simple_op1_range_solver): Same.
* value-range.cc (swap_out_of_order_endpoints): Delete.
(irange::set): Remove call to swap_out_of_order_endpoints.
2023-04-26 Aldy Hernandez <aldyh@redhat.com>
* builtins.cc (determine_block_size): Convert use of legacy API to
get_legacy_range.
* gimple-array-bounds.cc (check_out_of_bounds_and_warn): Same.
(array_bounds_checker::check_array_ref): Same.
* gimple-ssa-warn-restrict.cc
(builtin_memref::extend_offset_range): Same.
* ipa-cp.cc (ipcp_store_vr_results): Same.
* ipa-fnsummary.cc (set_switch_stmt_execution_predicate): Same.
* ipa-prop.cc (struct ipa_vr_ggc_hash_traits): Same.
(ipa_write_jump_function): Same.
* pointer-query.cc (get_size_range): Same.
* tree-data-ref.cc (split_constant_offset): Same.
* tree-ssa-strlen.cc (get_range): Same.
(maybe_diag_stxncpy_trunc): Same.
(strlen_pass::get_len_or_size): Same.
(strlen_pass::count_nonzero_bytes_addr): Same.
* tree-vect-patterns.cc (vect_get_range_info): Same.
* value-range.cc (irange::maybe_anti_range): Remove.
(get_legacy_range): New.
(irange::copy_to_legacy): Use get_legacy_range.
(ranges_from_anti_range): Same.
* value-range.h (class irange): Remove maybe_anti_range.
(get_legacy_range): New.
* vr-values.cc (check_for_binary_op_overflow): Convert use of
legacy API to get_legacy_range.
(compare_ranges): Same.
(compare_range_with_value): Same.
(bounds_of_var_in_loop): Same.
(find_case_label_ranges): Same.
(simplify_using_ranges::simplify_switch_using_ranges): Same.
2023-04-26 Aldy Hernandez <aldyh@redhat.com>
* value-range-pretty-print.cc (vrange_printer::visit): Remove
constant_p use.
* value-range.cc (irange::constant_p): Remove.
(irange::get_nonzero_bits_from_range): Remove constant_p use.
* value-range.h (class irange): Remove constant_p.
(irange::num_pairs): Remove constant_p use.
2023-04-26 Aldy Hernandez <aldyh@redhat.com>
* value-range.cc (irange::copy_legacy_to_multi_range): Remove
symbolics support.
(irange::set): Same.
(irange::legacy_lower_bound): Same.
(irange::legacy_upper_bound): Same.
(irange::contains_p): Same.
(range_tests_legacy): Same.
(irange::normalize_addresses): Remove.
(irange::normalize_symbolics): Remove.
(irange::symbolic_p): Remove.
* value-range.h (class irange): Remove symbolic_p,
normalize_symbolics, and normalize_addresses.
* vr-values.cc (simplify_using_ranges::two_valued_val_range_p):
Remove symbolics support.
2023-04-26 Aldy Hernandez <aldyh@redhat.com>
* value-range.cc (irange::may_contain_p): Remove.
* value-range.h (range_includes_zero_p): Rewrite may_contain_p
usage with contains_p.
* vr-values.cc (compare_range_with_value): Same.
2023-04-26 Aldy Hernandez <aldyh@redhat.com>
* tree-vrp.cc (supported_types_p): Remove.
(defined_ranges_p): Remove.
(range_fold_binary_expr): Remove.
(range_fold_unary_expr): Remove.
* tree-vrp.h (range_fold_unary_expr): Remove.
(range_fold_binary_expr): Remove.
2023-04-26 Aldy Hernandez <aldyh@redhat.com>
* ipa-cp.cc (ipa_vr_operation_and_type_effects): Convert to ranger API.
(ipa_value_range_from_jfunc): Same.
(propagate_vr_across_jump_function): Same.
* ipa-fnsummary.cc (evaluate_conditions_for_known_args): Same.
* ipa-prop.cc (ipa_compute_jump_functions_for_edge): Same.
* vr-values.cc (bounds_of_var_in_loop): Same.
2023-04-26 Aldy Hernandez <aldyh@redhat.com>
* gimple-array-bounds.cc (array_bounds_checker::get_value_range):
Add irange argument.
(check_out_of_bounds_and_warn): Remove check for vr.
(array_bounds_checker::check_array_ref): Remove pointer qualifier
for vr and adjust accordingly.
* gimple-array-bounds.h (get_value_range): Add irange argument.
* value-query.cc (class equiv_allocator): Delete.
(range_query::get_value_range): Delete.
(range_query::range_query): Remove allocator access.
(range_query::~range_query): Same.
* value-query.h (get_value_range): Delete.
* vr-values.cc
(simplify_using_ranges::op_with_boolean_value_range_p): Remove
call to get_value_range.
(check_for_binary_op_overflow): Same.
(simplify_using_ranges::legacy_fold_cond_overflow): Same.
(simplify_using_ranges::simplify_abs_using_ranges): Same.
(simplify_using_ranges::simplify_cond_using_ranges_1): Same.
(simplify_using_ranges::simplify_casted_cond): Same.
(simplify_using_ranges::simplify_switch_using_ranges): Same.
(simplify_using_ranges::two_valued_val_range_p): Same.
2023-04-26 Aldy Hernandez <aldyh@redhat.com>
* vr-values.cc
(simplify_using_ranges::vrp_evaluate_conditional_warnv_with_ops):
Rename to...
(simplify_using_ranges::legacy_fold_cond_overflow): ...this.
(simplify_using_ranges::vrp_visit_cond_stmt): Rename to...
(simplify_using_ranges::legacy_fold_cond): ...this.
(simplify_using_ranges::fold_cond): Rename
vrp_evaluate_conditional_warnv_with_ops to
legacy_fold_cond_overflow.
* vr-values.h (class vr_values): Replace vrp_visit_cond_stmt and
vrp_evaluate_conditional_warnv_with_ops with legacy_fold_cond and
legacy_fold_cond_overflow respectively.
2023-04-26 Aldy Hernandez <aldyh@redhat.com>
* vr-values.cc (get_vr_for_comparison): Remove.
(compare_name_with_value): Same.
(vrp_evaluate_conditional_warnv_with_ops): Remove calls to
compare_name_with_value.
* vr-values.h: Remove compare_name_with_value.
Remove get_vr_for_comparison.
2023-04-26 Roger Sayle <roger@nextmovesoftware.com>
* config/stormy16/stormy16.md (bswaphi2): New define_insn.
(bswapsi2): New define_insn.
(swaphi): New define_insn to exchange two registers (swpw).
(define_peephole2): Recognize exchange of registers as swaphi.
2023-04-26 Richard Biener <rguenther@suse.de>
* gimple-range-path.cc (path_range_query::compute_outgoing_relations):
Avoid last_stmt.
* ipa-pure-const.cc (pass_nothrow::execute): Likewise.
* predict.cc (apply_return_prediction): Likewise.
* sese.cc (set_ifsese_condition): Likewise. Simplify.
* tree-cfg.cc (assert_unreachable_fallthru_edge_p): Avoid last_stmt.
(make_edges_bb): Likewise.
(make_cond_expr_edges): Likewise.
(end_recording_case_labels): Likewise.
(make_gimple_asm_edges): Likewise.
(cleanup_dead_labels): Likewise.
(group_case_labels): Likewise.
(gimple_can_merge_blocks_p): Likewise.
(gimple_merge_blocks): Likewise.
(find_taken_edge): Likewise. Also handle empty fallthru blocks.
(gimple_duplicate_sese_tail): Avoid last_stmt.
(find_loop_dist_alias): Likewise.
(gimple_block_ends_with_condjump_p): Likewise.
(gimple_purge_dead_eh_edges): Likewise.
(gimple_purge_dead_abnormal_call_edges): Likewise.
(pass_warn_function_return::execute): Likewise.
(execute_fixup_cfg): Likewise.
* tree-eh.cc (redirect_eh_edge_1): Likewise.
(pass_lower_resx::execute): Likewise.
(pass_lower_eh_dispatch::execute): Likewise.
(cleanup_empty_eh): Likewise.
* tree-if-conv.cc (if_convertible_bb_p): Likewise.
(predicate_bbs): Likewise.
(ifcvt_split_critical_edges): Likewise.
* tree-loop-distribution.cc (create_edge_for_control_dependence):
Likewise.
(loop_distribution::transform_reduction_loop): Likewise.
* tree-parloops.cc (transform_to_exit_first_loop_alt): Likewise.
(try_transform_to_exit_first_loop_alt): Likewise.
(transform_to_exit_first_loop): Likewise.
(create_parallel_loop): Likewise.
* tree-scalar-evolution.cc (get_loop_exit_condition): Likewise.
* tree-ssa-dce.cc (mark_last_stmt_necessary): Likewise.
(eliminate_unnecessary_stmts): Likewise.
* tree-ssa-dom.cc
(dom_opt_dom_walker::set_global_ranges_from_unreachable_edges):
Likewise.
* tree-ssa-ifcombine.cc (ifcombine_ifandif): Likewise.
(pass_tree_ifcombine::execute): Likewise.
* tree-ssa-loop-ch.cc (entry_loop_condition_is_static): Likewise.
(should_duplicate_loop_header_p): Likewise.
* tree-ssa-loop-ivcanon.cc (create_canonical_iv): Likewise.
(tree_estimate_loop_size): Likewise.
(try_unroll_loop_completely): Likewise.
* tree-ssa-loop-ivopts.cc (tree_ssa_iv_optimize_loop): Likewise.
* tree-ssa-loop-manip.cc (ip_normal_pos): Likewise.
(canonicalize_loop_ivs): Likewise.
* tree-ssa-loop-niter.cc (determine_value_range): Likewise.
(bound_difference): Likewise.
(number_of_iterations_popcount): Likewise.
(number_of_iterations_cltz): Likewise.
(number_of_iterations_cltz_complement): Likewise.
(simplify_using_initial_conditions): Likewise.
(number_of_iterations_exit_assumptions): Likewise.
(loop_niter_by_eval): Likewise.
(estimate_numbers_of_iterations): Likewise.
2023-04-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/vector.md: Refine vmadc/vmsbc RA constraint.
2023-04-26 Kewen Lin <linkw@linux.ibm.com>
PR target/108758
* config/rs6000/rs6000-builtins.def
(__builtin_vsx_scalar_cmp_exp_qp_eq, __builtin_vsx_scalar_cmp_exp_qp_gt
__builtin_vsx_scalar_cmp_exp_qp_lt,
__builtin_vsx_scalar_cmp_exp_qp_unordered): Move from stanza ieee128-hw
to power9-vector.
2023-04-26 Kewen Lin <linkw@linux.ibm.com>
PR target/109069
* config/rs6000/altivec.md (sldoi_to_mov<mode>): Replace predicate
easy_vector_constant with const_vector_each_byte_same, add
handlings in preparation for !easy_vector_constant, and update
VECTOR_UNIT_ALTIVEC_OR_VSX_P with VECTOR_MEM_ALTIVEC_OR_VSX_P.
* config/rs6000/predicates.md (const_vector_each_byte_same): New
predicate.
2023-04-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/vector.md (*pred_cmp<mode>_merge_tie_mask): New pattern.
(*pred_ltge<mode>_merge_tie_mask): Ditto.
(*pred_cmp<mode>_scalar_merge_tie_mask): Ditto.
(*pred_eqne<mode>_scalar_merge_tie_mask): Ditto.
(*pred_cmp<mode>_extended_scalar_merge_tie_mask): Ditto.
(*pred_eqne<mode>_extended_scalar_merge_tie_mask): Ditto.
(*pred_cmp<mode>_narrow_merge_tie_mask): Ditto.
2023-04-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/vector.md: Fix redundant vmv1r.v.
2023-04-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/vector.md: Fix RA constraint.
2023-04-26 Pan Li <pan2.li@intel.com>
PR target/109272
* tree-ssa-sccvn.cc (vn_reference_eq): add type vector subparts
check for vn_reference equal.
2023-04-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-opts.h (enum riscv_autovec_preference_enum): Add enum for
auto-vectorization preference.
(enum riscv_autovec_lmul_enum): Add enum for choosing LMUL of RVV
auto-vectorization.
* config/riscv/riscv.opt: Add compile option for RVV auto-vectorization.
2023-04-26 Jivan Hakobyan <jivanhakobyan9@gmail.com>
* config/riscv/bitmanip.md: Updated predicates of bclri<mode>_nottwobits
and bclridisi_nottwobits patterns.
* config/riscv/predicates.md: (not_uimm_extra_bit_or_nottwobits): Adjust
predicate to avoid splitting arith constants.
(const_nottwobits_not_arith_operand): New predicate.
2023-04-25 Hans-Peter Nilsson <hp@axis.com>
* recog.cc (peep2_attempt, peep2_update_life): Correct
head-comment description of parameter match_len.
2023-04-25 Vineet Gupta <vineetg@rivosinc.com>
* config/riscv/riscv.md: riscv_move_integer() drop in_splitter arg.
riscv_split_symbol() drop in_splitter arg.
* config/riscv/riscv.cc: riscv_move_integer() drop in_splitter arg.
riscv_split_symbol() drop in_splitter arg.
riscv_force_temporary() drop in_splitter arg.
* config/riscv/riscv-protos.h: riscv_move_integer() drop in_splitter arg.
riscv_split_symbol() drop in_splitter arg.
2023-04-25 Eric Botcazou <ebotcazou@adacore.com>
* tree-ssa.cc (insert_debug_temp_for_var_def): Do not create
superfluous debug temporaries for single GIMPLE assignments.
2023-04-25 Richard Biener <rguenther@suse.de>
PR tree-optimization/109609
* attr-fnspec.h (arg_max_access_size_given_by_arg_p):
Clarify semantics.
* tree-ssa-alias.cc (check_fnspec): Correctly interpret
the size given by arg_max_access_size_given_by_arg_p as
maximum, not exact, size.
2023-04-25 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR target/99195
* config/aarch64/aarch64-simd.md (orn<mode>3): Rename to...
(orn<mode>3<vczle><vczbe>): ... This.
(bic<mode>3): Rename to...
(bic<mode>3<vczle><vczbe>): ... This.
(<su><maxmin><mode>3): Rename to...
(<su><maxmin><mode>3<vczle><vczbe>): ... This.
2023-04-25 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-simd.md (<su_optab>div<mode>3): New define_expand.
* config/aarch64/iterators.md (VQDIV): New mode iterator.
(vnx2di): New mode attribute.
2023-04-25 Richard Biener <rguenther@suse.de>
PR rtl-optimization/109585
* tree-ssa-alias.cc (aliasing_component_refs_p): Fix typo.
2023-04-25 Jakub Jelinek <jakub@redhat.com>
PR target/109566
* config/rs6000/rs6000.cc (rs6000_is_valid_rotate_dot_mask): For
!TARGET_64BIT, don't return true if UINTVAL (mask) << (63 - nb)
is larger than signed int maximum.
2023-04-25 Martin Liska <mliska@suse.cz>
* doc/gcov.texi: Document the new "calls" field and document
the API bump. Mention also "block_ids" for lines.
* gcov.cc (output_intermediate_json_line): Output info about
calls and extend branches as well.
(generate_results): Bump version to 2.
(output_line_details): Use block ID instead of a non-sensual
index.
2023-04-25 Roger Sayle <roger@nextmovesoftware.com>
* config/stormy16/stormy16.md (zero_extendqihi2): Restore/fix
length attribute for the first (memory operand) alternative.
2023-04-25 Victor Do Nascimento <victor.donascimento@arm.com>
* config/aarch64/aarch64-simd.md(aarch64_simd_stp<mode>): New.
* config/aarch64/constraints.md: Make "Umn" relaxed memory
constraint.
* config/aarch64/iterators.md(ldpstp_vel_sz): New.
2023-04-25 Aldy Hernandez <aldyh@redhat.com>
* value-range.cc (frange::set): Adjust constructor.
* value-range.h (nan_state::nan_state): Replace default
constructor with one taking an argument.
2023-04-25 Aldy Hernandez <aldyh@redhat.com>
* ipa-cp.cc (ipa_range_contains_p): New.
(decide_whether_version_node): Use it.
2023-04-24 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
* tree-ssa-forwprop.cc (is_combined_permutation_identity): Try to
simplify two successive VEC_PERM_EXPRs with same VLA mask,
where mask chooses elements in reverse order.
2023-04-24 Andrew Pinski <apinski@marvell.com>
* tree-ssa-phiopt.cc (match_simplify_replacement): Add new arguments
and support diamond shaped basic block form.
(tree_ssa_phiopt_worker): Update call to match_simplify_replacement
2023-04-24 Andrew Pinski <apinski@marvell.com>
* tree-ssa-phiopt.cc (empty_bb_or_one_feeding_into_p):
Instead of calling last_and_only_stmt, look for the last statement
manually.
2023-04-24 Andrew Pinski <apinski@marvell.com>
* tree-ssa-phiopt.cc (empty_bb_or_one_feeding_into_p):
New function.
(match_simplify_replacement): Call
empty_bb_or_one_feeding_into_p instead of doing it inline.
2023-04-24 Andrew Pinski <apinski@marvell.com>
PR tree-optimization/68894
* tree-ssa-phiopt.cc (tree_ssa_phiopt_worker): Remove the
continue for the do_hoist_loads diamond case.
2023-04-24 Andrew Pinski <apinski@marvell.com>
* tree-ssa-phiopt.cc (tree_ssa_phiopt_worker): Rearrange
code for better code readability.
2023-04-24 Andrew Pinski <apinski@marvell.com>
PR tree-optimization/109604
* tree-ssa-phiopt.cc (tree_ssa_phiopt_worker): Move the
diamond form check from ...
(minmax_replacement): Here.
2023-04-24 Patrick Palka <ppalka@redhat.com>
* tree.cc (strip_array_types): Don't define here.
(is_typedef_decl): Don't define here.
(typedef_variant_p): Don't define here.
* tree.h (strip_array_types): Define here.
(is_typedef_decl): Define here.
(typedef_variant_p): Define here.
2023-04-24 Frederik Harwath <frederik@codesourcery.com>
* doc/generic.texi (OpenMP): Add != to allowed
conditions and state that vars can be unsigned.
* tree.def (OMP_FOR): Likewise.
2023-04-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-simd.md (mulv2di3): New expander.
2023-04-24 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* doc/install.texi: Consistently use Solaris rather than Solaris 2.
Remove explicit Solaris 11 references.
Markup fixes.
(Options specification, --with-gnu-as): as and gas always differ
on Solaris.
Remove /usr/ccs/bin reference.
(Installing GCC: Binaries, Solaris (SPARC, Intel)): Remove.
(i?86-*-solaris2*): Merge assembler, linker recommendations ...
(*-*-solaris2*): ... here.
Update bundled GCC versions.
Don't refer to pre-built binaries.
Remove /bin/sh warning.
Update assembler, linker recommendations.
Document GNAT bootstrap compiler.
(sparc-sun-solaris2*): Remove non-UltraSPARC reference.
(sparc64-*-solaris2*): Move content...
(sparcv9-*-solaris2*): ...here.
Add GDC for 64-bit bootstrap compilers.
2023-04-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR target/109406
* config/aarch64/aarch64-sve.md (<optab><mode>3): Handle TARGET_SVE2 MUL
case.
* config/aarch64/aarch64-sve2.md (*aarch64_mul_unpredicated_<mode>): New
pattern.
2023-04-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-simd.md (aarch64_<sur>abal2<mode>): Rename to...
(aarch64_<su>abal2<mode>_insn): ... This. Use RTL codes instead of unspec.
(aarch64_<su>abal2<mode>): New define_expand.
* config/aarch64/aarch64.cc (aarch64_abd_rtx_p): New function.
(aarch64_rtx_costs): Handle ABD rtxes.
* config/aarch64/aarch64.md (UNSPEC_SABAL2, UNSPEC_UABAL2): Delete.
* config/aarch64/iterators.md (ABAL2): Delete.
(sur): Remove handling of UNSPEC_UABAL2 and UNSPEC_SABAL2.
2023-04-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-simd.md (aarch64_<sur>abal<mode>): Rename to...
(aarch64_<su>abal<mode>): ... This. Use RTL codes instead of unspec.
(<sur>sadv16qi): Rename to...
(<su>sadv16qi): ... This. Adjust for the above.
* config/aarch64/aarch64-sve.md (<sur>sad<vsi2qi>): Rename to...
(<su>sad<vsi2qi>): ... This. Adjust for the above.
* config/aarch64/aarch64.md (UNSPEC_SABAL, UNSPEC_UABAL): Delete.
* config/aarch64/iterators.md (ABAL): Delete.
(sur): Remove handling of UNSPEC_SABAL and UNSPEC_UABAL.
2023-04-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-simd.md (aarch64_<sur>abdl2<mode>): Rename to...
(aarch64_<su>abdl2<mode>_insn): ... This. Use RTL codes instead of unspec.
(aarch64_<su>abdl2<mode>): New define_expand.
* config/aarch64/aarch64.md (UNSPEC_SABDL2, UNSPEC_UABDL2): Delete.
* config/aarch64/iterators.md (ABDL2): Delete.
(sur): Remove handling of UNSPEC_SABDL2 and UNSPEC_UABDL2.
2023-04-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-simd.md (aarch64_<sur>abdl<mode>): Rename to...
(aarch64_<su>abdl<mode>): ... This. Use standard RTL ops instead of
unspec.
* config/aarch64/aarch64.md (UNSPEC_SABDL, UNSPEC_UABDL): Delete.
* config/aarch64/iterators.md (ABDL): Delete.
(sur): Remove handling of UNSPEC_SABDL and UNSPEC_UABDL.
2023-04-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-simd.md
(*aarch64_<su>addlv<VDQV_L:mode>_ze<GPI:mode>): New pattern.
2023-04-24 Richard Biener <rguenther@suse.de>
* gimple-ssa-split-paths.cc (is_feasible_trace): Avoid
last_stmt.
* graphite-scop-detection.cc (single_pred_cond_non_loop_exit):
Likewise.
* ipa-fnsummary.cc (set_cond_stmt_execution_predicate): Likewise.
(set_switch_stmt_execution_predicate): Likewise.
(phi_result_unknown_predicate): Likewise.
* ipa-prop.cc (compute_complex_ancestor_jump_func): Likewise.
(ipa_analyze_indirect_call_uses): Likewise.
* predict.cc (predict_iv_comparison): Likewise.
(predict_extra_loop_exits): Likewise.
(predict_loops): Likewise.
(tree_predict_by_opcode): Likewise.
* gimple-predicate-analysis.cc (predicate::init_from_control_deps):
Likewise.
* gimple-pretty-print.cc (dump_implicit_edges): Likewise.
* tree-ssa-phiopt.cc (tree_ssa_phiopt_worker): Likewise.
(replace_phi_edge_with_variable): Likewise.
(two_value_replacement): Likewise.
(value_replacement): Likewise.
(minmax_replacement): Likewise.
(spaceship_replacement): Likewise.
(cond_removal_in_builtin_zero_pattern): Likewise.
* tree-ssa-reassoc.cc (maybe_optimize_range_tests): Likewise.
* tree-ssa-sccvn.cc (vn_phi_eq): Likewise.
(vn_phi_lookup): Likewise.
(vn_phi_insert): Likewise.
* tree-ssa-structalias.cc (compute_points_to_sets): Likewise.
* tree-ssa-threadbackward.cc (back_threader::maybe_thread_block):
Likewise.
(back_threader_profitability::possibly_profitable_path_p):
Likewise.
* tree-ssa-threadedge.cc (jump_threader::thread_outgoing_edges):
Likewise.
* tree-switch-conversion.cc (pass_convert_switch::execute):
Likewise.
(pass_lower_switch<O0>::execute): Likewise.
* tree-tailcall.cc (tree_optimize_tail_calls_1): Likewise.
* tree-vect-loop-manip.cc (vect_loop_versioning): Likewise.
* tree-vect-slp.cc (vect_slp_function): Likewise.
* tree-vect-stmts.cc (cfun_returns): Likewise.
* tree-vectorizer.cc (vect_loop_vectorized_call): Likewise.
(vect_loop_dist_alias_call): Likewise.
2023-04-24 Richard Biener <rguenther@suse.de>
* cfgcleanup.cc (outgoing_edges_match): Use FORWARDER_BLOCK_P.
2023-04-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vsetvl.cc
(vector_infos_manager::all_avail_in_compatible_p): New function.
(pass_vsetvl::refine_vsetvls): Optimize vsetvls.
* config/riscv/riscv-vsetvl.h: New function.
2023-04-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vsetvl.cc (pass_vsetvl::pre_vsetvl): Add function
comment for cleanup_insns.
2023-04-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/vector-iterators.md: New unspec to refine fault first load pattern.
* config/riscv/vector.md: Refine fault first load pattern to erase avl from instructions
with the fault first load property.
2023-04-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-simd.md (aarch64_float_truncate_lo_): Rename to...
(aarch64_float_truncate_lo_<mode><vczle><vczbe>): ... This.
2023-04-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR target/99195
* config/aarch64/aarch64-simd.md (aarch64_addp<mode>): Rename to...
(aarch64_addp<mode><vczle><vczbe>): ... This.
2023-04-23 Roger Sayle <roger@nextmovesoftware.com>
* config/stormy16/stormy16.cc (xstormy16_rtx_costs): Rewrite to
provide reasonable values for common arithmetic operations and
immediate operands (in several machine modes).
2023-04-23 Roger Sayle <roger@nextmovesoftware.com>
* config/stormy16/stormy16.cc (xstormy16_print_operand): Add %h
format specifier to output high_part register name of SImode reg.
* config/stormy16/stormy16.md (extendhisi2): New define_insn.
(zero_extendqihi2): Fix lengths, consistent formatting and add
"and Rx,#255" alternative, for documentation purposes.
(zero_extendhisi2): New define_insn.
2023-04-23 Roger Sayle <roger@nextmovesoftware.com>
* config/stormy16/stormy16.cc (xstormy16_output_shift): Implement
SImode shifts by two by performing a single bit SImode shift twice.
2023-04-23 Aldy Hernandez <aldyh@redhat.com>
PR tree-optimization/109593
* value-range.cc (frange::operator==): Handle NANs.
2023-04-23 liuhongt <hongtao.liu@intel.com>
PR rtl-optimization/108707
* ira-costs.cc (scan_one_insn): Use NO_REGS instead of
GENERAL_REGS when preferred reg_class is not known.
2023-04-22 Andrew Pinski <apinski@marvell.com>
* tree-ssa-phiopt.cc (tree_ssa_phiopt_worker):
Change the code around slightly to move diamond
handling for do_store_elim/do_hoist_loads out of
the big if/else.
2023-04-22 Andrew Pinski <apinski@marvell.com>
* tree-ssa-phiopt.cc (tree_ssa_phiopt_worker):
Remove check on empty_block_p.
2023-04-22 Jakub Jelinek <jakub@redhat.com>
PR bootstrap/109589
* system.h (class auto_mpz): Workaround PR62101 bug in GCC 4.8 and 4.9.
* realmpfr.h (class auto_mpfr): Likewise.
2023-04-22 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/109583
* match.pd (fneg/fadd simplify): Don't call related_vector_mode
if vec_mode is not VECTOR_MODE_P.
2023-04-22 Jan Hubicka <hubicka@ucw.cz>
Ondrej Kubanek <kubanek0ondrej@gmail.com>
* cfgloopmanip.h (adjust_loop_info_after_peeling): Declare.
* tree-ssa-loop-ch.cc (ch_base::copy_headers): Fix updating of
loop profile and bounds after header duplication.
* tree-ssa-loop-ivcanon.cc (adjust_loop_info_after_peeling):
Break out from try_peel_loop; fix handling of 0 iterations.
(try_peel_loop): Use adjust_loop_info_after_peeling.
2023-04-21 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/109546
* tree-vrp.cc (remove_unreachable::remove_and_update_globals): Do
not fold conditions with ADDR_EXPR early.
2023-04-21 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64.md (aarch64_umax<mode>3_insn): Delete.
(umax<mode>3): Emit raw UMAX RTL instead of going through gen_ function
for umax.
(<optab><mode>3): New define_expand for MAXMIN_NOUMAX codes.
(*aarch64_<optab><mode>3_zero): Define.
(*aarch64_<optab><mode>3_cssc): Likewise.
* config/aarch64/iterators.md (maxminand): New code attribute.
2023-04-21 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR target/108779
* config/aarch64/aarch64-opts.h (enum aarch64_tp_reg): Define.
* config/aarch64/aarch64-protos.h (aarch64_output_load_tp):
Define prototype.
* config/aarch64/aarch64.cc (aarch64_tpidr_register): Declare.
(aarch64_override_options_internal): Handle the above.
(aarch64_output_load_tp): New function.
* config/aarch64/aarch64.md (aarch64_load_tp_hard): Call
aarch64_output_load_tp.
* config/aarch64/aarch64.opt (aarch64_tp_reg): Define enum.
(mtp=): New option.
* doc/invoke.texi (AArch64 Options): Document -mtp=.
2023-04-21 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR target/99195
* config/aarch64/aarch64-simd.md (add_vec_concat_subst_le): Define.
(add_vec_concat_subst_be): Likewise.
(vczle): Likewise.
(vczbe): Likewise.
(add<mode>3): Rename to...
(add<mode>3<vczle><vczbe>): ... This.
(sub<mode>3): Rename to...
(sub<mode>3<vczle><vczbe>): ... This.
(mul<mode>3): Rename to...
(mul<mode>3<vczle><vczbe>): ... This.
(and<mode>3): Rename to...
(and<mode>3<vczle><vczbe>): ... This.
(ior<mode>3): Rename to...
(ior<mode>3<vczle><vczbe>): ... This.
(xor<mode>3): Rename to...
(xor<mode>3<vczle><vczbe>): ... This.
* config/aarch64/iterators.md (VDZ): Define.
2023-04-21 Patrick Palka <ppalka@redhat.com>
* tree.cc (walk_tree_1): Avoid repeatedly dereferencing tp
and type_p.
2023-04-21 Jan Hubicka <jh@suse.cz>
* tree-ssa-loop-ch.cc (ch_base::copy_headers): Fix previous
commit.
2023-04-21 Vineet Gupta <vineetg@rivosinc.com>
* expmed.h (x_shift*_cost): convert to int [speed][mode][shift].
(shift*_cost_ptr ()): Access x_shift*_cost array directly.
2023-04-21 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
* config/aarch64/aarch64.cc (aarch64_simd_dup_constant): Use
force_reg instead of copy_to_mode_reg.
(aarch64_expand_vector_init): Likewise.
2023-04-21 Uroš Bizjak <ubizjak@gmail.com>
* config/i386/i386.h (REG_OK_FOR_INDEX_P, REG_OK_FOR_BASE_P): Remove.
(REG_OK_FOR_INDEX_NONSTRICT_P, REG_OK_FOR_BASE_NONSTRICT_P): Ditto.
(REG_OK_FOR_INDEX_STRICT_P, REG_OK_FOR_BASE_STRICT_P): Ditto.
(FIRST_INDEX_REG, LAST_INDEX_REG): New defines.
(LEGACY_INDEX_REG_P, LEGACY_INDEX_REGNO_P): New macros.
(INDEX_REG_P, INDEX_REGNO_P): Ditto.
(REGNO_OK_FOR_INDEX_P): Use INDEX_REGNO_P predicates.
(REGNO_OK_FOR_INDEX_NONSTRICT_P): New macro.
(EG_OK_FOR_BASE_NONSTRICT_P): Ditto.
* config/i386/predicates.md (index_register_operand):
Use REGNO_OK_FOR_INDEX_P and REGNO_OK_FOR_INDEX_NONSTRICT_P macros.
* config/i386/i386.cc (ix86_legitimate_address_p): Use
REGNO_OK_FOR_BASE_P, REGNO_OK_FOR_BASE_NONSTRICT_P,
REGNO_OK_FOR_INDEX_P and REGNO_OK_FOR_INDEX_NONSTRICT_P macros.
2023-04-21 Jan Hubicka <hubicka@ucw.cz>
Ondrej Kubanek <kubanek0ondrej@gmail.com>
* tree-ssa-loop-ch.cc (ch_base::copy_headers): Update loop header and
latch.
2023-04-21 Richard Biener <rguenther@suse.de>
* is-a.h (safe_is_a): New.
2023-04-21 Richard Biener <rguenther@suse.de>
* gimple-iterator.h (gimple_stmt_iterator::operator*): Add.
(gphi_iterator::operator*): Likewise.
2023-04-21 Jan Hubicka <hubicka@ucw.cz>
Michal Jires <michal@jires.eu>
* ipa-inline.cc (class inline_badness): New class.
(edge_heap_t, edge_heap_node_t): Use inline_badness for badness instead
of sreal.
(update_edge_key): Update.
(lookup_recursive_calls): Likewise.
(recursive_inlining): Likewise.
(add_new_edges_to_heap): Likewise.
(inline_small_functions): Likewise.
2023-04-21 Jan Hubicka <hubicka@ucw.cz>
* ipa-devirt.cc (odr_types_equivalent_p): Cleanup warned checks.
2023-04-21 Richard Biener <rguenther@suse.de>
PR tree-optimization/109573
* tree-vect-loop.cc (vectorizable_live_operation): Allow
unhandled SSA copy as well. Demote assert to checking only.
2023-04-21 Richard Biener <rguenther@suse.de>
* df-core.cc (df_analyze): Compute RPO on the reverse graph
for DF_BACKWARD problems.
(loop_post_order_compute): Rename to ...
(loop_rev_post_order_compute): ... this, compute a RPO.
(loop_inverted_post_order_compute): Rename to ...
(loop_inverted_rev_post_order_compute): ... this, compute a RPO.
(df_analyze_loop): Use RPO on the forward graph for DF_FORWARD
problems, RPO on the inverted graph for DF_BACKWARD.
2023-04-21 Richard Biener <rguenther@suse.de>
* cfganal.h (inverted_rev_post_order_compute): Rename
from ...
(inverted_post_order_compute): ... this. Add struct function
argument, change allocation to a C array.
* cfganal.cc (inverted_rev_post_order_compute): Likewise.
* lcm.cc (compute_antinout_edge): Adjust.
* lra-lives.cc (lra_create_live_ranges_1): Likewise.
* tree-ssa-dce.cc (remove_dead_stmt): Likewise.
* tree-ssa-pre.cc (compute_antic): Likewise.
2023-04-21 Richard Biener <rguenther@suse.de>
* df.h (df_d::postorder_inverted): Change back to int *,
clarify comments.
* df-core.cc (rest_of_handle_df_finish): Adjust.
(df_analyze_1): Likewise.
(df_analyze): For DF_FORWARD problems use RPO on the forward
graph. Adjust.
(loop_inverted_post_order_compute): Adjust API.
(df_analyze_loop): Adjust.
(df_get_n_blocks): Likewise.
(df_get_postorder): Likewise.
2023-04-21 Juzhe-Zhong <juzhe.zhong@rivai.ai>
PR target/108270
* config/riscv/riscv-vsetvl.cc
(vector_infos_manager::all_empty_predecessor_p): New function.
(pass_vsetvl::backward_demand_fusion): Ditto.
* config/riscv/riscv-vsetvl.h: Ditto.
2023-04-21 Robin Dapp <rdapp@ventanamicro.com>
PR target/109582
* config/riscv/generic.md: Change standard names to insn names.
2023-04-21 Richard Biener <rguenther@suse.de>
* lcm.cc (compute_antinout_edge): Use RPO on the inverted graph.
(compute_laterin): Use RPO.
(compute_available): Likewise.
2023-04-21 Peng Fan <fanpeng@loongson.cn>
* config/loongarch/gnu-user.h (MUSL_DYNAMIC_LINKER): Redefine.
2023-04-21 Juzhe-Zhong <juzhe.zhong@rivai.ai>
PR target/109547
* config/riscv/riscv-vsetvl.cc (local_eliminate_vsetvl_insn): New function.
(vector_insn_info::skip_avl_compatible_p): Ditto.
(vector_insn_info::merge): Remove default value.
(pass_vsetvl::compute_local_backward_infos): Ditto.
(pass_vsetvl::cleanup_insns): Add local vsetvl elimination.
* config/riscv/riscv-vsetvl.h: Ditto.
2023-04-20 Alejandro Colomar <alx.manpages@gmail.com>
* doc/extend.texi (Common Function Attributes): Remove duplicate
word.
2023-04-20 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/109564
* gimple-range-fold.cc (fold_using_range::range_of_phi): Do no ignore
UNDEFINED range names when deciding if all PHI arguments are the same,
2023-04-20 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/109011
* tree-vect-patterns.cc (vect_recog_ctz_ffs_pattern): Use
.CTZ (X) = .POPCOUNT ((X - 1) & ~X) in preference to
.CTZ (X) = PREC - .POPCOUNT (X | -X).
2023-04-20 Vladimir N. Makarov <vmakarov@redhat.com>
* lra-constraints.cc (match_reload): Exclude some hard regs for
multi-reg inout reload pseudos used in asm in different mode.
2023-04-20 Uros Bizjak <ubizjak@gmail.com>
* config/arm/arm.cc (thumb1_legitimate_address_p):
Use VIRTUAL_REGISTER_P predicate.
(arm_eliminable_register): Ditto.
* config/avr/avr.md (push<mode>_1): Ditto.
* config/bfin/predicates.md (register_no_elim_operand): Ditto.
* config/h8300/predicates.md (register_no_sp_elim_operand): Ditto.
* config/i386/predicates.md (register_no_elim_operand): Ditto.
* config/iq2000/predicates.md (call_insn_operand): Ditto.
* config/microblaze/microblaze.h (CALL_INSN_OP): Ditto.
2023-04-20 Uros Bizjak <ubizjak@gmail.com>
PR target/78952
* config/i386/predicates.md (extract_operator): New predicate.
* config/i386/i386.md (any_extract): Remove code iterator.
(*cmpqi_ext<mode>_1_mem_rex64): Use extract_operator predicate.
(*cmpqi_ext<mode>_1): Ditto.
(*cmpqi_ext<mode>_2): Ditto.
(*cmpqi_ext<mode>_3_mem_rex64): Ditto.
(*cmpqi_ext<mode>_3): Ditto.
(*cmpqi_ext<mode>_4): Ditto.
(*extzvqi_mem_rex64): Ditto.
(*extzvqi): Ditto.
(*insvqi_2): Ditto.
(*extendqi<SWI24:mode>_ext_1): Ditto.
(*addqi_ext<mode>_0): Ditto.
(*addqi_ext<mode>_1): Ditto.
(*addqi_ext<mode>_2): Ditto.
(*subqi_ext<mode>_0): Ditto.
(*subqi_ext<mode>_2): Ditto.
(*testqi_ext<mode>_1): Ditto.
(*testqi_ext<mode>_2): Ditto.
(*andqi_ext<mode>_0): Ditto.
(*andqi_ext<mode>_1): Ditto.
(*andqi_ext<mode>_1_cc): Ditto.
(*andqi_ext<mode>_2): Ditto.
(*<any_or:code>qi_ext<mode>_0): Ditto.
(*<any_or:code>qi_ext<mode>_1): Ditto.
(*<any_or:code>qi_ext<mode>_2): Ditto.
(*xorqi_ext<mode>_1_cc): Ditto.
(*negqi_ext<mode>_2): Ditto.
(*ashlqi_ext<mode>_2): Ditto.
(*<any_shiftrt:insn>qi_ext<mode>_2): Ditto.
2023-04-20 Raphael Zinsly <rzinsly@ventanamicro.com>
PR target/108248
* config/riscv/bitmanip.md (clz, ctz, pcnt, min, max patterns): Use
<bitmanip_insn> as the type to allow for fine grained control of
scheduling these insns.
* config/riscv/generic.md (generic_alu): Add bitmanip, clz, ctz, pcnt,
min, max.
* config/riscv/riscv.md (type attribute): Add types for clz, ctz,
pcnt, signed and unsigned min/max.
2023-04-20 Juzhe-Zhong <juzhe.zhong@rivai.ai>
kito-cheng <kito.cheng@sifive.com>
* config/riscv/riscv.h (enum reg_class): Fix RVV register order.
2023-04-20 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
kito-cheng <kito.cheng@sifive.com>
PR target/109535
* config/riscv/riscv-vsetvl.cc (count_regno_occurrences): New function.
(pass_vsetvl::cleanup_insns): Fix bug.
2023-04-20 Andrew Stubbs <ams@codesourcery.com>
* config/gcn/gcn-valu.md (vnsi, VnSI): Add scalar modes.
(ldexp<mode>3): Delete.
(ldexp<mode>3<exec>): Change "B" to "A".
2023-04-20 Jakub Jelinek <jakub@redhat.com>
Jonathan Wakely <jwakely@redhat.com>
* tree.h (built_in_function_equal_p): New helper function.
(fndecl_built_in_p): Turn into variadic template to support
1 or more built_in_function arguments.
* builtins.cc (fold_builtin_expect): Use 3 argument fndecl_built_in_p.
* gimplify.cc (goa_stabilize_expr): Likewise.
* cgraphclones.cc (cgraph_node::create_clone): Likewise.
* ipa-fnsummary.cc (compute_fn_summary): Likewise.
* omp-low.cc (setjmp_or_longjmp_p): Likewise.
* cgraph.cc (cgraph_edge::redirect_call_stmt_to_callee,
cgraph_update_edges_for_call_stmt_node,
cgraph_edge::verify_corresponds_to_fndecl,
cgraph_node::verify_node): Likewise.
* tree-stdarg.cc (optimize_va_list_gpr_fpr_size): Likewise.
* gimple-ssa-warn-access.cc (matching_alloc_calls_p): Likewise.
* ipa-prop.cc (try_make_edge_direct_virtual_call): Likewise.
2023-04-20 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/109011
* tree-vect-patterns.cc (vect_recog_ctz_ffs_pattern): New function.
(vect_recog_popcount_clz_ctz_ffs_pattern): Move vect_pattern_detected
call later. Don't punt for IFN_CTZ or IFN_FFS if it doesn't have
direct optab support, but has instead IFN_CLZ, IFN_POPCOUNT or
for IFN_FFS IFN_CTZ support, use vect_recog_ctz_ffs_pattern for that
case.
(vect_vect_recog_func_ptrs): Add ctz_ffs entry.
2023-04-20 Richard Biener <rguenther@suse.de>
* df-core.cc (rest_of_handle_df_initialize): Remove
computation of df->postorder, df->postorder_inverted and
df->n_blocks.
2023-04-20 Haochen Jiang <haochen.jiang@intel.com>
* common/config/i386/i386-common.cc
(OPTION_MASK_ISA2_AVX_UNSET): Add OPTION_MASK_ISA2_VAES_UNSET.
(ix86_handle_option): Set AVX flag for VAES.
* config/i386/i386-builtins.cc (ix86_init_mmx_sse_builtins):
Add OPTION_MASK_ISA2_VAES_UNSET.
(def_builtin): Share builtin between AES and VAES.
* config/i386/i386-expand.cc (ix86_check_builtin_isa_match):
Ditto.
* config/i386/i386.md (aes): New isa attribute.
* config/i386/sse.md (aesenc): Add pattern for VAES with xmm.
(aesenclast): Ditto.
(aesdec): Ditto.
(aesdeclast): Ditto.
* config/i386/vaesintrin.h: Remove redundant avx target push.
* config/i386/wmmintrin.h (_mm_aesdec_si128): Change to macro.
(_mm_aesdeclast_si128): Ditto.
(_mm_aesenc_si128): Ditto.
(_mm_aesenclast_si128): Ditto.
2023-04-20 Hu, Lin1 <lin1.hu@intel.com>
* config/i386/avx2intrin.h
(_MM_REDUCE_OPERATOR_BASIC_EPI16): New macro.
(_MM_REDUCE_OPERATOR_MAX_MIN_EP16): Ditto.
(_MM256_REDUCE_OPERATOR_BASIC_EPI16): Ditto.
(_MM256_REDUCE_OPERATOR_MAX_MIN_EP16): Ditto.
(_MM_REDUCE_OPERATOR_BASIC_EPI8): Ditto.
(_MM_REDUCE_OPERATOR_MAX_MIN_EP8): Ditto.
(_MM256_REDUCE_OPERATOR_BASIC_EPI8): Ditto.
(_MM256_REDUCE_OPERATOR_MAX_MIN_EP8): Ditto.
(_mm_reduce_add_epi16): New instrinsics.
(_mm_reduce_mul_epi16): Ditto.
(_mm_reduce_and_epi16): Ditto.
(_mm_reduce_or_epi16): Ditto.
(_mm_reduce_max_epi16): Ditto.
(_mm_reduce_max_epu16): Ditto.
(_mm_reduce_min_epi16): Ditto.
(_mm_reduce_min_epu16): Ditto.
(_mm256_reduce_add_epi16): Ditto.
(_mm256_reduce_mul_epi16): Ditto.
(_mm256_reduce_and_epi16): Ditto.
(_mm256_reduce_or_epi16): Ditto.
(_mm256_reduce_max_epi16): Ditto.
(_mm256_reduce_max_epu16): Ditto.
(_mm256_reduce_min_epi16): Ditto.
(_mm256_reduce_min_epu16): Ditto.
(_mm_reduce_add_epi8): Ditto.
(_mm_reduce_mul_epi8): Ditto.
(_mm_reduce_and_epi8): Ditto.
(_mm_reduce_or_epi8): Ditto.
(_mm_reduce_max_epi8): Ditto.
(_mm_reduce_max_epu8): Ditto.
(_mm_reduce_min_epi8): Ditto.
(_mm_reduce_min_epu8): Ditto.
(_mm256_reduce_add_epi8): Ditto.
(_mm256_reduce_mul_epi8): Ditto.
(_mm256_reduce_and_epi8): Ditto.
(_mm256_reduce_or_epi8): Ditto.
(_mm256_reduce_max_epi8): Ditto.
(_mm256_reduce_max_epu8): Ditto.
(_mm256_reduce_min_epi8): Ditto.
(_mm256_reduce_min_epu8): Ditto.
* config/i386/avx512vlbwintrin.h:
(_mm_mask_reduce_add_epi16): Ditto.
(_mm_mask_reduce_mul_epi16): Ditto.
(_mm_mask_reduce_and_epi16): Ditto.
(_mm_mask_reduce_or_epi16): Ditto.
(_mm_mask_reduce_max_epi16): Ditto.
(_mm_mask_reduce_max_epu16): Ditto.
(_mm_mask_reduce_min_epi16): Ditto.
(_mm_mask_reduce_min_epu16): Ditto.
(_mm256_mask_reduce_add_epi16): Ditto.
(_mm256_mask_reduce_mul_epi16): Ditto.
(_mm256_mask_reduce_and_epi16): Ditto.
(_mm256_mask_reduce_or_epi16): Ditto.
(_mm256_mask_reduce_max_epi16): Ditto.
(_mm256_mask_reduce_max_epu16): Ditto.
(_mm256_mask_reduce_min_epi16): Ditto.
(_mm256_mask_reduce_min_epu16): Ditto.
(_mm_mask_reduce_add_epi8): Ditto.
(_mm_mask_reduce_mul_epi8): Ditto.
(_mm_mask_reduce_and_epi8): Ditto.
(_mm_mask_reduce_or_epi8): Ditto.
(_mm_mask_reduce_max_epi8): Ditto.
(_mm_mask_reduce_max_epu8): Ditto.
(_mm_mask_reduce_min_epi8): Ditto.
(_mm_mask_reduce_min_epu8): Ditto.
(_mm256_mask_reduce_add_epi8): Ditto.
(_mm256_mask_reduce_mul_epi8): Ditto.
(_mm256_mask_reduce_and_epi8): Ditto.
(_mm256_mask_reduce_or_epi8): Ditto.
(_mm256_mask_reduce_max_epi8): Ditto.
(_mm256_mask_reduce_max_epu8): Ditto.
(_mm256_mask_reduce_min_epi8): Ditto.
(_mm256_mask_reduce_min_epu8): Ditto.
2023-04-20 Haochen Jiang <haochen.jiang@intel.com>
* common/config/i386/i386-common.cc
(OPTION_MASK_ISA_VPCLMULQDQ_SET):
Add OPTION_MASK_ISA_PCLMUL_SET and OPTION_MASK_ISA_AVX_SET.
(OPTION_MASK_ISA_AVX_UNSET):
Add OPTION_MASK_ISA_VPCLMULQDQ_UNSET.
(OPTION_MASK_ISA_PCLMUL_UNSET): Ditto.
* config/i386/i386.md (vpclmulqdqvl): New.
* config/i386/sse.md (pclmulqdq): Add evex encoding.
* config/i386/vpclmulqdqintrin.h: Remove redudant avx target
push.
2023-04-20 Haochen Jiang <haochen.jiang@intel.com>
* config/i386/avx512vlbwintrin.h
(_mm_mask_blend_epi16): Remove __OPTIMIZE__ wrapper.
(_mm_mask_blend_epi8): Ditto.
(_mm256_mask_blend_epi16): Ditto.
(_mm256_mask_blend_epi8): Ditto.
* config/i386/avx512vlintrin.h
(_mm256_mask_blend_pd): Ditto.
(_mm256_mask_blend_ps): Ditto.
(_mm256_mask_blend_epi64): Ditto.
(_mm256_mask_blend_epi32): Ditto.
(_mm_mask_blend_pd): Ditto.
(_mm_mask_blend_ps): Ditto.
(_mm_mask_blend_epi64): Ditto.
(_mm_mask_blend_epi32): Ditto.
* config/i386/sse.md (VF_AVX512BWHFBF16): Removed.
(VF_AVX512HFBFVL): Move it before the first usage.
(<avx512>_blendm<mode>): Change iterator from VF_AVX512BWHFBF16
to VF_AVX512HFBFVL.
2023-04-20 Haochen Jiang <haochen.jiang@intel.com>
* common/config/i386/i386-common.cc
(OPTION_MASK_ISA_AVX512VBMI2_SET): Change OPTION_MASK_ISA_AVX512F_SET
to OPTION_MASK_ISA_AVX512BW_SET.
(OPTION_MASK_ISA_AVX512F_UNSET):
Remove OPTION_MASK_ISA_AVX512VBMI2_UNSET.
(OPTION_MASK_ISA_AVX512BW_UNSET):
Add OPTION_MASK_ISA_AVX512VBMI2_UNSET.
* config/i386/avx512vbmi2intrin.h: Do not push avx512bw.
* config/i386/avx512vbmi2vlintrin.h: Ditto.
* config/i386/i386-builtin.def: Remove OPTION_MASK_ISA_AVX512BW.
* config/i386/sse.md (VI12_AVX512VLBW): Removed.
(VI12_VI48F_AVX512VLBW): Rename to VI12_VI48F_AVX512VL.
(compress<mode>_mask): Change iterator from VI12_AVX512VLBW to
VI12_AVX512VL.
(compressstore<mode>_mask): Ditto.
(expand<mode>_mask): Ditto.
(expand<mode>_maskz): Ditto.
(*expand<mode>_mask): Change iterator from VI12_VI48F_AVX512VLBW to
VI12_VI48F_AVX512VL.
2023-04-20 Haochen Jiang <haochen.jiang@intel.com>
* common/config/i386/i386-common.cc
(OPTION_MASK_ISA_AVX512BITALG_SET):
Change OPTION_MASK_ISA_AVX512F_SET
to OPTION_MASK_ISA_AVX512BW_SET.
(OPTION_MASK_ISA_AVX512F_UNSET):
Remove OPTION_MASK_ISA_AVX512BITALG_SET.
(OPTION_MASK_ISA_AVX512BW_UNSET):
Add OPTION_MASK_ISA_AVX512BITALG_SET.
* config/i386/avx512bitalgintrin.h: Do not push avx512bw.
* config/i386/i386-builtin.def:
Remove redundant OPTION_MASK_ISA_AVX512BW.
* config/i386/sse.md (VI1_AVX512VLBW): Removed.
(avx512vl_vpshufbitqmb<mode><mask_scalar_merge_name>):
Change the iterator from VI1_AVX512VLBW to VI1_AVX512VL.
2023-04-20 Haochen Jiang <haochen.jiang@intel.com>
* config/i386/i386-expand.cc
(ix86_check_builtin_isa_match): Correct wrong comments.
Add a new macro SHARE_BUILTIN and refactor the current if
clauses to macro.
2023-04-20 Mo, Zewei <zewei.mo@intel.com>
* config/i386/cpuid.h: Open a new section for Extended Features
Leaf (%eax == 7, %ecx == 0) and Extended Features Sub-leaf (%eax == 7,
%ecx == 1).
2023-04-20 Hu, Lin1 <lin1.hu@intel.com>
* config/i386/sse.md: Modify insn vperm{i,f}
and vshuf{i,f}.
2023-04-19 Max Filippov <jcmvbkbc@gmail.com>
* config/xtensa/xtensa-opts.h: New header.
* config/xtensa/xtensa.h (STRICT_ALIGNMENT): Redefine as
xtensa_strict_align.
* config/xtensa/xtensa.cc (xtensa_option_override): When
-m[no-]strict-align is not specified in the command line set
xtensa_strict_align to 0 if the hardware supports both unaligned
loads and stores or to 1 otherwise.
* config/xtensa/xtensa.opt (mstrict-align): New option.
* doc/invoke.texi (Xtensa Options): Document -m[no-]strict-align.
2023-04-19 Max Filippov <jcmvbkbc@gmail.com>
* config/xtensa/xtensa-dynconfig.cc (xtensa_get_config_v4): New
function.
2023-04-19 Andrew Pinski <apinski@marvell.com>
* config/i386/i386.md (*movsicc_noc_zext_1): New pattern.
2023-04-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-modes.def (FLOAT_MODE): Add chunk 128 support.
(VECTOR_BOOL_MODE): Ditto.
(ADJUST_NUNITS): Ditto.
(ADJUST_ALIGNMENT): Ditto.
(ADJUST_BYTESIZE): Ditto.
(ADJUST_PRECISION): Ditto.
(RVV_MODES): Ditto.
(VECTOR_MODE_WITH_PREFIX): Ditto.
* config/riscv/riscv-v.cc (ENTRY): Ditto.
(get_vlmul): Ditto.
(get_ratio): Ditto.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_TYPE): Ditto.
* config/riscv/riscv-vector-builtins.def (DEF_RVV_TYPE): Ditto.
(vbool64_t): Ditto.
(vbool32_t): Ditto.
(vbool16_t): Ditto.
(vbool8_t): Ditto.
(vbool4_t): Ditto.
(vbool2_t): Ditto.
(vbool1_t): Ditto.
(vint8mf8_t): Ditto.
(vuint8mf8_t): Ditto.
(vint8mf4_t): Ditto.
(vuint8mf4_t): Ditto.
(vint8mf2_t): Ditto.
(vuint8mf2_t): Ditto.
(vint8m1_t): Ditto.
(vuint8m1_t): Ditto.
(vint8m2_t): Ditto.
(vuint8m2_t): Ditto.
(vint8m4_t): Ditto.
(vuint8m4_t): Ditto.
(vint8m8_t): Ditto.
(vuint8m8_t): Ditto.
(vint16mf4_t): Ditto.
(vuint16mf4_t): Ditto.
(vint16mf2_t): Ditto.
(vuint16mf2_t): Ditto.
(vint16m1_t): Ditto.
(vuint16m1_t): Ditto.
(vint16m2_t): Ditto.
(vuint16m2_t): Ditto.
(vint16m4_t): Ditto.
(vuint16m4_t): Ditto.
(vint16m8_t): Ditto.
(vuint16m8_t): Ditto.
(vint32mf2_t): Ditto.
(vuint32mf2_t): Ditto.
(vint32m1_t): Ditto.
(vuint32m1_t): Ditto.
(vint32m2_t): Ditto.
(vuint32m2_t): Ditto.
(vint32m4_t): Ditto.
(vuint32m4_t): Ditto.
(vint32m8_t): Ditto.
(vuint32m8_t): Ditto.
(vint64m1_t): Ditto.
(vuint64m1_t): Ditto.
(vint64m2_t): Ditto.
(vuint64m2_t): Ditto.
(vint64m4_t): Ditto.
(vuint64m4_t): Ditto.
(vint64m8_t): Ditto.
(vuint64m8_t): Ditto.
(vfloat32mf2_t): Ditto.
(vfloat32m1_t): Ditto.
(vfloat32m2_t): Ditto.
(vfloat32m4_t): Ditto.
(vfloat32m8_t): Ditto.
(vfloat64m1_t): Ditto.
(vfloat64m2_t): Ditto.
(vfloat64m4_t): Ditto.
(vfloat64m8_t): Ditto.
* config/riscv/riscv-vector-switch.def (ENTRY): Ditto.
* config/riscv/riscv.cc (riscv_legitimize_poly_move): Ditto.
(riscv_convert_vector_bits): Ditto.
* config/riscv/riscv.md:
* config/riscv/vector-iterators.md:
* config/riscv/vector.md
(@pred_indexed_<order>store<VNX32_QH:mode><VNX32_QHI:mode>): Ditto.
(@pred_indexed_<order>store<VNX32_QHS:mode><VNX32_QHSI:mode>): Ditto.
(@pred_indexed_<order>store<VNX64_Q:mode><VNX64_Q:mode>): Ditto.
(@pred_indexed_<order>store<VNX64_QH:mode><VNX64_QHI:mode>): Ditto.
(@pred_indexed_<order>store<VNX128_Q:mode><VNX128_Q:mode>): Ditto.
(@pred_reduc_<reduc><mode><vlmul1_zve64>): Ditto.
(@pred_widen_reduc_plus<v_su><mode><vwlmul1_zve64>): Ditto.
(@pred_reduc_plus<order><mode><vlmul1_zve64>): Ditto.
(@pred_widen_reduc_plus<order><mode><vwlmul1_zve64>): Ditto.
2023-04-19 Pan Li <pan2.li@intel.com>
* simplify-rtx.cc (simplify_context::simplify_binary_operation_1):
Align IOR (A | (~A) -> -1) optimization MODE_CLASS condition to AND.
2023-04-19 Uros Bizjak <ubizjak@gmail.com>
PR target/78904
PR target/78952
* config/i386/i386.md (*cmpqi_ext<mode>_1_mem_rex64): New insn pattern.
(*cmpqi_ext<mode>_1): Use nonimmediate_operand predicate
for operand 0. Use any_extract code iterator.
(*cmpqi_ext<mode>_1 peephole2): New peephole2 pattern.
(*cmpqi_ext<mode>_2): Use any_extract code iterator.
(*cmpqi_ext<mode>_3_mem_rex64): New insn pattern.
(*cmpqi_ext<mode>_1): Use general_operand predicate
for operand 1. Use any_extract code iterator.
(*cmpqi_ext<mode>_3 peephole2): New peephole2 pattern.
(*cmpqi_ext<mode>_4): Use any_extract code iterator.
2023-04-19 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-simd.md (aarch64_saddw2<mode>): Delete.
(aarch64_uaddw2<mode>): Delete.
(aarch64_ssubw2<mode>): Delete.
(aarch64_usubw2<mode>): Delete.
(aarch64_<ANY_EXTEND:su><ADDSUB:optab>w2<mode>): New define_expand.
2023-04-19 Richard Biener <rguenther@suse.de>
* tree-ssa-structalias.cc (do_ds_constraint): Use
solve_add_graph_edge.
2023-04-19 Richard Biener <rguenther@suse.de>
* tree-ssa-structalias.cc (solve_add_graph_edge): New function,
split out from ...
(do_sd_constraint): ... here.
2023-04-19 Richard Biener <rguenther@suse.de>
* tree-cfg.cc (gimple_can_merge_blocks_p): Remove condition
rejecting the merge when A contains only a non-local label.
2023-04-19 Uros Bizjak <ubizjak@gmail.com>
* rtl.h (VIRTUAL_REGISTER_P): New predicate.
(VIRTUAL_REGISTER_NUM_P): Ditto.
(REGNO_PTR_FRAME_P): Use VIRTUAL_REGISTER_NUM_P predicate.
* expr.cc (force_operand): Use VIRTUAL_REGISTER_P predicate.
* function.cc (instantiate_decl_rtl): Ditto.
* rtlanal.cc (rtx_addr_can_trap_p_1): Ditto.
(nonzero_address_p): Ditto.
(refers_to_regno_p): Use VIRTUAL_REGISTER_NUM_P predicate.
2023-04-19 Aldy Hernandez <aldyh@redhat.com>
* value-range.h (Value_Range::Value_Range): Avoid pointer sharing.
2023-04-19 Richard Biener <rguenther@suse.de>
* system.h (auto_mpz::operator->()): New.
* realmpfr.h (auto_mpfr::operator->()): New.
* builtins.cc (do_mpfr_lgamma_r): Use auto_mpfr.
* real.cc (real_from_string): Likewise.
(dconst_e_ptr): Likewise.
(dconst_sqrt2_ptr): Likewise.
* tree-ssa-loop-niter.cc (refine_value_range_using_guard):
Use auto_mpz.
(bound_difference_of_offsetted_base): Likewise.
(number_of_iterations_ne): Likewise.
(number_of_iterations_lt_to_ne): Likewise.
* ubsan.cc: Include realmpfr.h.
(ubsan_instrument_float_cast): Use auto_mpfr.
2023-04-19 Richard Biener <rguenther@suse.de>
* tree-ssa-structalias.cc (solve_graph): Remove self-copy
edges, remove edges from escaped after special-casing them.
2023-04-19 Richard Biener <rguenther@suse.de>
* tree-ssa-structalias.cc (do_sd_constraint): Fixup escape
special casing.
2023-04-19 Richard Biener <rguenther@suse.de>
* tree-ssa-structalias.cc (do_sd_constraint): Do not write
to the LHS varinfo solution member.
2023-04-19 Richard Biener <rguenther@suse.de>
* tree-ssa-structalias.cc (topo_visit): Look at the real
destination of edges.
2023-04-19 Richard Biener <rguenther@suse.de>
PR tree-optimization/44794
* tree-ssa-loop-manip.cc (tree_transform_and_unroll_loop):
If an epilogue loop is required set its iteration upper bound.
2023-04-19 Xi Ruoyao <xry111@xry111.site>
PR target/109465
* config/loongarch/loongarch-protos.h
(loongarch_expand_block_move): Add a parameter as alignment RTX.
* config/loongarch/loongarch.h:
(LARCH_MAX_MOVE_BYTES_PER_LOOP_ITER): Remove.
(LARCH_MAX_MOVE_BYTES_STRAIGHT): Remove.
(LARCH_MAX_MOVE_OPS_PER_LOOP_ITER): Define.
(LARCH_MAX_MOVE_OPS_STRAIGHT): Define.
(MOVE_RATIO): Use LARCH_MAX_MOVE_OPS_PER_LOOP_ITER instead of
LARCH_MAX_MOVE_BYTES_PER_LOOP_ITER.
* config/loongarch/loongarch.cc (loongarch_expand_block_move):
Take the alignment from the parameter, but set it to
UNITS_PER_WORD if !TARGET_STRICT_ALIGN. Limit the length of
straight-line implementation with LARCH_MAX_MOVE_OPS_STRAIGHT
instead of LARCH_MAX_MOVE_BYTES_STRAIGHT.
(loongarch_block_move_straight): When there are left-over bytes,
half the mode size instead of falling back to byte mode at once.
(loongarch_block_move_loop): Limit the length of loop body with
LARCH_MAX_MOVE_OPS_PER_LOOP_ITER instead of
LARCH_MAX_MOVE_BYTES_PER_LOOP_ITER.
* config/loongarch/loongarch.md (cpymemsi): Pass the alignment
to loongarch_expand_block_move.
2023-04-19 Xi Ruoyao <xry111@xry111.site>
* config/loongarch/loongarch.cc
(loongarch_setup_incoming_varargs): Don't save more GARs than
cfun->va_list_gpr_size / UNITS_PER_WORD.
2023-04-19 Richard Biener <rguenther@suse.de>
* tree-ssa-loop-manip.cc (determine_exit_conditions): Fix
no epilogue condition.
2023-04-19 Richard Biener <rguenther@suse.de>
* gimple.h (gimple_assign_load): Outline...
* gimple.cc (gimple_assign_load): ... here. Avoid
get_base_address and instead just strip the outermost
handled component, treating a remaining handled component
as load.
2023-04-19 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-simd-builtins.def (neg): Delete builtins
definition.
* config/aarch64/arm_fp16.h (vnegh_f16): Reimplement using normal negation.
2023-04-19 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/109011
* tree-vect-patterns.cc (vect_recog_popcount_pattern): Rename to ...
(vect_recog_popcount_clz_ctz_ffs_pattern): ... this. Handle also
CLZ, CTZ and FFS. Remove vargs variable, use
gimple_build_call_internal rather than gimple_build_call_internal_vec.
(vect_vect_recog_func_ptrs): Adjust popcount entry.
2023-04-19 Jakub Jelinek <jakub@redhat.com>
PR target/109040
* dse.cc (replace_read): If read_reg is a SUBREG of a word mode
REG, for WORD_REGISTER_OPERATIONS copy SUBREG_REG of it into
a new REG rather than the SUBREG.
2023-04-19 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
* config/aarch64/aarch64-simd.md (aarch64_simd_vec_set_zero<mode>):
New pattern.
2023-04-19 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR target/108840
* config/aarch64/aarch64.cc (aarch64_rtx_costs): Merge ASHIFT and
ROTATE, ROTATERT, LSHIFTRT, ASHIFTRT cases. Handle subregs in op1.
2023-04-19 Richard Biener <rguenther@suse.de>
PR rtl-optimization/109237
* cse.cc (insn_live_p): Remove NEXT_INSN walk, instead check
TREE_VISITED on INSN_VAR_LOCATION_DECL.
(delete_trivially_dead_insns): Maintain TREE_VISITED on
active debug bind INSN_VAR_LOCATION_DECL.
2023-04-19 Richard Biener <rguenther@suse.de>
PR rtl-optimization/109237
* cfgcleanup.cc (bb_is_just_return): Walk insns backwards.
2023-04-19 Christophe Lyon <christophe.lyon@arm.com>
* doc/install.texi (enable-decimal-float): Add AArch64.
2023-04-19 liuhongt <hongtao.liu@intel.com>
PR rtl-optimization/109351
* ira.cc (setup_class_subset_and_memory_move_costs): Check
hard_regno_mode_ok before setting lowest memory move cost for
the mode with different reg classes.
2023-04-18 Jason Merrill <jason@redhat.com>
* doc/invoke.texi: Remove stray @gol.
2023-04-18 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* ifcvt.cc (cond_move_process_if_block): Consider the result of
targetm.noce_conversion_profitable_p() when replacing the original
sequence with the converted one.
2023-04-18 Mark Harmstone <mark@harmstone.com>
* common.opt (gcodeview): Add new option.
* gcc.cc (driver_handle_option); Handle OPT_gcodeview.
* opts.cc (command_handle_option): Similarly.
* doc/invoke.texi: Add documentation for -gcodeview.
2023-04-18 Andrew Pinski <apinski@marvell.com>
* tree-ssa-phiopt.cc (tree_ssa_phiopt_worker): Remove declaration.
(make_pass_phiopt): Make execute out of line.
(tree_ssa_cs_elim): Move code into ...
(pass_cselim::execute): here.
2023-04-18 Sam James <sam@gentoo.org>
* system.h: Drop unused INCLUDE_PTHREAD_H.
2023-04-18 Kevin Lee <kevinl@rivosinc.com>
* tree-vect-data-refs.cc (vect_grouped_store_supported): Add new
condition.
2023-04-18 Sinan Lin <sinan.lin@linux.alibaba.com>
* config/riscv/bitmanip.md (rotr<mode>3 expander): Enable for ZBKB.
(bswapdi2, bswapsi2): Similarly.
2023-04-18 Uros Bizjak <ubizjak@gmail.com>
PR target/94908
* config/i386/i386-builtin.def (__builtin_ia32_insertps128):
Use CODE_FOR_sse4_1_insertps_v4sf.
* config/i386/i386-expand.cc (expand_vec_perm_insertps): New.
(expand_vec_perm_1): Call expand_vec_per_insertps.
* config/i386/i386.md ("unspec"): Declare UNSPEC_INSERTPS here.
* config/i386/mmx.md (mmxscalarmode): New mode attribute.
(@sse4_1_insertps_<mode>): New insn pattern.
* config/i386/sse.md (@sse4_1_insertps_<mode>): Macroize insn
pattern from sse4_1_insertps using VI4F_128 mode iterator.
2023-04-18 Aldy Hernandez <aldyh@redhat.com>
* value-range.cc (gt_ggc_mx): New.
(gt_pch_nx): New.
* value-range.h (class vrange): Add GTY marker.
(class frange): Same.
(gt_ggc_mx): Remove.
(gt_pch_nx): Remove.
2023-04-18 Victor L. Do Nascimento <victor.donascimento@arm.com>
* lra-constraints.cc (constraint_unique): New.
(process_address_1): Apply constraint_unique test.
* recog.cc (constrain_operands): Allow relaxed memory
constaints.
2023-04-18 Kito Cheng <kito.cheng@sifive.com>
* doc/extend.texi (Target Builtins): Add RISC-V Vector
Intrinsics.
(RISC-V Vector Intrinsics): Document GCC implemented which
version of RISC-V vector intrinsics and its reference.
2023-04-18 Richard Biener <rguenther@suse.de>
PR middle-end/108786
* bitmap.h (bitmap_clear_first_set_bit): New.
* bitmap.cc (bitmap_first_set_bit_worker): Rename from
bitmap_first_set_bit and add optional clearing of the bit.
(bitmap_first_set_bit): Wrap bitmap_first_set_bit_worker.
(bitmap_clear_first_set_bit): Likewise.
* df-core.cc (df_worklist_dataflow_doublequeue): Use
bitmap_clear_first_set_bit.
* graphite-scop-detection.cc (scop_detection::merge_sese):
Likewise.
* sanopt.cc (sanitize_asan_mark_unpoison): Likewise.
(sanitize_asan_mark_poison): Likewise.
* tree-cfgcleanup.cc (cleanup_tree_cfg_noloop): Likewise.
* tree-into-ssa.cc (rewrite_blocks): Likewise.
* tree-ssa-dce.cc (simple_dce_from_worklist): Likewise.
* tree-ssa-sccvn.cc (do_rpo_vn_1): Likewise.
2023-04-18 Richard Biener <rguenther@suse.de>
* tree-ssa-structalias.cc (dump_sa_stats): Split out from...
(dump_sa_points_to_info): ... this function.
(compute_points_to_sets): Guard large dumps with TDF_DETAILS,
and call dump_sa_stats guarded with TDF_STATS.
(ipa_pta_execute): Likewise.
(compute_may_aliases): Guard dump_alias_info with
TDF_DETAILS|TDF_ALIAS.
2023-04-18 Andrew Pinski <apinski@marvell.com>
* tree-ssa-phiopt.cc (gimple_simplify_phiopt): Dump
the expression that is being tried when TDF_FOLDING
is true.
(phiopt_worker::match_simplify_replacement): Dump
the sequence which was created by gimple_simplify_phiopt
when TDF_FOLDING is true.
2023-04-18 Andrew Pinski <apinski@marvell.com>
* tree-ssa-phiopt.cc (match_simplify_replacement):
Simplify code that does the movement slightly.
2023-04-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64.md (@aarch64_rev16<mode>): Change to
define_expand.
(rev16<mode>2): Rename to...
(aarch64_rev16<mode>2_alt1): ... This.
(rev16<mode>2_alt): Rename to...
(*aarch64_rev16<mode>2_alt2): ... This.
2023-04-18 Aldy Hernandez <aldyh@redhat.com>
* emit-rtl.cc (init_emit_once): Initialize dconstm0.
* gimple-range-op.cc (class cfn_signbit): Remove dconstm0
declaration.
* range-op-float.cc (zero_range): Use dconstm0.
(zero_to_inf_range): Same.
* real.h (dconstm0): New.
* value-range.cc (frange::flush_denormals_to_zero): Use dconstm0.
(frange::set_zero): Do not declare dconstm0.
2023-04-18 Richard Biener <rguenther@suse.de>
* system.h (class auto_mpz): New,
* realmpfr.h (class auto_mpfr): Likewise.
* fold-const-call.cc (do_mpfr_arg1): Use auto_mpfr.
(do_mpfr_arg2): Likewise.
* tree-ssa-loop-niter.cc (bound_difference): Use auto_mpz;
2023-04-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-builtins.cc (aarch64_init_simd_intrinsics): Take
builtin flags from intrinsic data rather than hardcoded FLAG_AUTO_FP.
2023-04-18 Aldy Hernandez <aldyh@redhat.com>
* value-range.cc (frange::operator==): Adjust for NAN.
(range_tests_nan): Remove some NAN tests.
2023-04-18 Aldy Hernandez <aldyh@redhat.com>
* inchash.cc (hash::add_real_value): New.
* inchash.h (class hash): Add add_real_value.
* value-range.cc (add_vrange): New.
* value-range.h (inchash::add_vrange): New.
2023-04-18 Richard Biener <rguenther@suse.de>
PR tree-optimization/109539
* gimple-ssa-warn-access.cc (pass_waccess::check_pointer_uses):
Re-implement pointer relatedness for PHIs.
2023-04-18 Andrew Stubbs <ams@codesourcery.com>
* config/gcn/gcn-valu.md (SV_SFDF): New iterator.
(SV_FP): New iterator.
(scalar_mode, SCALAR_MODE): Add identity mappings for scalar modes.
(recip<mode>2): Unify the two patterns using SV_FP.
(div_scale<mode><exec_vcc>): New insn.
(div_fmas<mode><exec>): New insn.
(div_fixup<mode><exec>): New insn.
(div<mode>3): Unify the two expanders and rewrite using hardfp.
* config/gcn/gcn.cc (gcn_md_reorg): Support "vccwait" attribute.
* config/gcn/gcn.md (unspec): Add UNSPEC_DIV_SCALE, UNSPEC_DIV_FMAS,
and UNSPEC_DIV_FIXUP.
(vccwait): New attribute.
2023-04-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64.cc (aarch64_validate_mcpu): Add hint to use -march
if the argument matches that.
2023-04-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/atomics.md
(*aarch64_atomic_load<ALLX:mode>_rcpc_zext):
Use SD_HSDI for destination mode iterator.
2023-04-18 Jin Ma <jinma@linux.alibaba.com>
* common/config/riscv/riscv-common.cc (multi_letter_subset_rank): Swap the order
of z-extensions and s-extensions.
(riscv_subset_list::parse): Likewise.
2023-04-18 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/109240
* match.pd (fneg/fadd): Rewrite such that it handles both plus as
first vec_perm operand and minus as second using fneg/fadd and
minus as first vec_perm operand and plus as second using fneg/fsub.
2023-04-18 Aldy Hernandez <aldyh@redhat.com>
* data-streamer.cc (bp_pack_real_value): New.
(bp_unpack_real_value): New.
* data-streamer.h (bp_pack_real_value): New.
(bp_unpack_real_value): New.
* tree-streamer-in.cc (unpack_ts_real_cst_value_fields): Use
bp_unpack_real_value.
* tree-streamer-out.cc (pack_ts_real_cst_value_fields): Use
bp_pack_real_value.
2023-04-18 Aldy Hernandez <aldyh@redhat.com>
* wide-int.h (WIDE_INT_MAX_HWIS): New.
(class fixed_wide_int_storage): Use it.
(trailing_wide_ints <N>::set_precision): Use it.
(trailing_wide_ints <N>::extra_size): Use it.
2023-04-18 Xi Ruoyao <xry111@xry111.site>
* config/loongarch/loongarch-protos.h
(loongarch_addu16i_imm12_operand_p): New function prototype.
(loongarch_split_plus_constant): Likewise.
* config/loongarch/loongarch.cc
(loongarch_addu16i_imm12_operand_p): New function.
(loongarch_split_plus_constant): Likewise.
* config/loongarch/loongarch.h (ADDU16I_OPERAND): New macro.
(DUAL_IMM12_OPERAND): Likewise.
(DUAL_ADDU16I_OPERAND): Likewise.
* config/loongarch/constraints.md (La, Lb, Lc, Ld, Le): New
constraint.
* config/loongarch/predicates.md (const_dual_imm12_operand): New
predicate.
(const_addu16i_operand): Likewise.
(const_addu16i_imm12_di_operand): Likewise.
(const_addu16i_imm12_si_operand): Likewise.
(plus_di_operand): Likewise.
(plus_si_operand): Likewise.
(plus_si_extend_operand): Likewise.
* config/loongarch/loongarch.md (add<mode>3): Convert to
define_insn_and_split. Use plus_<mode>_operand predicate
instead of arith_operand. Add alternatives for La, Lb, Lc, Ld,
and Le constraints.
(*addsi3_extended): Convert to define_insn_and_split. Use
plus_si_extend_operand instead of arith_operand. Add
alternatives for La and Le alternatives.
2023-04-18 Aldy Hernandez <aldyh@redhat.com>
* value-range.h (Value_Range::Value_Range): New.
(Value_Range::contains_p): New.
2023-04-18 Aldy Hernandez <aldyh@redhat.com>
* value-range.h (class vrange): Make m_discriminator const.
(class irange): Make m_max_ranges const. Adjust constructors
accordingly.
(class unsupported_range): Construct vrange appropriately.
(class frange): Same.
2023-04-18 Lulu Cheng <chenglulu@loongson.cn>
* config/loongarch/loongarch.h (LOGICAL_OP_NON_SHORT_CIRCUIT): Remove the macro
definition.
2023-04-18 Lulu Cheng <chenglulu@loongson.cn>
* doc/extend.texi: Add section for LoongArch Base Built-in functions.
2023-04-18 Fei Gao <gaofei@eswincomputing.com>
* config/riscv/riscv.cc (riscv_first_stack_step): Make codes more
readable.
(riscv_expand_epilogue): Likewise.
2023-04-17 Fei Gao <gaofei@eswincomputing.com>
* config/riscv/riscv.cc (riscv_expand_prologue): Consider save-restore in
stack allocation.
(riscv_expand_epilogue): Consider save-restore in stack deallocation.
2023-04-17 Andrew Pinski <apinski@marvell.com>
* tree-ssa-phiopt.cc (gate_hoist_loads): Remove
prototype.
2023-04-17 Aldy Hernandez <aldyh@redhat.com>
* gimple-ssa-warn-alloca.cc (pass_walloca::execute): Do not export
global ranges.
2023-04-17 Fei Gao <gaofei@eswincomputing.com>
* config/riscv/riscv.cc (riscv_first_stack_step): Add a new function
parameter remaining_size.
(riscv_compute_frame_info): Adapt new riscv_first_stack_step interface.
(riscv_expand_prologue): Likewise.
(riscv_expand_epilogue): Likewise.
2023-04-17 Feng Wang <wangfeng@eswincomputing.com>
* config/riscv/bitmanip.md (rotrsi3_sext): Support generating
roriw for constant counts.
* rtl.h (reverse_rotate_by_imm_p): Add function declartion
* simplify-rtx.cc (reverse_rotate_by_imm_p): New function.
(simplify_context::simplify_binary_operation_1): Use it.
* expmed.cc (expand_shift_1): Likewise.
2023-04-17 Martin Jambor <mjambor@suse.cz>
PR ipa/107769
PR ipa/109318
* cgraph.h (symtab_node::find_reference): Add parameter use_type.
* ipa-prop.h (ipa_pass_through_data): New flag refdesc_decremented.
(ipa_zap_jf_refdesc): New function.
(ipa_get_jf_pass_through_refdesc_decremented): Likewise.
(ipa_set_jf_pass_through_refdesc_decremented): Likewise.
* ipa-cp.cc (ipcp_discover_new_direct_edges): Provide a value for
the new parameter of find_reference.
(adjust_references_in_caller): Likewise. Make sure the constant jump
function is not used to decrement a refdec counter again. Only
decrement refdesc counters when the pass_through jump function allows
it. Added a detailed dump when decrementing refdesc counters.
* ipa-prop.cc (ipa_print_node_jump_functions_for_edge): Dump new flag.
(ipa_set_jf_simple_pass_through): Initialize the new flag.
(ipa_set_jf_unary_pass_through): Likewise.
(ipa_set_jf_arith_pass_through): Likewise.
(remove_described_reference): Provide a value for the new parameter of
find_reference.
(update_jump_functions_after_inlining): Zap refdesc of new jfunc if
the previous pass_through had a flag mandating that we do so.
(propagate_controlled_uses): Likewise. Only decrement refdesc
counters when the pass_through jump function allows it.
(ipa_edge_args_sum_t::duplicate): Provide a value for the new
parameter of find_reference.
(ipa_write_jump_function): Assert the new flag does not have to be
streamed.
* symtab.cc (symtab_node::find_reference): Add parameter use_type, use
it in searching.
2023-04-17 Philipp Tomsich <philipp.tomsich@vrull.eu>
Di Zhao <di.zhao@amperecomputing.com>
* config/aarch64/aarch64-tuning-flags.def (AARCH64_EXTRA_TUNING_OPTION):
Add AARCH64_EXTRA_TUNE_NO_LDP_COMBINE.
* config/aarch64/aarch64.cc (aarch64_operands_ok_for_ldpstp):
Check for the above tuning option when processing loads.
2023-04-17 Richard Biener <rguenther@suse.de>
PR tree-optimization/109524
* tree-vrp.cc (remove_unreachable::m_list): Change to a
vector of pairs of block indices.
(remove_unreachable::maybe_register_block): Adjust.
(remove_unreachable::remove_and_update_globals): Likewise.
Deal with removed blocks.
2023-04-16 Jeff Law <jlaw@ventanamicro>
PR target/109508
* config/riscv/riscv.cc (riscv_expand_conditional_move): For
TARGET_SFB_ALU, force the true arm into a register.
2023-04-15 John David Anglin <danglin@gcc.gnu.org>
PR target/104989
* config/pa/pa-protos.h (pa_function_arg_size): Update prototype.
* config/pa/pa.cc (pa_function_arg): Return NULL_RTX if argument
size is zero.
(pa_arg_partial_bytes): Don't call pa_function_arg_size twice.
(pa_function_arg_size): Change return type to int. Return zero
for arguments larger than 1 GB. Update comments.
2023-04-15 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/109154
* tree-if-conv.cc (predicate_scalar_phi): For complex PHIs, emit just
args_len - 1 COND_EXPRs rather than args_len. Formatting fix.
2023-04-15 Jason Merrill <jason@redhat.com>
PR c++/109514
* gimple-ssa-warn-access.cc (pass_waccess::check_dangling_stores):
Overhaul lhs_ref.ref analysis.
2023-04-14 Richard Biener <rguenther@suse.de>
PR tree-optimization/109502
* tree-vect-stmts.cc (vectorizable_assignment): Fix
check for conversion between mask and non-mask types.
2023-04-14 Jeff Law <jlaw@ventanamicro.com>
Jakub Jelinek <jakub@redhat.com>
PR target/108947
PR target/109040
* combine.cc (simplify_and_const_int_1): Compute nonzero_bits in
word_mode rather than mode if WORD_REGISTER_OPERATIONS and mode is
smaller than word_mode.
* simplify-rtx.cc (simplify_context::simplify_binary_operation_1)
<case AND>: Likewise.
2023-04-14 Jakub Jelinek <jakub@redhat.com>
* loop-iv.cc (iv_number_of_iterations): Use gen_int_mode instead
of GEN_INT.
2023-04-13 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/108139
PR tree-optimization/109462
* gimple-range-cache.cc (ranger_cache::fill_block_cache): Remove
equivalency check for PHI nodes.
* gimple-range-fold.cc (fold_using_range::range_of_phi): Ensure def
does not dominate single-arg equivalency edges.
2023-04-13 Richard Sandiford <richard.sandiford@arm.com>
PR target/108910
* config/aarch64/aarch64.cc (aarch64_function_arg_alignment): Do
not trust TYPE_ALIGN for pointer types; use POINTER_SIZE instead.
2023-04-13 Richard Biener <rguenther@suse.de>
PR tree-optimization/109491
* tree-ssa-sccvn.cc (expressions_equal_p): Restore the
NULL operands test.
2023-04-12 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
PR target/109479
* config/riscv/riscv-vector-builtins-types.def (vint8mf8_t): Fix predicate.
(vint16mf4_t): Ditto.
(vint32mf2_t): Ditto.
(vint64m1_t): Ditto.
(vint64m2_t): Ditto.
(vint64m4_t): Ditto.
(vint64m8_t): Ditto.
(vuint8mf8_t): Ditto.
(vuint16mf4_t): Ditto.
(vuint32mf2_t): Ditto.
(vuint64m1_t): Ditto.
(vuint64m2_t): Ditto.
(vuint64m4_t): Ditto.
(vuint64m8_t): Ditto.
(vfloat32mf2_t): Ditto.
(vbool64_t): Ditto.
* config/riscv/riscv-vector-builtins.cc (register_builtin_type): Add comments.
(register_vector_type): Ditto.
(check_required_extensions): Fix condition.
* config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_ZVE64): Remove it.
(RVV_REQUIRE_ELEN_64): New define.
(RVV_REQUIRE_MIN_VLEN_64): Ditto.
* config/riscv/riscv-vector-switch.def (TARGET_VECTOR_FP32): Remove it.
(TARGET_VECTOR_FP64): Ditto.
(ENTRY): Fix predicate.
* config/riscv/vector-iterators.md: Fix predicate.
2023-04-12 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/109410
* tree-ssa-reassoc.cc (build_and_add_sum): Split edge from entry
block if first statement of the function is a call to returns_twice
function.
2023-04-12 Jakub Jelinek <jakub@redhat.com>
PR target/109458
* config/i386/i386.cc: Include rtl-error.h.
(ix86_print_operand): For z modifier warning, use warning_for_asm
if this_is_asm_operands. For Z modifier errors, use %c and code
instead of hardcoded Z.
2023-04-12 Costas Argyris <costas.argyris@gmail.com>
* config/i386/x-mingw32-utf8: Remove extrataneous $@
2023-04-12 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/109462
* gimple-range-cache.cc (ranger_cache::fill_block_cache): Don't
check for equivalences if NAME is a phi node.
2023-04-12 Richard Biener <rguenther@suse.de>
PR tree-optimization/109473
* tree-vect-loop.cc (vect_create_epilog_for_reduction):
Convert scalar result to the computation type before performing
the reduction adjustment.
2023-04-12 Richard Biener <rguenther@suse.de>
PR tree-optimization/109469
* tree-vect-slp.cc (vect_slp_function): Skip region starts with
a returns-twice call.
2023-04-12 Richard Biener <rguenther@suse.de>
PR tree-optimization/109434
* tree-ssa-dse.cc (initialize_ao_ref_for_dse): Properly
handle possibly throwing calls when processing the LHS
and may-defs are not OK.
2023-04-11 Lin Sinan <mynameisxiaou@gmail.com>
* config/riscv/predicates.md (uimm_extra_bit_or_twobits): Adjust
predicate to avoid splitting arith constants.
2023-04-11 Yanzhang Wang <yanzhang.wang@intel.com>
Pan Li <pan2.li@intel.com>
Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Kito Cheng <kito.cheng@sifive.com>
PR target/109104
* config/riscv/riscv-protos.h (emit_hard_vlmax_vsetvl): New.
* config/riscv/riscv-v.cc (emit_hard_vlmax_vsetvl): New.
(emit_vlmax_vsetvl): Use emit_hard_vlmax_vsetvl.
* config/riscv/riscv.cc (vector_zero_call_used_regs): New.
(riscv_zero_call_used_regs): New.
(TARGET_ZERO_CALL_USED_REGS): New.
2023-04-11 Martin Liska <mliska@suse.cz>
PR driver/108241
* opts.cc (finish_options): Drop also
x_flag_var_tracking_assignments.
2023-04-11 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR tree-optimization/108888
* tree-if-conv.cc (predicate_statements): Fix gimple call check.
2023-04-11 Haochen Gui <guihaoc@gcc.gnu.org>
PR target/108812
* config/rs6000/vsx.md (vsx_sign_extend_qi_<mode>): Rename to...
(vsx_sign_extend_v16qi_<mode>): ... this.
(vsx_sign_extend_hi_<mode>): Rename to...
(vsx_sign_extend_v8hi_<mode>): ... this.
(vsx_sign_extend_si_v2di): Rename to...
(vsx_sign_extend_v4si_v2di): ... this.
(vsignextend_qi_<mode>): Remove.
(vsignextend_hi_<mode>): Remove.
(vsignextend_si_v2di): Remove.
(vsignextend_v2di_v1ti): Remove.
(*xxspltib_<mode>_split): Replace gen_vsx_sign_extend_qi_v2di with
gen_vsx_sign_extend_v16qi_v2di and gen_vsx_sign_extend_qi_v4si
with gen_vsx_sign_extend_v16qi_v4si.
* config/rs6000/rs6000.md (split for DI constant generation):
Replace gen_vsx_sign_extend_qi_si with gen_vsx_sign_extend_v16qi_si.
(split for HSDI constant generation): Replace gen_vsx_sign_extend_qi_di
with gen_vsx_sign_extend_v16qi_di and gen_vsx_sign_extend_qi_si
with gen_vsx_sign_extend_v16qi_si.
* config/rs6000/rs6000-builtins.def (__builtin_altivec_vsignextsb2d):
Set bif-pattern to vsx_sign_extend_v16qi_v2di.
(__builtin_altivec_vsignextsb2w): Set bif-pattern to
vsx_sign_extend_v16qi_v4si.
(__builtin_altivec_visgnextsh2d): Set bif-pattern to
vsx_sign_extend_v8hi_v2di.
(__builtin_altivec_vsignextsh2w): Set bif-pattern to
vsx_sign_extend_v8hi_v4si.
(__builtin_altivec_vsignextsw2d): Set bif-pattern to
vsx_sign_extend_si_v2di.
(__builtin_altivec_vsignext): Set bif-pattern to
vsx_sign_extend_v2di_v1ti.
* config/rs6000/rs6000-builtin.cc (lxvrse_expand_builtin): Replace
gen_vsx_sign_extend_qi_v2di with gen_vsx_sign_extend_v16qi_v2di,
gen_vsx_sign_extend_hi_v2di with gen_vsx_sign_extend_v8hi_v2di and
gen_vsx_sign_extend_si_v2di with gen_vsx_sign_extend_v4si_v2di.
2023-04-10 Michael Meissner <meissner@linux.ibm.com>
PR target/70243
* config/rs6000/vsx.md (vsx_fmav4sf4): Do not generate vmaddfp.
(vsx_nfmsv4sf4): Do not generate vnmsubfp.
2023-04-10 Haochen Jiang <haochen.jiang@intel.com>
* config/i386/i386.h (PTA_GRANITERAPIDS): Add PTA_AMX_COMPLEX.
2023-04-10 Haochen Jiang <haochen.jiang@intel.com>
* common/config/i386/cpuinfo.h (get_available_features):
Detect AMX-COMPLEX.
* common/config/i386/i386-common.cc
(OPTION_MASK_ISA2_AMX_COMPLEX_SET,
OPTION_MASK_ISA2_AMX_COMPLEX_UNSET): New.
(ix86_handle_option): Handle -mamx-complex.
* common/config/i386/i386-cpuinfo.h (enum processor_features):
Add FEATURE_AMX_COMPLEX.
* common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for
amx-complex.
* config.gcc: Add amxcomplexintrin.h.
* config/i386/cpuid.h (bit_AMX_COMPLEX): New.
* config/i386/i386-c.cc (ix86_target_macros_internal): Define
__AMX_COMPLEX__.
* config/i386/i386-isa.def (AMX_COMPLEX): Add DEF_PTA(AMX_COMPLEX).
* config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p):
Handle amx-complex.
* config/i386/i386.opt: Add option -mamx-complex.
* config/i386/immintrin.h: Include amxcomplexintrin.h.
* doc/extend.texi: Document amx-complex.
* doc/invoke.texi: Document -mamx-complex.
* doc/sourcebuild.texi: Document target amx-complex.
* config/i386/amxcomplexintrin.h: New file.
2023-04-08 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/109392
* tree-vect-generic.cc (tree_vec_extract): Handle failure
of maybe_push_res_to_seq better.
2023-04-08 Jakub Jelinek <jakub@redhat.com>
* Makefile.in (CORETYPES_H): Depend on align.h, poly-int.h and
poly-int-types.h.
(SYSTEM_H): Depend on $(HASHTAB_H).
* config/riscv/t-riscv (build/genrvv-type-indexer.o): Remove unused
dependency on $(RTL_BASE_H), remove redundant dependency on
insn-modes.h.
2023-04-06 Richard Earnshaw <rearnsha@arm.com>
PR target/107674
* config/arm/arm.cc (arm_effective_regno): New function.
(mve_vector_mem_operand): Use it.
2023-04-06 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/109417
* gimple-range-gori.cc (gori_compute::may_recompute_p): Check if
dependency is in SSA_NAME_FREE_LIST.
2023-04-06 Andrew Pinski <apinski@marvell.com>
PR tree-optimization/109427
* params.opt (-param=vect-induction-float=):
Fix option attribute typo for IntegerRange.
2023-04-05 Jeff Law <jlaw@ventanamicro>
PR target/108892
* combine.cc (combine_instructions): Force re-recognition when
after restoring the body of an insn to its original form.
2023-04-05 Martin Jambor <mjambor@suse.cz>
PR ipa/108959
* ipa-sra.cc (zap_useless_ipcp_results): New function.
(process_isra_node_results): Call it.
2023-04-05 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/vector.md: Fix incorrect operand order.
2023-04-05 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vsetvl.cc
(pass_vsetvl::compute_local_backward_infos): Update user vsetvl in local
demand fusion.
2023-04-05 Li Xu <xuli1@eswincomputing.com>
* config/riscv/riscv-vector-builtins.def: Fix typo.
* config/riscv/riscv.cc (riscv_dwarf_poly_indeterminate_value): Ditto.
* config/riscv/vector-iterators.md: Ditto.
2023-04-04 Hans-Peter Nilsson <hp@axis.com>
* doc/md.texi (Including Patterns): Fix page break.
2023-04-04 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/109386
* range-op-float.cc (foperator_lt::op1_range, foperator_lt::op2_range,
foperator_le::op1_range, foperator_le::op2_range,
foperator_gt::op1_range, foperator_gt::op2_range,
foperator_ge::op1_range, foperator_ge::op2_range): Make r varying for
BRS_FALSE case even if the other op is maybe_isnan, not just
known_isnan.
(foperator_unordered_lt::op1_range, foperator_unordered_lt::op2_range,
foperator_unordered_le::op1_range, foperator_unordered_le::op2_range,
foperator_unordered_gt::op1_range, foperator_unordered_gt::op2_range,
foperator_unordered_ge::op1_range, foperator_unordered_ge::op2_range):
Make r varying for BRS_TRUE case even if the other op is maybe_isnan,
not just known_isnan.
2023-04-04 Marek Polacek <polacek@redhat.com>
PR sanitizer/109107
* fold-const.cc (fold_binary_loc): Use TYPE_OVERFLOW_SANITIZED
when associating.
* match.pd: Use TYPE_OVERFLOW_SANITIZED.
2023-04-04 Stam Markianos-Wright <stam.markianos-wright@arm.com>
* config/arm/mve.md (mve_vcvtq_n_to_f_<supf><mode>): Swap operands.
(mve_vcreateq_f<mode>): Swap operands.
2023-04-04 Andrew Stubbs <ams@codesourcery.com>
* config/gcn/gcn-valu.md (one_cmpl<mode>2<exec>): New.
2023-04-04 Jakub Jelinek <jakub@redhat.com>
PR target/109384
* common/config/riscv/riscv-common.cc (riscv_subset_list::parse):
Reword diagnostics about zfinx conflict with f, formatting fixes.
2023-04-04 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* config/sol2.h (LIB_SPEC): Don't link with -lpthread.
2023-04-04 Richard Biener <rguenther@suse.de>
PR tree-optimization/109304
* tree-profile.cc (tree_profiling): Use symtab node
availability to decide whether to skip adjusting calls.
Do not adjust calls to internal functions.
2023-04-04 Kewen Lin <linkw@linux.ibm.com>
PR target/108807
* config/rs6000/rs6000.cc (rs6000_expand_vector_set_var_p9): Fix gen
function for permutation control vector by considering big endianness.
2023-04-04 Kewen Lin <linkw@linux.ibm.com>
PR target/108699
* config/rs6000/altivec.md (*p9v_parity<mode>2): Rename to ...
(rs6000_vprtyb<mode>2): ... this.
* config/rs6000/rs6000-builtins.def (VPRTYBD): Replace parityv2di2 with
rs6000_vprtybv2di2.
(VPRTYBW): Replace parityv4si2 with rs6000_vprtybv4si2.
(VPRTYBQ): Replace parityv1ti2 with rs6000_vprtybv1ti2.
* config/rs6000/vector.md (parity<mode>2 with VEC_IP): Expand with
popcountv16qi2 and the corresponding rs6000_vprtyb<mode>2.
2023-04-04 Hans-Peter Nilsson <hp@axis.com>
Sandra Loosemore <sandra@codesourcery.com>
* doc/md.texi (Insn Splitting): Tweak wording for readability.
2023-04-03 Martin Jambor <mjambor@suse.cz>
PR ipa/109303
* ipa-prop.cc (determine_known_aggregate_parts): Check that the
offset + size will be representable in unsigned int.
2023-04-03 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
* configure.ac (ZSTD_LIB): Move before zstd.h check.
Unset gcc_cv_header_zstd_h without libzstd.
* configure: Regenerate.
2023-04-03 Martin Liska <mliska@suse.cz>
* doc/invoke.texi: Document new param.
2023-04-03 Cupertino Miranda <cupertino.miranda@oracle.com>
* doc/sourcebuild.texi (const_volatile_readonly_section): Document
new check_effective_target function.
2023-04-03 Li Xu <xuli1@eswincomputing.com>
* config/riscv/riscv-vector-builtins.def (vuint32m8_t): Fix typo.
(vfloat32m8_t): Likewise
2023-04-03 liuhongt <hongtao.liu@intel.com>
* doc/md.texi: Document signbitm2.
2023-04-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
kito-cheng <kito.cheng@sifive.com>
* config/riscv/vector.md: Fix RA constraint.
2023-04-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-protos.h (gen_avl_for_scalar_move): New function.
* config/riscv/riscv-v.cc (gen_avl_for_scalar_move): New function.
* config/riscv/vector.md: Fix scalar move bug.
2023-04-01 Jakub Jelinek <jakub@redhat.com>
* range-op-float.cc (foperator_equal::fold_range): If at least
one of the op ranges is not singleton and neither is NaN and all
4 bounds are zero, return [1, 1].
(foperator_not_equal::fold_range): In the same case return [0, 0].
2023-04-01 Jakub Jelinek <jakub@redhat.com>
* range-op-float.cc (foperator_equal::fold_range): Perform the
non-singleton handling regardless of maybe_isnan (op1, op2).
(foperator_not_equal::fold_range): Likewise.
(foperator_lt::fold_range, foperator_le::fold_range,
foperator_gt::fold_range, foperator_ge::fold_range): Perform the
real_* comparison check which results in range_false (type)
even if maybe_isnan (op1, op2). Simplify.
(foperator_ltgt): New class.
(fop_ltgt): New variable.
(floating_op_table::floating_op_table): Handle LTGT_EXPR using
fop_ltgt.
2023-04-01 Jakub Jelinek <jakub@redhat.com>
PR target/109254
* builtins.cc (apply_args_size): If targetm.calls.get_raw_arg_mode
returns VOIDmode, handle it like if the register isn't used for
passing arguments at all.
(apply_result_size): If targetm.calls.get_raw_result_mode returns
VOIDmode, handle it like if the register isn't used for returning
results at all.
* target.def (get_raw_result_mode, get_raw_arg_mode): Document what it
means to return VOIDmode.
* doc/tm.texi: Regenerated.
* config/aarch64/aarch64.cc (aarch64_function_value_regno_p): Return
TARGET_SVE for P0_REGNUM.
(aarch64_function_arg_regno_p): Also return true for p0-p3.
(aarch64_get_reg_raw_mode): Return VOIDmode for PR_REGNUM_P regs.
2023-03-31 Vladimir N. Makarov <vmakarov@redhat.com>
* lra-constraints.cc: (combine_reload_insn): New function.
2023-03-31 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/91645
* range-op-float.cc (foperator_unordered_lt::fold_range,
foperator_unordered_le::fold_range,
foperator_unordered_gt::fold_range,
foperator_unordered_ge::fold_range,
foperator_unordered_equal::fold_range): Call the ordered
fold_range on ranges with cleared NaNs.
* value-query.cc (range_query::get_tree_range): Handle also
COMPARISON_CLASS_P trees.
2023-03-31 Kito Cheng <kito.cheng@sifive.com>
Andrew Pinski <pinskia@gmail.com>
PR target/109328
* config/riscv/t-riscv: Add missing dependencies.
2023-03-31 liuhongt <hongtao.liu@intel.com>
* config/i386/i386.cc (inline_memory_move_cost): Return 100
for MASK_REGS when MODE_SIZE > 8.
2023-03-31 liuhongt <hongtao.liu@intel.com>
PR target/85048
* config/i386/i386-builtin.def (BDESC): Adjust icode name from
ufloat/ufix to floatuns/fixuns.
* config/i386/i386-expand.cc
(ix86_expand_vector_convert_uns_vsivsf): Adjust comments.
* config/i386/sse.md
(ufloat<sseintvecmodelower><mode>2<mask_name><round_name>):
Renamed to ..
(<mask_codefor>floatuns<sseintvecmodelower><mode>2<mask_name><round_name>):.. this.
(<mask_codefor><avx512>_ufix_notrunc<sf2simodelower><mode><mask_name><round_name>):
Renamed to ..
(<mask_codefor><avx512>_fixuns_notrunc<sf2simodelower><mode><mask_name><round_name>):
.. this.
(<fixsuffix>fix_truncv16sfv16si2<mask_name><round_saeonly_name>):
Renamed to ..
(fix<fixunssuffix>_truncv16sfv16si2<mask_name><round_saeonly_name>):.. this.
(ufloat<si2dfmodelower><mode>2<mask_name>): Renamed to ..
(floatuns<si2dfmodelower><mode>2<mask_name>): .. this.
(ufloatv2siv2df2<mask_name>): Renamed to ..
(<mask_codefor>floatunsv2siv2df2<mask_name>): .. this.
(ufix_notrunc<mode><si2dfmodelower>2<mask_name><round_name>):
Renamed to ..
(fixuns_notrunc<mode><si2dfmodelower>2<mask_name><round_name>):
.. this.
(ufix_notruncv2dfv2si2): Renamed to ..
(fixuns_notruncv2dfv2si2):.. this.
(ufix_notruncv2dfv2si2_mask): Renamed to ..
(fixuns_notruncv2dfv2si2_mask): .. this.
(*ufix_notruncv2dfv2si2_mask_1): Renamed to ..
(*fixuns_notruncv2dfv2si2_mask_1): .. this.
(ufix_truncv2dfv2si2): Renamed to ..
(*fixuns_truncv2dfv2si2): .. this.
(ufix_truncv2dfv2si2_mask): Renamed to ..
(fixuns_truncv2dfv2si2_mask): .. this.
(*ufix_truncv2dfv2si2_mask_1): Renamed to ..
(*fixuns_truncv2dfv2si2_mask_1): .. this.
(ufix_truncv4dfv4si2<mask_name>): Renamed to ..
(fixuns_truncv4dfv4si2<mask_name>): .. this.
(ufix_notrunc<mode><sseintvecmodelower>2<mask_name><round_name>):
Renamed to ..
(fixuns_notrunc<mode><sseintvecmodelower>2<mask_name><round_name>):
.. this.
(ufix_trunc<mode><sseintvecmodelower>2<mask_name>): Renamed to ..
(<mask_codefor>fixuns_trunc<mode><sseintvecmodelower>2<mask_name>):
.. this.
2023-03-30 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/109154
* gimple-range-gori.cc (gori_compute::may_recompute_p): Add depth limit.
* gimple-range-gori.h (may_recompute_p): Add depth param.
* params.opt (ranger-recompute-depth): New param.
2023-03-30 Jason Merrill <jason@redhat.com>
PR c++/107897
PR c++/108887
* cgraph.h: Move reset() from cgraph_node to symtab_node.
* cgraphunit.cc (symtab_node::reset): Adjust. Also call
remove_from_same_comdat_group.
2023-03-30 Richard Biener <rguenther@suse.de>
PR tree-optimization/107561
* gimple-ssa-warn-access.cc (get_size_range): Add flags
argument and pass it on.
(check_access): When querying for the size range pass
SR_ALLOW_ZERO when the known destination size is zero.
2023-03-30 Richard Biener <rguenther@suse.de>
PR tree-optimization/109342
* tree-ssa-sccvn.cc (vn_nary_op_get_predicated_value): New
overload for edge. When that edge is a backedge use
dominated_by_p directly.
2023-03-30 liuhongt <hongtao.liu@intel.com>
* config/i386/i386-expand.cc (expand_vec_perm_blend): Generate
vpblendd instead of vpblendw for V4SI under avx2.
2023-03-29 Hans-Peter Nilsson <hp@axis.com>
* config/cris/cris.cc (cris_rtx_costs) [CONST_INT]: Return 0
for many quick operands, for register-sized modes.
2023-03-29 Jiawei <jiawei@iscas.ac.cn>
* common/config/riscv/riscv-common.cc (riscv_subset_list::parse):
New check.
2023-03-29 Martin Liska <mliska@suse.cz>
PR bootstrap/109310
* configure.ac: Emit a warning for deprecated option
--enable-link-mutex.
* configure: Regenerate.
2023-03-29 Richard Biener <rguenther@suse.de>
PR tree-optimization/109331
* tree-ssa-forwprop.cc (pass_forwprop::execute): When we
discover a taken edge make sure to cleanup the CFG.
2023-03-29 Richard Biener <rguenther@suse.de>
PR tree-optimization/109327
* tree-ssa-forwprop.cc (pass_forwprop::execute): Deal with
already removed stmts when draining to_remove.
2023-03-29 Richard Biener <rguenther@suse.de>
PR ipa/106124
* dwarf2out.cc (lookup_type_die): Reset TREE_ASM_WRITTEN
so we can re-create the DIE for the type if required.
2023-03-29 Jakub Jelinek <jakub@redhat.com>
Richard Biener <rguenther@suse.de>
PR tree-optimization/109301
* tree-ssa-math-opts.cc (pass_data_cse_sincos): Change
properties_provided from PROP_gimple_opt_math to 0.
(pass_data_expand_powcabs): Change properties_provided from 0 to
PROP_gimple_opt_math.
2023-03-29 Richard Biener <rguenther@suse.de>
PR tree-optimization/109154
* tree-if-conv.cc (gen_phi_arg_condition): Handle single
inverted condition specially by inverting at the caller.
(gen_phi_arg_condition): Swap COND_EXPR arms if requested.
2023-03-28 David Malcolm <dmalcolm@redhat.com>
PR c/107002
* diagnostic-show-locus.cc (column_range::column_range): Factor
out assertion conditional into...
(column_range::valid_p): ...this new function.
(line_corrections::add_hint): Don't attempt to consolidate hints
if it would lead to invalid column_range instances.
2023-03-28 Kito Cheng <kito.cheng@sifive.com>
PR target/109312
* config/riscv/riscv-c.cc (riscv_ext_version_value): New.
(riscv_cpu_cpp_builtins): Define __riscv_v_intrinsic and
minor refactor.
2023-03-28 Alexander Monakov <amonakov@ispras.ru>
PR rtl-optimization/109187
* haifa-sched.cc (autopref_rank_for_schedule): Avoid use of overflowing
subtraction in three-way comparison.
2023-03-28 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/109265
PR tree-optimization/109274
* gimple-range-gori.cc (gori_compute::compute_operand_range): Do
not create a relation record is op1 and op2 are the same symbol.
(gori_compute::compute_operand1_range): Pass op1 == op2 to the
handler for this stmt, but create a new record only if this statement
generates a relation based on the ranges.
(gori_compute::compute_operand2_range): Ditto.
* value-relation.h (value_relation::set_relation): Always create the
record that is requested.
2023-03-28 Richard Biener <rguenther@suse.de>
PR tree-optimization/107087
* tree-ssa-forwprop.cc (pass_forwprop::execute): Track
executable regions to avoid useless work and to better
propagate degenerate PHIs.
2023-03-28 Costas Argyris <costas.argyris@gmail.com>
* config/i386/x-mingw32-utf8: update comments.
2023-03-28 Richard Sandiford <richard.sandiford@arm.com>
PR target/109072
* config/aarch64/aarch64-protos.h (aarch64_vector_load_decl): Declare.
* config/aarch64/aarch64.h (machine_function::vector_load_decls): New
variable.
* config/aarch64/aarch64-builtins.cc (aarch64_record_vector_load_arg):
New function.
(aarch64_general_gimple_fold_builtin): Delay folding of vld1 until
after inlining. Record which decls are loaded from. Fix handling
of vops for loads and stores.
* config/aarch64/aarch64.cc (aarch64_vector_load_decl): New function.
(aarch64_accesses_vector_load_decl_p): Likewise.
(aarch64_vector_costs::m_stores_to_vector_load_decl): New member
variable.
(aarch64_vector_costs::add_stmt_cost): If the function has a vld1
that loads from a decl, treat vector stores to those decls as
zero cost.
(aarch64_vector_costs::finish_cost): ...and in that case,
if the vector code does nothing more than a store, give the
prologue a zero cost as well.
2023-03-28 Richard Biener <rguenther@suse.de>
PR bootstrap/84402
PR tree-optimization/108129
* genmatch.cc (lower_for): For (match ...) delay
substituting into the match operator if possible.
(dt_operand::gen_gimple_expr): For user_id look at the
first substitute for determining how to access operands.
(dt_operand::gen_generic_expr): Likewise.
(dt_node::gen_kids): Properly sort user_ids according
to their substitutes.
(dt_node::gen_kids_1): Code-generate user_id matching.
2023-03-28 Jakub Jelinek <jakub@redhat.com>
Jonathan Wakely <jwakely@redhat.com>
* gcov-tool.cc (do_merge, do_merge_stream, do_rewrite, do_overlap):
Use subcommand rather than sub-command in function comments.
2023-03-28 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/109154
* value-range.h (frange::flush_denormals_to_zero): Make it public
rather than private.
* value-range.cc (frange::set): Don't call flush_denormals_to_zero
here.
* range-op-float.cc (range_operator_float::fold_range): Call
flush_denormals_to_zero.
2023-03-28 Jakub Jelinek <jakub@redhat.com>
PR middle-end/106190
* sanopt.cc (pass_sanopt::execute): Return TODO_cleanup_cfg if any
of the IFN_{UB,HWA,A}SAN_* internal fns are lowered.
2023-03-28 Jakub Jelinek <jakub@redhat.com>
* range-op-float.cc (float_widen_lhs_range): Use pass get_nan_state
as 4th argument to set to avoid clear_nan and union_ calls.
2023-03-28 Jakub Jelinek <jakub@redhat.com>
PR target/109276
* config/i386/i386.cc (assign_386_stack_local): For DImode
with SLOT_FLOATxFDI_387 and -m32 -mpreferred-stack-boundary=2 pass
align 32 rather than 0 to assign_stack_local.
2023-03-28 Eric Botcazou <ebotcazou@adacore.com>
PR target/109140
* config/sparc/sparc.cc (sparc_expand_vcond): Call signed_condition
on operand #3 to get the final condition code. Use std::swap.
* config/sparc/sparc.md (vcondv8qiv8qi): New VIS 4 expander.
(fucmp<gcond:code>8<P:mode>_vis): Move around.
(fpcmpu<gcond:code><GCM:gcm_name><P:mode>_vis): Likewise.
(vcondu<GCM:mode><GCM:mode>): New VIS 4 expander.
2023-03-28 Eric Botcazou <ebotcazou@adacore.com>
* doc/gm2.texi: Add missing Next, Previous and Top fields to most
top-level sections.
2023-03-28 Costas Argyris <costas.argyris@gmail.com>
* config.host: Pull in i386/x-mingw32-utf8 Makefile
fragment and reference utf8rc-mingw32.o explicitly
for mingw hosts.
* config/i386/sym-mingw32.cc: prevent name mangling of
stub symbol.
* config/i386/x-mingw32-utf8: Make utf8rc-mingw32.o
depend on manifest file explicitly.
2023-03-28 Richard Biener <rguenther@suse.de>
Revert:
2023-03-27 Richard Biener <rguenther@suse.de>
PR rtl-optimization/109237
* cfgcleanup.cc (bb_is_just_return): Walk insns backwards.
2023-03-28 Richard Biener <rguenther@suse.de>
* common.opt (gdwarf): Remove Negative(gdwarf-).
2023-03-28 Richard Biener <rguenther@suse.de>
* common.opt (gdwarf): Add RejectNegative.
(gdwarf-): Likewise.
(ggdb): Likewise.
(gvms): Likewise.
2023-03-28 Hans-Peter Nilsson <hp@axis.com>
* config/cris/constraints.md ("T"): Correct to
define_memory_constraint.
2023-03-28 Hans-Peter Nilsson <hp@axis.com>
* config/cris/cris.md (BW2): New mode-iterator.
(lra_szext_decomposed, lra_szext_decomposed_indirect_with_offset): New
peephole2s.
2023-03-28 Hans-Peter Nilsson <hp@axis.com>
* config/cris/cris.md ("*add<mode>3_addi"): Improve to bail only
for possible eliminable compares.
2023-03-28 Hans-Peter Nilsson <hp@axis.com>
* config/cris/constraints.md ("R"): Remove unused constraint.
2023-03-27 Jonathan Wakely <jwakely@redhat.com>
PR gcov-profile/109297
* gcov-tool.cc (merge_usage): Fix "subcomand" typo.
(merge_stream_usage): Likewise.
(overlap_usage): Likewise.
2023-03-27 Christoph Müllner <christoph.muellner@vrull.eu>
PR target/109296
* config/riscv/thead.md: Add missing mode specifiers.
2023-03-27 Philipp Tomsich <philipp.tomsich@vrull.eu>
Jiangning Liu <jiangning.liu@amperecomputing.com>
Manolis Tsamis <manolis.tsamis@vrull.eu>
* config/aarch64/aarch64.cc: Update vector costs for ampere1.
2023-03-27 Richard Biener <rguenther@suse.de>
PR rtl-optimization/109237
* cfgcleanup.cc (bb_is_just_return): Walk insns backwards.
2023-03-27 Richard Biener <rguenther@suse.de>
PR lto/109263
* lto-wrapper.cc (run_gcc): Parse alternate debug options
as well, they always enable debug.
2023-03-27 Kewen Lin <linkw@linux.ibm.com>
PR target/109167
* config/rs6000/emmintrin.h (_mm_bslli_si128): Move the implementation
from ...
(_mm_slli_si128): ... here. Change to call _mm_bslli_si128 directly.
2023-03-27 Kewen Lin <linkw@linux.ibm.com>
PR target/109082
* config/rs6000/emmintrin.h (_mm_bslli_si128): Check __N is not less
than zero when calling vec_sld.
(_mm_bsrli_si128): Return __A if __N is zero, check __N is bigger than
zero when calling vec_sld.
(_mm_slli_si128): Return __A if _imm5 is zero, check _imm5 is bigger
than zero when calling vec_sld.
2023-03-27 Sandra Loosemore <sandra@codesourcery.com>
* doc/generic.texi (OpenMP): Document OMP_SIMD, OMP_DISTRIBUTE,
OMP_TASKLOOP, and OMP_LOOP with OMP_FOR. Document how collapsed
loops are represented and which fields are vectors. Add
documentation for OMP_FOR_PRE_BODY field. Document internal
form of non-rectangular loops and OMP_FOR_NON_RECTANGULAR.
* tree.def (OMP_FOR): Make documentation consistent with the
Texinfo manual, to fill some gaps and correct errors.
2023-03-26 Andreas Schwab <schwab@linux-m68k.org>
PR target/106282
* config/m68k/m68k.h (FINAL_PRESCAN_INSN): Define.
* config/m68k/m68k.cc (m68k_final_prescan_insn): Define.
(handle_move_double): Call it before handle_movsi.
* config/m68k/m68k-protos.h: Declare it.
2023-03-26 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/109230
* match.pd (fneg/fadd simplify): Verify also odd permutation indexes.
2023-03-26 Jakub Jelinek <jakub@redhat.com>
PR ipa/105685
* predict.cc (compute_function_frequency): Don't call
warn_function_cold if function already has cold attribute.
2023-03-26 Gerald Pfeifer <gerald@pfeifer.com>
* doc/install.texi: Remove anachronistic note
related to languages built and separate source tarballs.
2023-03-25 David Malcolm <dmalcolm@redhat.com>
PR analyzer/109098
* diagnostic-format-sarif.cc (read_until_eof): Delete.
(maybe_read_file): Delete.
(sarif_builder::maybe_make_artifact_content_object): Use
get_source_file_content rather than maybe_read_file.
Reject it if it's not valid UTF-8.
* input.cc (file_cache_slot::get_full_file_content): New.
(get_source_file_content): New.
(selftest::check_cpp_valid_utf8_p): New.
(selftest::test_cpp_valid_utf8_p): New.
(selftest::input_cc_tests): Call selftest::test_cpp_valid_utf8_p.
* input.h (get_source_file_content): New prototype.
2023-03-24 David Malcolm <dmalcolm@redhat.com>
* doc/analyzer.texi (Debugging the Analyzer): Add notes on useful
debugging options.
(Special Functions for Debugging the Analyzer): Convert to a
table, and rewrite in places.
(Other Debugging Techniques): Add notes on how to compare two
different exploded graphs.
2023-03-24 David Malcolm <dmalcolm@redhat.com>
PR other/109163
* json.cc: Update comments to indicate that we now preserve
insertion order of keys within objects.
(object::print): Traverse keys in insertion order.
(object::set): Preserve insertion order of keys.
(selftest::test_writing_objects): Add an additional key to verify
that we preserve insertion order.
* json.h (object::m_keys): New field.
2023-03-24 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/109238
* gimple-range-cache.cc (ranger_cache::resolve_dom): Ignore
predecessors which this block dominates.
2023-03-24 Richard Biener <rguenther@suse.de>
PR tree-optimization/106912
* tree-profile.cc (tree_profiling): Update stmts only when
profiling or testing coverage. Make sure to update calls
fntype, stripping 'const' there.
2023-03-24 Jakub Jelinek <jakub@redhat.com>
PR middle-end/109258
* builtins.cc (inline_expand_builtin_bytecmp): Return NULL_RTX early
if target == const0_rtx.
2023-03-24 Alexandre Oliva <oliva@adacore.com>
* doc/sourcebuild.texi (weak_undefined, posix_memalign):
Document options and effective targets.
2023-03-24 Costas Argyris <costas.argyris@gmail.com>
* config/i386/x-mingw32-utf8: Make HOST_EXTRA_OBJS_SYMBOL
optional.
2023-03-23 Pat Haugen <pthaugen@linux.ibm.com>
* config/rs6000/rs6000.md (*mod<mode>3, umod<mode>3): Add
non-earlyclobber alternative.
2023-03-23 Andrew Pinski <apinski@marvell.com>
PR c/84900
* fold-const.cc (maybe_lvalue_p): Treat COMPOUND_LITERAL_EXPR
as a lvalue.
2023-03-23 Richard Biener <rguenther@suse.de>
PR tree-optimization/107569
* tree-ssa-sccvn.cc (eliminate_dom_walker::eliminate_stmt):
Do not push SSA names with zero uses as available leader.
(process_bb): Likewise.
2023-03-23 Richard Biener <rguenther@suse.de>
PR tree-optimization/109262
* tree-ssa-forwprop.cc (pass_forwprop::execute): When
combining a piecewise complex load avoid touching loads
that throw internally. Use fun, not cfun throughout.
2023-03-23 Jakub Jelinek <jakub@redhat.com>
* value-range.cc (irange::irange_union, irange::intersect): Fix
comment spelling bugs.
* gimple-range-trace.cc (range_tracer::do_header): Likewise.
* gimple-range-trace.h: Likewise.
* gimple-range-edge.cc: Likewise.
(gimple_outgoing_range_stmt_p,
gimple_outgoing_range::switch_edge_range,
gimple_outgoing_range::edge_range_p): Likewise.
* gimple-range.cc (gimple_ranger::prefill_stmt_dependencies,
gimple_ranger::fold_stmt, gimple_ranger::register_transitive_infer,
assume_query::assume_query, assume_query::calculate_phi): Likewise.
* gimple-range-edge.h: Likewise.
* value-range.h (Value_Range::set, Value_Range::lower_bound,
Value_Range::upper_bound, frange::set_undefined): Likewise.
* gimple-range-gori.h (range_def_chain::depend, gori_map::m_outgoing,
gori_compute): Likewise.
* gimple-range-fold.h (fold_using_range): Likewise.
* gimple-range-path.cc (path_range_query::compute_ranges_in_phis):
Likewise.
* gimple-range-gori.cc (range_def_chain::in_chain_p,
range_def_chain::dump, gori_map::calculate_gori,
gori_compute::compute_operand_range_switch,
gori_compute::logical_combine, gori_compute::refine_using_relation,
gori_compute::compute_operand1_range, gori_compute::may_recompute_p):
Likewise.
* gimple-range.h: Likewise.
(enable_ranger): Likewise.
* range-op.h (empty_range_varying): Likewise.
* value-query.h (value_query): Likewise.
* gimple-range-cache.cc (block_range_cache::set_bb_range,
block_range_cache::dump, ssa_global_cache::clear_global_range,
temporal_cache::temporal_value, temporal_cache::current_p,
ranger_cache::range_of_def, ranger_cache::propagate_updated_value,
ranger_cache::range_from_dom, ranger_cache::register_inferred_value):
Likewise.
* gimple-range-fold.cc (fur_edge::get_phi_operand,
fur_stmt::get_operand, gimple_range_adjustment,
fold_using_range::range_of_phi,
fold_using_range::relation_fold_and_or): Likewise.
* value-range-storage.h (irange_storage_slot::MAX_INTS): Likewise.
* value-query.cc (range_query::value_of_expr,
range_query::value_on_edge, range_query::query_relation): Likewise.
* tree-vrp.cc (remove_unreachable::remove_and_update_globals,
intersect_range_with_nonzero_bits): Likewise.
* gimple-range-infer.cc (gimple_infer_range::check_assume_func,
exit_range): Likewise.
* value-relation.h: Likewise.
(equiv_oracle, relation_trio::relation_trio, value_relation,
value_relation::value_relation, pe_min): Likewise.
* range-op-float.cc (range_operator_float::rv_fold,
frange_arithmetic, foperator_unordered_equal::op1_range,
foperator_div::rv_fold): Likewise.
* gimple-range-op.cc (cfn_clz::fold_range): Likewise.
* value-relation.cc (equiv_oracle::query_relation,
equiv_oracle::register_equiv, equiv_oracle::add_equiv_to_block,
value_relation::apply_transitive, relation_chain_head::find_relation,
dom_oracle::query_relation, dom_oracle::find_relation_block,
dom_oracle::find_relation_dom, path_oracle::register_equiv): Likewise.
* range-op.cc (range_operator::wi_fold_in_parts_equiv,
create_possibly_reversed_range, adjust_op1_for_overflow,
operator_mult::wi_fold, operator_exact_divide::op1_range,
operator_cast::lhs_op1_relation, operator_cast::fold_pair,
operator_cast::fold_range, operator_abs::wi_fold, range_op_cast_tests,
range_op_lshift_tests): Likewise.
2023-03-23 Andrew Stubbs <ams@codesourcery.com>
* config/gcn/gcn.cc (gcn_class_max_nregs): Handle vectors in SGPRs.
(move_callee_saved_registers): Detect the bug condition early.
2023-03-23 Andrew Stubbs <ams@codesourcery.com>
* config/gcn/gcn-protos.h (gcn_stepped_zero_int_parallel_p): New.
* config/gcn/gcn-valu.md (V_1REG_ALT): New.
(V_2REG_ALT): New.
(vec_extract<V_1REG:mode><V_1REG_ALT:mode>_nop): New.
(vec_extract<V_2REG:mode><V_2REG_ALT:mode>_nop): New.
(vec_extract<V_ALL:mode><V_ALL_ALT:mode>): Use new patterns.
* config/gcn/gcn.cc (gcn_stepped_zero_int_parallel_p): New.
* config/gcn/predicates.md (ascending_zero_int_parallel): New.
2023-03-23 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/109176
* tree-vect-generic.cc (expand_vector_condition): If a has
vector boolean type and is a comparison, also check if both
the comparison and VEC_COND_EXPR could be successfully expanded
individually.
2023-03-23 Pan Li <pan2.li@intel.com>
Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
PR target/108654
PR target/108185
* config/riscv/riscv-modes.def (ADJUST_BYTESIZE): Adjust size
for vector mask modes.
* config/riscv/riscv.cc (riscv_v_adjust_bytesize): New.
* config/riscv/riscv.h (riscv_v_adjust_bytesize): New.
2023-03-23 Songhe Zhu <zhusonghe@eswincomputing.com>
* config/riscv/multilib-generator: Adjusting the loop of 'alt' in 'alts'.
2023-03-23 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
PR target/109244
* config/riscv/riscv-protos.h (emit_vlmax_vsetvl): Define as global.
(emit_vlmax_op): Ditto.
* config/riscv/riscv-v.cc (get_sew): New function.
(emit_vlmax_vsetvl): Adapt function.
(emit_pred_op): Ditto.
(emit_vlmax_op): Ditto.
(emit_nonvlmax_op): Ditto.
(legitimize_move): Fix LRA ICE.
(gen_no_side_effects_vsetvl_rtx): Adapt function.
* config/riscv/vector.md (@mov<V_FRACT:mode><P:mode>_lra): New pattern.
(@mov<VB:mode><P:mode>_lra): Ditto.
(*mov<V_FRACT:mode><P:mode>_lra): Ditto.
(*mov<VB:mode><P:mode>_lra): Ditto.
2023-03-23 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
PR target/109228
* config/riscv/riscv-vector-builtins-bases.cc (class vlenb): Add
__riscv_vlenb support.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def (vlenb): Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc (struct vlenb_def): Ditto.
(SHAPE): Ditto.
* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
* config/riscv/riscv-vector-builtins.cc: Ditto.
2023-03-23 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
kito-cheng <kito.cheng@sifive.com>
* config/riscv/riscv-vsetvl.cc (reg_available_p): Fix bugs.
(pass_vsetvl::compute_local_backward_infos): Fix bugs.
(pass_vsetvl::need_vsetvl): Fix bugs.
(pass_vsetvl::backward_demand_fusion): Fix bugs.
(pass_vsetvl::demand_fusion): Fix bugs.
(eliminate_insn): Fix bugs.
(insert_vsetvl): Ditto.
(pass_vsetvl::emit_local_forward_vsetvls): Ditto.
* config/riscv/riscv-vsetvl.h (enum vsetvl_type): Ditto.
* config/riscv/vector.md: Ditto.
2023-03-23 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
kito-cheng <kito.cheng@sifive.com>
* config/riscv/riscv-vector-builtins-bases.cc: Fix ternary bug.
* config/riscv/vector-iterators.md (nmsac): Ditto.
(nmsub): Ditto.
(msac): Ditto.
(msub): Ditto.
(nmadd): Ditto.
(nmacc): Ditto.
* config/riscv/vector.md (@pred_mul_<optab><mode>): Ditto.
(@pred_mul_plus<mode>): Ditto.
(*pred_madd<mode>): Ditto.
(*pred_macc<mode>): Ditto.
(*pred_mul_plus<mode>): Ditto.
(@pred_mul_plus<mode>_scalar): Ditto.
(*pred_madd<mode>_scalar): Ditto.
(*pred_macc<mode>_scalar): Ditto.
(*pred_mul_plus<mode>_scalar): Ditto.
(*pred_madd<mode>_extended_scalar): Ditto.
(*pred_macc<mode>_extended_scalar): Ditto.
(*pred_mul_plus<mode>_extended_scalar): Ditto.
(@pred_minus_mul<mode>): Ditto.
(*pred_<madd_nmsub><mode>): Ditto.
(*pred_nmsub<mode>): Ditto.
(*pred_<macc_nmsac><mode>): Ditto.
(*pred_nmsac<mode>): Ditto.
(*pred_mul_<optab><mode>): Ditto.
(*pred_minus_mul<mode>): Ditto.
(@pred_mul_<optab><mode>_scalar): Ditto.
(@pred_minus_mul<mode>_scalar): Ditto.
(*pred_<madd_nmsub><mode>_scalar): Ditto.
(*pred_nmsub<mode>_scalar): Ditto.
(*pred_<macc_nmsac><mode>_scalar): Ditto.
(*pred_nmsac<mode>_scalar): Ditto.
(*pred_mul_<optab><mode>_scalar): Ditto.
(*pred_minus_mul<mode>_scalar): Ditto.
(*pred_<madd_nmsub><mode>_extended_scalar): Ditto.
(*pred_nmsub<mode>_extended_scalar): Ditto.
(*pred_<macc_nmsac><mode>_extended_scalar): Ditto.
(*pred_nmsac<mode>_extended_scalar): Ditto.
(*pred_mul_<optab><mode>_extended_scalar): Ditto.
(*pred_minus_mul<mode>_extended_scalar): Ditto.
(*pred_<madd_msub><mode>): Ditto.
(*pred_<macc_msac><mode>): Ditto.
(*pred_<madd_msub><mode>_scalar): Ditto.
(*pred_<macc_msac><mode>_scalar): Ditto.
(@pred_neg_mul_<optab><mode>): Ditto.
(@pred_mul_neg_<optab><mode>): Ditto.
(*pred_<nmadd_msub><mode>): Ditto.
(*pred_<nmsub_nmadd><mode>): Ditto.
(*pred_<nmacc_msac><mode>): Ditto.
(*pred_<nmsac_nmacc><mode>): Ditto.
(*pred_neg_mul_<optab><mode>): Ditto.
(*pred_mul_neg_<optab><mode>): Ditto.
(@pred_neg_mul_<optab><mode>_scalar): Ditto.
(@pred_mul_neg_<optab><mode>_scalar): Ditto.
(*pred_<nmadd_msub><mode>_scalar): Ditto.
(*pred_<nmsub_nmadd><mode>_scalar): Ditto.
(*pred_<nmacc_msac><mode>_scalar): Ditto.
(*pred_<nmsac_nmacc><mode>_scalar): Ditto.
(*pred_neg_mul_<optab><mode>_scalar): Ditto.
(*pred_mul_neg_<optab><mode>_scalar): Ditto.
(@pred_widen_neg_mul_<optab><mode>): Ditto.
(@pred_widen_mul_neg_<optab><mode>): Ditto.
(@pred_widen_neg_mul_<optab><mode>_scalar): Ditto.
(@pred_widen_mul_neg_<optab><mode>_scalar): Ditto.
2023-03-23 liuhongt <hongtao.liu@intel.com>
* builtins.cc (builtin_memset_read_str): Replace
targetm.gen_memset_scratch_rtx with gen_reg_rtx.
(builtin_memset_gen_str): Ditto.
* config/i386/i386-expand.cc
(ix86_convert_const_wide_int_to_broadcast): Replace
ix86_gen_scratch_sse_rtx with gen_reg_rtx.
(ix86_expand_vector_move): Ditto.
* config/i386/i386-protos.h (ix86_gen_scratch_sse_rtx):
Removed.
* config/i386/i386.cc (ix86_gen_scratch_sse_rtx): Removed.
(TARGET_GEN_MEMSET_SCRATCH_RTX): Removed.
* doc/tm.texi: Remove TARGET_GEN_MEMSET_SCRATCH_RTX.
* doc/tm.texi.in: Ditto.
* target.def: Ditto.
2023-03-22 Vladimir N. Makarov <vmakarov@redhat.com>
* lra.cc (lra): Do not repeat inheritance and live range splitting
when asm error is found.
2023-03-22 Andrew Jenner <andrew@codesourcery.com>
* config/gcn/gcn-protos.h (gcn_expand_dpp_swap_pairs_insn)
(gcn_expand_dpp_distribute_even_insn)
(gcn_expand_dpp_distribute_odd_insn): Declare.
* config/gcn/gcn-valu.md (@dpp_swap_pairs<mode>)
(@dpp_distribute_even<mode>, @dpp_distribute_odd<mode>)
(cmul<conj_op><mode>3, cml<addsub_as><mode>4, vec_addsub<mode>3)
(cadd<rot><mode>3, vec_fmaddsub<mode>4, vec_fmsubadd<mode>4)
(fms<mode>4<exec>, fms<mode>4_negop2<exec>, fms<mode>4)
(fms<mode>4_negop2): New patterns.
* config/gcn/gcn.cc (gcn_expand_dpp_swap_pairs_insn)
(gcn_expand_dpp_distribute_even_insn)
(gcn_expand_dpp_distribute_odd_insn): New functions.
* config/gcn/gcn.md: Add entries to unspec enum.
2023-03-22 Aldy Hernandez <aldyh@redhat.com>
PR tree-optimization/109008
* value-range.cc (frange::set): Add nan_state argument.
* value-range.h (class nan_state): New.
(frange::get_nan_state): New.
2023-03-22 Martin Liska <mliska@suse.cz>
* configure: Regenerate.
2023-03-21 Joseph Myers <joseph@codesourcery.com>
* stor-layout.cc (finalize_type_size): Copy TYPE_TYPELESS_STORAGE
to variants.
2023-03-21 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/109192
* gimple-range-gori.cc (gori_compute::compute_operand_range):
Terminate gori calculations if a relation is not relevant.
* value-relation.h (value_relation::set_relation): Allow
equality between op1 and op2 if they are the same.
2023-03-21 Richard Biener <rguenther@suse.de>
PR tree-optimization/109219
* tree-vect-loop.cc (vectorizable_reduction): Check
slp_node, not STMT_SLP_TYPE.
* tree-vect-stmts.cc (vectorizable_condition): Likewise.
* tree-vect-slp.cc (vect_slp_analyze_node_operations_1):
Remove assertion on STMT_SLP_TYPE.
2023-03-21 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/109215
* tree.h (enum special_array_member): Adjust comments for int_0
and trail_0.
* tree.cc (component_ref_sam_type): Clear zero_elts if memtype
has zero sized element type and the array has variable number of
elements or constant one or more elements.
(component_ref_size): Adjust comments, formatting fix.
2023-03-21 Arsen Arsenović <arsen@aarsen.me>
* configure.ac: Add check for the Texinfo 6.8
CONTENTS_OUTPUT_LOCATION customization variable and set it if
supported.
* configure: Regenerate.
* Makefile.in (MAKEINFO_TOC_INLINE_FLAG): New variable. Set by
configure.ac to -c CONTENTS_OUTPUT_LOCATION=inline if
CONTENTS_OUTPUT_LOCATION support is detected, empty otherwise.
($(build_htmldir)/%/index.html): Pass MAKEINFO_TOC_INLINE_FLAG.
2023-03-21 Arsen Arsenović <arsen@aarsen.me>
* doc/extend.texi: Associate use_hazard_barrier_return index
entry with its attribute.
* doc/invoke.texi: Associate -fcanon-prefix-map index entry with
its attribute
2023-03-21 Arsen Arsenović <arsen@aarsen.me>
* doc/implement-c.texi: Remove usage of @gol.
* doc/invoke.texi: Ditto.
* doc/sourcebuild.texi: Ditto.
* doc/include/gcc-common.texi: Remove @gol. In new Makeinfo and
texinfo.tex versions, the bug it was working around appears to
be gone.
2023-03-21 Arsen Arsenović <arsen@aarsen.me>
* doc/include/texinfo.tex: Update to 2023-01-17.19.
2023-03-21 Arsen Arsenović <arsen@aarsen.me>
* doc/include/gcc-common.texi: Add @defbuiltin{,x} and
@enddefbuiltin for defining built-in functions.
* doc/extend.texi: Apply @defbuiltin{,x} to many, but not all,
places where it should be used.
2023-03-21 Arsen Arsenović <arsen@aarsen.me>
* doc/extend.texi (Formatted Output Function Checking): New
subsection for grouping together printf et al.
(Exception handling) Fix missing @ sign before copyright
header, which lead to the copyright line leaking into
'(gcc)Exception handling'.
* doc/gcc.texi: Set document language to en_US.
(@copying): Wrap front cover texts in quotations, move in manual
description text.
2023-03-21 Arsen Arsenović <arsen@aarsen.me>
* doc/gcc.texi: Add the Indices appendix, to make texinfo
generate nice indices overview page.
2023-03-21 Richard Biener <rguenther@suse.de>
PR tree-optimization/109170
* gimple-range-op.cc (cfn_pass_through_arg1): New.
(gimple_range_op_handler::maybe_builtin_call): Handle
__builtin_expect via cfn_pass_through_arg1.
2023-03-20 Michael Meissner <meissner@linux.ibm.com>
PR target/109067
* config/rs6000/rs6000.cc (create_complex_muldiv): Delete.
(init_float128_ieee): Delete code to switch complex multiply and divide
for long double.
(complex_multiply_builtin_code): New helper function.
(complex_divide_builtin_code): Likewise.
(rs6000_mangle_decl_assembler_name): Add support for mangling the name
of complex 128-bit multiply and divide built-in functions.
2023-03-20 Peter Bergner <bergner@linux.ibm.com>
PR target/109178
* config/rs6000/rs6000-builtin.cc (stv_expand_builtin): Use tmode.
2023-03-19 Jonny Grant <jg@jguk.org>
* doc/extend.texi (Common Function Attributes) <nonnull>:
Correct typo.
2023-03-18 Peter Bergner <bergner@linux.ibm.com>
PR rtl-optimization/109179
* lra-constraints.cc (combine_reload_insn): Enforce TO is not a debug
insn or note. Move the tests earlier to guard lra_get_insn_recog_data.
2023-03-17 Jakub Jelinek <jakub@redhat.com>
PR target/105554
* function.h (push_struct_function): Add ABSTRACT_P argument defaulted
to false.
* function.cc (push_struct_function): Add ABSTRACT_P argument, pass it
to allocate_struct_function instead of false.
* tree-inline.cc (initialize_cfun): Don't copy DECL_ARGUMENTS
nor DECL_RESULT here. Pass true as ABSTRACT_P to
push_struct_function. Call targetm.target_option.relayout_function
after it.
(tree_function_versioning): Formatting fix.
2023-03-17 Vladimir N. Makarov <vmakarov@redhat.com>
* lra-constraints.cc: Include hooks.h.
(combine_reload_insn): New function.
(lra_constraints): Call it.
2023-03-17 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
kito-cheng <kito.cheng@sifive.com>
* config/riscv/riscv-v.cc (legitimize_move): Allow undef value
as legitimate value.
* config/riscv/riscv-vector-builtins.cc
(function_expander::use_ternop_insn): Fix bugs of ternary intrinsic.
(function_expander::use_widen_ternop_insn): Ditto.
* config/riscv/vector.md (@vundefined<mode>): New pattern.
(pred_mul_<optab><mode>_undef_merge): Remove.
(*pred_mul_<optab><mode>_undef_merge_scalar): Ditto.
(*pred_mul_<optab><mode>_undef_merge_extended_scalar): Ditto.
(pred_neg_mul_<optab><mode>_undef_merge): Ditto.
(*pred_neg_mul_<optab><mode>_undef_merge_scalar): Ditto.
2023-03-17 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
PR target/109092
* config/riscv/riscv.md: Fix subreg bug.
2023-03-17 Jakub Jelinek <jakub@redhat.com>
PR middle-end/108685
* omp-expand.cc (expand_omp_for_ordered_loops): Add L0_BB argument,
use its loop_father rather than BODY_BB's loop_father.
(expand_omp_for_generic): Adjust expand_omp_for_ordered_loops caller.
If broken_loop with ordered > collapse and at least one of those
extra loops aren't guaranteed to have at least one iteration, change
l0_bb's loop_father to entry_bb's loop_father. Set cont_bb's
loop_father to l0_bb's loop_father rather than l1_bb's.
2023-03-17 Jakub Jelinek <jakub@redhat.com>
PR plugins/108634
* gdbhooks.py (TreePrinter.to_string): Wrap
gdb.parse_and_eval('tree_code_type') in a try block, parse
and eval 'tree_code_type_tmpl<0>::tree_code_type' instead if it
raises exception. Update comments for the recent tree_code_type
changes.
2023-03-17 Sandra Loosemore <sandra@codesourcery.com>
* doc/extend.texi (BPF Built-in Functions): Fix numerous markup
issues. Add more line breaks to example so it doesn't overflow
the margins.
2023-03-17 Sandra Loosemore <sandra@codesourcery.com>
* doc/extend.texi (Common Function Attributes) <access>: Fix bad
line breaks in examples.
<malloc>: Fix bad line breaks in running text, also copy-edit
for consistency.
(Extended Asm) <Generic Operand Modifiers>: Fix @multitable width.
* doc/invoke.texi (Option Summary) <Developer Options>: Fix misplaced
@gol.
(C++ Dialect Options) <-fcontracts>: Add line break in example.
<-Wctad-maybe-unsupported>: Likewise.
<-Winvalid-constexpr>: Likewise.
(Warning Options) <-Wdangling-pointer>: Likewise.
<-Winterference-size>: Likewise.
<-Wvla-parameter>: Likewise.
(Static Analyzer Options): Fix bad line breaks in running text,
plus add some missing markup.
(Optimize Options) <openacc-privatization>: Fix more bad line
breaks in running text.
2023-03-16 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386-expand.cc (expand_vec_perm_pblendv):
Handle 8-byte modes only with TARGET_MMX_WITH_SSE.
(expand_vec_perm_2perm_pblendv): Ditto.
2023-03-16 Martin Liska <mliska@suse.cz>
PR middle-end/106133
* gcc.cc (driver_handle_option): Use x_main_input_basename
if x_dump_base_name is null.
* opts.cc (common_handle_option): Likewise.
2023-03-16 Richard Biener <rguenther@suse.de>
PR tree-optimization/109123
* gimple-ssa-warn-access.cc (pass_waccess::warn_invalid_pointer):
Do not emit -Wuse-after-free late.
(pass_waccess::check_call): Always check call pointer uses.
2023-03-16 Richard Biener <rguenther@suse.de>
PR tree-optimization/109141
* tree-dfa.h (renumber_gimple_stmt_uids_in_block): New.
* tree-dfa.cc (renumber_gimple_stmt_uids_in_block): Split
out from ...
(renumber_gimple_stmt_uids): ... here and
(renumber_gimple_stmt_uids_in_blocks): ... here.
* gimple-ssa-warn-access.cc (pass_waccess::use_after_inval_p):
Use renumber_gimple_stmt_uids_in_block to also assign UIDs
to PHIs.
(pass_waccess::check_pointer_uses): Process all PHIs.
2023-03-15 David Malcolm <dmalcolm@redhat.com>
PR analyzer/109097
* diagnostic-format-sarif.cc (class sarif_invocation): New.
(class sarif_ice_notification): New.
(sarif_builder::m_invocation_obj): New field.
(sarif_invocation::add_notification_for_ice): New.
(sarif_invocation::prepare_to_flush): New.
(sarif_ice_notification::sarif_ice_notification): New.
(sarif_builder::sarif_builder): Add m_invocation_obj.
(sarif_builder::end_diagnostic): Special-case DK_ICE and
DK_ICE_NOBT.
(sarif_builder::flush_to_file): Call prepare_to_flush on
m_invocation_obj. Pass the latter to make_top_level_object.
(sarif_builder::make_result_object): Move creation of "locations"
array to...
(sarif_builder::make_locations_arr): ...this new function.
(sarif_builder::make_top_level_object): Add "invocation_obj" param
and pass it to make_run_object.
(sarif_builder::make_run_object): Add "invocation_obj" param and
use it.
(sarif_ice_handler): New callback.
(diagnostic_output_format_init_sarif): Wire up sarif_ice_handler.
* diagnostic.cc (diagnostic_initialize): Initialize new field
"ice_handler_cb".
(diagnostic_action_after_output): If it is set, make one attempt
to call ice_handler_cb.
* diagnostic.h (diagnostic_context::ice_handler_cb): New field.
2023-03-15 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386-expand.cc (expand_vec_perm_blend):
Handle 8-byte modes only with TARGET_MMX_WITH_SSE. Handle V2SFmode
and fix V2HImode handling.
(expand_vec_perm_1): Try to emit BLEND instruction
before MOVSS/MOVSD.
* config/i386/mmx.md (*mmx_blendps): New insn pattern.
2023-03-15 Tobias Burnus <tobias@codesourcery.com>
* omp-low.cc (omp_runtime_api_call): Add omp_in_explicit_task.
2023-03-15 Richard Biener <rguenther@suse.de>
* gimple-ssa-warn-access.cc (pass_waccess::check_pointer_uses):
Do not diagnose clobbers.
2023-03-15 Richard Biener <rguenther@suse.de>
PR tree-optimization/109139
* tree-ssa-live.cc (remove_unused_locals): Look at the
base address for unused decls on the LHS of .DEFERRED_INIT.
2023-03-15 Xi Ruoyao <xry111@xry111.site>
PR other/109086
* builtins.cc (inline_string_cmp): Force the character
difference into "result" pseudo-register, instead of reassign
the pseudo-register.
2023-03-15 Christoph Müllner <christoph.muellner@vrull.eu>
* config.gcc: Add thead.o to RISC-V extra_objs.
* config/riscv/peephole.md: Add mempair peephole passes.
* config/riscv/riscv-protos.h (riscv_split_64bit_move_p): New
prototype.
(th_mempair_operands_p): Likewise.
(th_mempair_order_operands): Likewise.
(th_mempair_prepare_save_restore_operands): Likewise.
(th_mempair_save_restore_regs): Likewise.
(th_mempair_output_move): Likewise.
* config/riscv/riscv.cc (riscv_save_reg): Move code.
(riscv_restore_reg): Move code.
(riscv_for_each_saved_reg): Add code to emit mempair insns.
* config/riscv/t-riscv: Add thead.cc.
* config/riscv/thead.md (*th_mempair_load_<GPR:mode>2):
New insn.
(*th_mempair_store_<GPR:mode>2): Likewise.
(*th_mempair_load_extendsidi2): Likewise.
(*th_mempair_load_zero_extendsidi2): Likewise.
* config/riscv/thead.cc: New file.
2023-03-15 Christoph Müllner <christoph.muellner@vrull.eu>
* config/riscv/constraints.md (TARGET_XTHEADFMV ? FP_REGS : NO_REGS)
New constraint "th_f_fmv".
(TARGET_XTHEADFMV ? GR_REGS : NO_REGS): New constraint
"th_r_fmv".
* config/riscv/riscv.cc (riscv_split_doubleword_move):
Add split code for XTheadFmv.
(riscv_secondary_memory_needed): XTheadFmv does not need
secondary memory.
* config/riscv/riscv.md: Add new UNSPEC_XTHEADFMV and
UNSPEC_XTHEADFMV_HW. Add support for XTheadFmv to
movdf_hardfloat_rv32.
* config/riscv/thead.md (th_fmv_hw_w_x): New INSN.
(th_fmv_x_w): New INSN.
(th_fmv_x_hw): New INSN.
2023-03-15 Christoph Müllner <christoph.muellner@vrull.eu>
* config/riscv/riscv.md (maddhisi4): New expand.
(msubhisi4): New expand.
* config/riscv/thead.md (*th_mula<mode>): New pattern.
(*th_mulawsi): New pattern.
(*th_mulawsi2): New pattern.
(*th_maddhisi4): New pattern.
(*th_sextw_maddhisi4): New pattern.
(*th_muls<mode>): New pattern.
(*th_mulswsi): New pattern.
(*th_mulswsi2): New pattern.
(*th_msubhisi4): New pattern.
(*th_sextw_msubhisi4): New pattern.
2023-03-15 Christoph Müllner <christoph.muellner@vrull.eu>
* config/riscv/iterators.md (TARGET_64BIT): Add GPR2 iterator.
* config/riscv/riscv-protos.h (riscv_expand_conditional_move):
Add prototype.
* config/riscv/riscv.cc (riscv_rtx_costs): Add costs for
XTheadCondMov.
(riscv_expand_conditional_move): New function.
(riscv_expand_conditional_move_onesided): New function.
* config/riscv/riscv.md: Add support for XTheadCondMov.
* config/riscv/thead.md (*th_cond_mov<GPR:mode><GPR2:mode>): Add
support for XTheadCondMov.
(*th_cond_gpr_mov<GPR:mode><GPR2:mode>): Likewise.
2023-03-15 Christoph Müllner <christoph.muellner@vrull.eu>
* config/riscv/bitmanip.md (clzdi2): New expand.
(clzsi2): New expand.
(ctz<mode>2): New expand.
(popcount<mode>2): New expand.
(<bitmanip_optab>si2): Rename INSN.
(*<bitmanip_optab>si2): Hide INSN name.
(<bitmanip_optab>di2): Rename INSN.
(*<bitmanip_optab>di2): Hide INSN name.
(rotrsi3): Remove INSN.
(rotr<mode>3): Add expand.
(*rotrsi3): New INSN.
(rotrdi3): Rename INSN.
(*rotrdi3): Hide INSN name.
(rotrsi3_sext): Rename INSN.
(*rotrsi3_sext): Hide INSN name.
(bswap<mode>2): Remove INSN.
(bswapdi2): Add expand.
(bswapsi2): Add expand.
(*bswap<mode>2): Hide INSN name.
* config/riscv/riscv.cc (riscv_rtx_costs): Add costs for sign
extraction.
* config/riscv/riscv.md (extv<mode>): New expand.
(extzv<mode>): New expand.
* config/riscv/thead.md (*th_srri<mode>3): New INSN.
(*th_ext<mode>): New INSN.
(*th_extu<mode>): New INSN.
(*th_clz<mode>2): New INSN.
(*th_rev<mode>2): New INSN.
2023-03-15 Christoph Müllner <christoph.muellner@vrull.eu>
* config/riscv/riscv.cc (riscv_rtx_costs): Add xthead:tst cost.
* config/riscv/thead.md (*th_tst<mode>3): New INSN.
2023-03-15 Christoph Müllner <christoph.muellner@vrull.eu>
* config/riscv/riscv.md: Include thead.md
* config/riscv/thead.md: New file.
2023-03-15 Christoph Müllner <christoph.muellner@vrull.eu>
* config/riscv/riscv-cores.def (RISCV_CORE): Add "thead-c906".
2023-03-15 Christoph Müllner <christoph.muellner@vrull.eu>
* common/config/riscv/riscv-common.cc: Add xthead* extensions.
* config/riscv/riscv-opts.h (MASK_XTHEADBA): New.
(MASK_XTHEADBB): New.
(MASK_XTHEADBS): New.
(MASK_XTHEADCMO): New.
(MASK_XTHEADCONDMOV): New.
(MASK_XTHEADFMEMIDX): New.
(MASK_XTHEADFMV): New.
(MASK_XTHEADINT): New.
(MASK_XTHEADMAC): New.
(MASK_XTHEADMEMIDX): New.
(MASK_XTHEADMEMPAIR): New.
(MASK_XTHEADSYNC): New.
(TARGET_XTHEADBA): New.
(TARGET_XTHEADBB): New.
(TARGET_XTHEADBS): New.
(TARGET_XTHEADCMO): New.
(TARGET_XTHEADCONDMOV): New.
(TARGET_XTHEADFMEMIDX): New.
(TARGET_XTHEADFMV): New.
(TARGET_XTHEADINT): New.
(TARGET_XTHEADMAC): New.
(TARGET_XTHEADMEMIDX): New.
(TARGET_XTHEADMEMPAIR): new.
(TARGET_XTHEADSYNC): New.
* config/riscv/riscv.opt: Add riscv_xthead_subext.
2023-03-15 Hu, Lin1 <lin1.hu@intel.com>
PR target/109117
* config/i386/i386-builtin.def (__builtin_ia32_vaesdec_v16qi,
__builtin_ia32_vaesdeclast_v16qi,__builtin_ia32_vaesenc_v16qi,
__builtin_ia32_vaesenclast_v16qi): Require OPTION_MASK_ISA_AVX512VL.
2023-03-14 Jakub Jelinek <jakub@redhat.com>
PR target/109109
* config/i386/i386-expand.cc (split_double_concat): Fix splitting
when lo is equal to dhi and hi is a MEM which uses dlo register.
2023-03-14 Martin Jambor <mjambor@suse.cz>
PR ipa/107925
* ipa-cp.cc (update_profiling_info): Drop counts of orig_node to
global0 instead of zeroing when it does not have as many counts as
it should.
2023-03-14 Martin Jambor <mjambor@suse.cz>
PR ipa/107925
* ipa-cp.cc (update_specialized_profile): Drop orig_node_count to
ipa count, remove assert, lenient_count_portion_handling, dump
also orig_node_count.
2023-03-14 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386-expand.cc (expand_vec_perm_movs):
Handle V2SImode for TARGET_MMX_WITH_SSE.
* config/i386/mmx.md (*mmx_movss_<mode>): Rename from *mmx_movss
using V2FI mode iterator to handle both V2SI and V2SF modes.
2023-03-14 Sam James <sam@gentoo.org>
* config/riscv/genrvv-type-indexer.cc: Avoid calloc() poisoning on musl by
including <sstream> earlier.
* system.h: Add INCLUDE_SSTREAM.
2023-03-14 Richard Biener <rguenther@suse.de>
* tree-ssa-live.cc (remove_unused_locals): Do not treat
the .DEFERRED_INIT of a variable as use, instead remove
that if it is the only use.
2023-03-14 Eric Botcazou <ebotcazou@adacore.com>
PR rtl-optimization/107762
* expr.cc (emit_group_store): Revert latest change.
2023-03-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR tree-optimization/109005
* tree-if-conv.cc (get_bitfield_rep): Replace BLKmode check with
aggregate type check.
2023-03-14 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/109115
* tree-vect-patterns.cc (vect_recog_divmod_pattern): Don't use
r.upper_bound () on r.undefined_p () range.
2023-03-14 Jan Hubicka <hubicka@ucw.cz>
PR tree-optimization/106896
* profile-count.cc (profile_count::to_sreal_scale): Synchronize
implementatoin with probability_in; avoid some asserts.
2023-03-13 Max Filippov <jcmvbkbc@gmail.com>
* config/xtensa/linux.h (TARGET_ASM_FILE_END): New macro.
2023-03-13 Sean Bright <sean@seanbright.com>
* doc/invoke.texi (Warning Options): Remove errant 'See'
before @xref.
2023-03-13 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.h (REG_OK_STRICT, REG_OK_FOR_INDEX_P,
REG_OK_FOR_BASE_P): Remove.
2023-03-13 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/vector-iterators.md (=vd,vr): Fine tune.
(=vd,vd,vr,vr): Ditto.
* config/riscv/vector.md: Ditto.
2023-03-13 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vector-builtins.cc
(function_expander::use_compare_insn): Add operand predicate check.
2023-03-13 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/vector.md: Fine tune RA constraints.
2023-03-13 Tobias Burnus <tobias@codesourcery.com>
* config/gcn/mkoffload.cc (main): Pass -save-temps on for the
hsaco assemble/link.
2023-03-13 Richard Biener <rguenther@suse.de>
PR tree-optimization/109046
* tree-ssa-forwprop.cc (pass_forwprop::execute): Combine
piecewise complex loads.
2023-03-12 Jakub Jelinek <jakub@redhat.com>
* config/aarch64/aarch64.h (aarch64_bf16_type_node): Remove.
(aarch64_bf16_ptr_type_node): Adjust comment.
* config/aarch64/aarch64.cc (aarch64_gimplify_va_arg_expr): Use
bfloat16_type_node rather than aarch64_bf16_type_node.
(aarch64_libgcc_floating_mode_supported_p,
aarch64_scalar_mode_supported_p): Also support BFmode.
(aarch64_invalid_conversion, aarch64_invalid_unary_op): Remove.
(aarch64_invalid_binary_op): Remove BFmode related rejections.
(TARGET_INVALID_CONVERSION, TARGET_INVALID_UNARY_OP): Don't redefine.
* config/aarch64/aarch64-builtins.cc (aarch64_bf16_type_node): Remove.
(aarch64_int_or_fp_type): Use bfloat16_type_node rather than
aarch64_bf16_type_node.
(aarch64_init_simd_builtin_types): Likewise.
(aarch64_init_bf16_types): Likewise. Don't create bfloat16_type_node,
which is created in tree.cc already.
* config/aarch64/aarch64-sve-builtins.def (svbfloat16_t): Likewise.
2023-03-12 Roger Sayle <roger@nextmovesoftware.com>
PR middle-end/109031
* tree-chrec.cc (chrec_apply): When folding "{a, +, a} (x-1)",
ensure that the type of x is as wide or wider than the type of a.
2023-03-12 Tamar Christina <tamar.christina@arm.com>
PR target/108583
* config/aarch64/aarch64-simd.md (@aarch64_bitmask_udiv<mode>3): Remove.
(*bitmask_shift_plus<mode>): New.
* config/aarch64/aarch64-sve2.md (*bitmask_shift_plus<mode>): New.
(@aarch64_bitmask_udiv<mode>3): Remove.
* config/aarch64/aarch64.cc
(aarch64_vectorize_can_special_div_by_constant,
TARGET_VECTORIZE_CAN_SPECIAL_DIV_BY_CONST): Removed.
(TARGET_VECTORIZE_PREFERRED_DIV_AS_SHIFTS_OVER_MULT,
aarch64_vectorize_preferred_div_as_shifts_over_mult): New.
2023-03-12 Tamar Christina <tamar.christina@arm.com>
PR target/108583
* target.def (preferred_div_as_shifts_over_mult): New.
* doc/tm.texi.in: Document it.
* doc/tm.texi: Regenerate.
* targhooks.cc (default_preferred_div_as_shifts_over_mult): New.
* targhooks.h (default_preferred_div_as_shifts_over_mult): New.
* tree-vect-patterns.cc (vect_recog_divmod_pattern): Use it.
2023-03-12 Tamar Christina <tamar.christina@arm.com>
Richard Sandiford <richard.sandiford@arm.com>
PR target/108583
* tree-ssa-math-opts.cc (convert_mult_to_fma): Inhibit FMA in case not
single use.
2023-03-12 Tamar Christina <tamar.christina@arm.com>
Andrew MacLeod <amacleod@redhat.com>
PR target/108583
* gimple-range-op.h (gimple_range_op_handler): Add maybe_non_standard.
* gimple-range-op.cc (gimple_range_op_handler::gimple_range_op_handler):
Use it.
(gimple_range_op_handler::maybe_non_standard): New.
* range-op.cc (class operator_widen_plus_signed,
operator_widen_plus_signed::wi_fold, class operator_widen_plus_unsigned,
operator_widen_plus_unsigned::wi_fold, class operator_widen_mult_signed,
operator_widen_mult_signed::wi_fold, class operator_widen_mult_unsigned,
operator_widen_mult_unsigned::wi_fold,
ptr_op_widen_mult_signed, ptr_op_widen_mult_unsigned,
ptr_op_widen_plus_signed, ptr_op_widen_plus_unsigned): New.
* range-op.h (ptr_op_widen_mult_signed, ptr_op_widen_mult_unsigned,
ptr_op_widen_plus_signed, ptr_op_widen_plus_unsigned): New
2023-03-12 Tamar Christina <tamar.christina@arm.com>
PR target/108583
* doc/tm.texi (TARGET_VECTORIZE_CAN_SPECIAL_DIV_BY_CONST): Remove.
* doc/tm.texi.in: Likewise.
* explow.cc (round_push, align_dynamic_address): Revert previous patch.
* expmed.cc (expand_divmod): Likewise.
* expmed.h (expand_divmod): Likewise.
* expr.cc (force_operand, expand_expr_divmod): Likewise.
* optabs.cc (expand_doubleword_mod, expand_doubleword_divmod): Likewise.
* target.def (can_special_div_by_const): Remove.
* target.h: Remove tree-core.h include
* targhooks.cc (default_can_special_div_by_const): Remove.
* targhooks.h (default_can_special_div_by_const): Remove.
* tree-vect-generic.cc (expand_vector_operation): Remove hook.
* tree-vect-patterns.cc (vect_recog_divmod_pattern): Remove hook.
* tree-vect-stmts.cc (vectorizable_operation): Remove hook.
2023-03-12 Sandra Loosemore <sandra@codesourcery.com>
* doc/install.texi2html: Fix issue number typo in comment.
2023-03-12 Gaius Mulley <gaiusmod2@gmail.com>
* doc/gm2.texi (Elementary data types): Equivalence BOOLEAN with
bool.
2023-03-12 Sandra Loosemore <sandra@codesourcery.com>
* doc/invoke.texi (Optimize Options): Add markup to
description of asan-kernel-mem-intrinsic-prefix, and clarify
wording slightly.
2023-03-11 Gerald Pfeifer <gerald@pfeifer.com>
* doc/extend.texi (Named Address Spaces): Drop a redundant link
to AVR-LibC.
2023-03-11 Jeff Law <jlaw@ventanamicro>
PR web/88860
* doc/extend.texi: Clarify Attribute Syntax a bit.
2023-03-11 Sandra Loosemore <sandra@codesourcery.com>
* doc/install.texi (Prerequisites): Suggest using newer versions
of Texinfo.
(Final install): Clean up and modernize discussion of how to
build or obtain the GCC manuals.
* doc/install.texi2html: Update comment to point to the PR instead
of "makeinfo 4.7 brokenness" (it's not specific to that version).
2023-03-10 Jakub Jelinek <jakub@redhat.com>
PR target/107703
* optabs.cc (expand_fix): For conversions from BFmode to integral,
use shifts to convert it to SFmode first and then convert SFmode
to integral.
2023-03-10 Andrew Pinski <apinski@marvell.com>
* config/aarch64/aarch64.md: Add a new define_split
to help combine.
2023-03-10 Richard Biener <rguenther@suse.de>
* tree-ssa-structalias.cc (solve_graph): Immediately
iterate self-cycles.
2023-03-10 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/109008
* range-op-float.cc (float_widen_lhs_range): If not
-frounding-math and not IBM double double format, extend lhs
range just by 0.5ulp rather than 1ulp in each direction.
2023-03-10 Jakub Jelinek <jakub@redhat.com>
PR target/107998
* config.gcc (x86_64-*-cygwin*): Don't add i386/t-cygwin-w64 into
$tmake_file.
* config/i386/t-cygwin-w64: Remove.
2023-03-10 Jakub Jelinek <jakub@redhat.com>
PR plugins/108634
* tree-core.h (tree_code_type, tree_code_length): For C++11 or
C++14, don't declare as extern const arrays.
(tree_code_type_tmpl, tree_code_length_tmpl): New types with
static constexpr member arrays for C++11 or C++14.
* tree.h (TREE_CODE_CLASS): For C++11 or C++14 use
tree_code_type_tmpl <0>::tree_code_type instead of tree_code_type.
(TREE_CODE_LENGTH): For C++11 or C++14 use
tree_code_length_tmpl <0>::tree_code_length instead of
tree_code_length.
* tree.cc (tree_code_type, tree_code_length): Remove.
2023-03-10 Jakub Jelinek <jakub@redhat.com>
PR other/108464
* common.opt (fcanon-prefix-map): New option.
* opts.cc: Include file-prefix-map.h.
(flag_canon_prefix_map): New variable.
(common_handle_option): Handle OPT_fcanon_prefix_map.
(gen_command_line_string): Ignore OPT_fcanon_prefix_map.
* file-prefix-map.h (flag_canon_prefix_map): Declare.
* file-prefix-map.cc (struct file_prefix_map): Add canonicalize
member.
(add_prefix_map): Initialize canonicalize member from
flag_canon_prefix_map, and if true canonicalize it using lrealpath.
(remap_filename): Revert 2022-11-01 and 2022-11-07 changes,
use lrealpath result only for map->canonicalize map entries.
* lto-opts.cc (lto_write_options): Ignore OPT_fcanon_prefix_map.
* opts-global.cc (handle_common_deferred_options): Clear
flag_canon_prefix_map at the start and handle OPT_fcanon_prefix_map.
* doc/invoke.texi (-fcanon-prefix-map): Document.
(-ffile-prefix-map, -fdebug-prefix-map, -fprofile-prefix-map): Add
see also for -fcanon-prefix-map.
* doc/cppopts.texi (-fmacro-prefix-map): Likewise.
2023-03-10 Jakub Jelinek <jakub@redhat.com>
PR c/108079
* cgraphunit.cc (check_global_declaration): Don't warn for unused
variables which have OPT_Wunused_variable warning suppressed.
2023-03-10 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/109008
* range-op-float.cc (float_widen_lhs_range): If lb is
minimum representable finite number or ub is maximum
representable finite number, instead of widening it to
-inf or inf widen it to negative or positive 0x0.8p+(EMAX+1).
Temporarily clear flag_finite_math_only when canonicalizing
the widened range.
2023-03-10 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-builtins.cc (riscv_gimple_fold_builtin): New function.
* config/riscv/riscv-protos.h (riscv_gimple_fold_builtin): Ditto.
(gimple_fold_builtin): Ditto.
* config/riscv/riscv-vector-builtins-bases.cc (class read_vl): New class.
(class vleff): Ditto.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def (read_vl): Ditto.
(vleff): Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc (struct read_vl_def): Ditto.
(struct fault_load_def): Ditto.
(SHAPE): Ditto.
* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
* config/riscv/riscv-vector-builtins.cc
(rvv_arg_type_info::get_tree_type): Add size_ptr.
(gimple_folder::gimple_folder): New class.
(gimple_folder::fold): Ditto.
(gimple_fold_builtin): New function.
(get_read_vl_instance): Ditto.
(get_read_vl_decl): Ditto.
* config/riscv/riscv-vector-builtins.def (size_ptr): Add size_ptr.
* config/riscv/riscv-vector-builtins.h (class gimple_folder): New class.
(get_read_vl_instance): New function.
(get_read_vl_decl): Ditto.
* config/riscv/riscv-vsetvl.cc (fault_first_load_p): Ditto.
(read_vl_insn_p): Ditto.
(available_occurrence_p): Ditto.
(backward_propagate_worthwhile_p): Ditto.
(gen_vsetvl_pat): Adapt for vleff support.
(get_forward_read_vl_insn): New function.
(get_backward_fault_first_load_insn): Ditto.
(source_equal_p): Adapt for vleff support.
(first_ratio_invalid_for_second_sew_p): Remove.
(first_ratio_invalid_for_second_lmul_p): Ditto.
(first_lmul_less_than_second_lmul_p): Ditto.
(first_ratio_less_than_second_ratio_p): Ditto.
(support_relaxed_compatible_p): New function.
(vector_insn_info::operator>): Remove.
(vector_insn_info::operator>=): Refine.
(vector_insn_info::parse_insn): Adapt for vleff support.
(vector_insn_info::compatible_p): Ditto.
(vector_insn_info::update_fault_first_load_avl): New function.
(pass_vsetvl::transfer_after): Adapt for vleff support.
(pass_vsetvl::demand_fusion): Ditto.
(pass_vsetvl::cleanup_insns): Ditto.
* config/riscv/riscv-vsetvl.def (DEF_INCOMPATIBLE_COND): Remove
redundant condtions.
* config/riscv/riscv-vsetvl.h (struct demands_cond): New function.
* config/riscv/riscv.cc (TARGET_GIMPLE_FOLD_BUILTIN): New target hook.
* config/riscv/riscv.md: Adapt for vleff support.
* config/riscv/t-riscv: Ditto.
* config/riscv/vector-iterators.md: New iterator.
* config/riscv/vector.md (read_vlsi): New pattern.
(read_vldi_zero_extend): Ditto.
(@pred_fault_load<mode>): Ditto.
2023-03-10 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vector-builtins.cc
(function_expander::use_ternop_insn): Use maybe_gen_insn instead.
(function_expander::use_widen_ternop_insn): Ditto.
* optabs.cc (maybe_gen_insn): Extend nops handling.
2023-03-10 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vector-builtins-bases.cc: Split indexed load
patterns according to RVV ISA.
* config/riscv/vector-iterators.md: New iterators.
* config/riscv/vector.md
(@pred_indexed_<order>load<VNX1_QHSD:mode><VNX1_QHSDI:mode>): Remove.
(@pred_indexed_<order>load<mode>_same_eew): New pattern.
(@pred_indexed_<order>load<mode>_x2_greater_eew): Ditto.
(@pred_indexed_<order>load<mode>_x4_greater_eew): Ditto.
(@pred_indexed_<order>load<mode>_x8_greater_eew): Ditto.
(@pred_indexed_<order>load<mode>_x2_smaller_eew): Ditto.
(@pred_indexed_<order>load<mode>_x4_smaller_eew): Ditto.
(@pred_indexed_<order>load<mode>_x8_smaller_eew): Ditto.
(@pred_indexed_<order>load<VNX2_QHSD:mode><VNX2_QHSDI:mode>): Remove.
(@pred_indexed_<order>load<VNX4_QHSD:mode><VNX4_QHSDI:mode>): Ditto.
(@pred_indexed_<order>load<VNX8_QHSD:mode><VNX8_QHSDI:mode>): Ditto.
(@pred_indexed_<order>load<VNX16_QHS:mode><VNX16_QHSI:mode>): Ditto.
(@pred_indexed_<order>load<VNX32_QH:mode><VNX32_QHI:mode>): Ditto.
(@pred_indexed_<order>load<VNX64_Q:mode><VNX64_Q:mode>): Ditto.
2023-03-10 Michael Collison <collison@rivosinc.com>
* tree-vect-loop-manip.cc (vect_do_peeling): Use
result of constant_lower_bound instead of vf for the lower
bound of the epilog loop trip count.
2023-03-09 Tamar Christina <tamar.christina@arm.com>
* passes.cc (emergency_dump_function): Finish graph generation.
2023-03-09 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64.md (tbranch_<code><mode>3): Restrict to SHORT
and bottom bit only.
2023-03-09 Andrew Pinski <apinski@marvell.com>
PR tree-optimization/108980
* gimple-array-bounds.cc (array_bounds_checker::check_array_ref):
Reorgnize the call to warning for not strict flexible arrays
to be before the check of warned.
2023-03-09 Jason Merrill <jason@redhat.com>
* doc/extend.texi: Comment out __is_deducible docs.
2023-03-09 Jason Merrill <jason@redhat.com>
PR c++/105841
* doc/extend.texi (Type Traits):: Document __is_deducible.
2023-03-09 Costas Argyris <costas.argyris@gmail.com>
PR driver/108865
* config.host: add object for x86_64-*-mingw*.
* config/i386/sym-mingw32.cc: dummy file to attach
symbol.
* config/i386/utf8-mingw32.rc: windres resource file.
* config/i386/winnt-utf8.manifest: XML manifest to
enable UTF-8.
* config/i386/x-mingw32: reference to x-mingw32-utf8.
* config/i386/x-mingw32-utf8: Makefile fragment to
embed UTF-8 manifest.
2023-03-09 Vladimir N. Makarov <vmakarov@redhat.com>
* lra-constraints.cc (process_alt_operands): Use operand modes for
clobbered regs instead of the biggest access mode.
2023-03-09 Richard Biener <rguenther@suse.de>
PR middle-end/108995
* fold-const.cc (extract_muldiv_1): Avoid folding
(CST * b) / CST2 when sanitizing overflow and we rely on
overflow being undefined.
2023-03-09 Jakub Jelinek <jakub@redhat.com>
Richard Biener <rguenther@suse.de>
PR tree-optimization/109008
* range-op-float.cc (float_widen_lhs_range): New function.
(foperator_plus::op1_range, foperator_minus::op1_range,
foperator_minus::op2_range, foperator_mult::op1_range,
foperator_div::op1_range, foperator_div::op2_range): Use it.
2023-03-07 Jonathan Grant <jg@jguk.org>
PR sanitizer/81649
* doc/invoke.texi (Instrumentation Options): Clarify
LeakSanitizer behavior.
2023-03-07 Benson Muite <benson_muite@emailplus.org>
* doc/install.texi (Prerequisites): Add link to gmplib.org.
2023-03-07 Pan Li <pan2.li@intel.com>
Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
PR target/108185
PR target/108654
* config/riscv/riscv-modes.def (ADJUST_PRECISION): Adjust VNx*BI
modes.
* config/riscv/riscv.cc (riscv_v_adjust_precision): New.
* config/riscv/riscv.h (riscv_v_adjust_precision): New.
* genmodes.cc (adj_precision): New.
(ADJUST_PRECISION): New.
(emit_mode_adjustments): Handle ADJUST_PRECISION.
2023-03-07 Hans-Peter Nilsson <hp@axis.com>
* doc/sourcebuild.texi: Document check_effective_target_tail_call.
2023-03-06 Paul-Antoine Arras <pa@codesourcery.com>
* config/gcn/gcn-valu.md (<expander><mode>3_exec): Add patterns for
{s|u}{max|min} in QI, HI and DI modes.
(<expander><mode>3): Add pattern for {s|u}{max|min} in DI mode.
(cond_<fexpander><mode>): Add pattern for cond_f{max|min}.
(cond_<expander><mode>): Add pattern for cond_{s|u}{max|min}.
* config/gcn/gcn.cc (gcn_spill_class): Allow the exec register to be
saved in SGPRs.
2023-03-06 Richard Biener <rguenther@suse.de>
PR tree-optimization/109025
* tree-vect-loop.cc (vect_is_simple_reduction): Verify
the inner LC PHI use is the inner loop PHI latch definition
before classifying an outer PHI as double reduction.
2023-03-06 Jan Hubicka <hubicka@ucw.cz>
PR target/108429
* config/i386/x86-tune.def (X86_TUNE_USE_SCATTER_2PARTS): Enable for
generic.
(X86_TUNE_USE_SCATTER_4PARTS): Likewise.
(X86_TUNE_USE_SCATTER): Likewise.
2023-03-06 Xi Ruoyao <xry111@xry111.site>
PR target/109000
* config/loongarch/loongarch.h (FP_RETURN): Use
TARGET_*_FLOAT_ABI instead of TARGET_*_FLOAT.
(UNITS_PER_FP_ARG): Likewise.
2023-03-05 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vsetvl.cc (reg_available_p): Fix bug.
(pass_vsetvl::backward_demand_fusion): Ditto.
2023-03-05 Liao Shihua <shihua@iscas.ac.cn>
SiYu Wu <siyu@isrc.iscas.ac.cn>
* config/riscv/crypto.md (riscv_sm3p0_<mode>): Add ZKSED's and ZKSH's
instructions.
(riscv_sm3p1_<mode>): New.
(riscv_sm4ed_<mode>): New.
(riscv_sm4ks_<mode>): New.
* config/riscv/riscv-builtins.cc (AVAIL): Add ZKSED's and ZKSH's AVAIL.
* config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): Add ZKSED's and
ZKSH's built-in functions.
2023-03-05 Liao Shihua <shihua@iscas.ac.cn>
SiYu Wu <siyu@isrc.iscas.ac.cn>
* config/riscv/crypto.md (riscv_sha256sig0_<mode>): Add ZKNH's instructions.
(riscv_sha256sig1_<mode>): New.
(riscv_sha256sum0_<mode>): New.
(riscv_sha256sum1_<mode>): New.
(riscv_sha512sig0h): New.
(riscv_sha512sig0l): New.
(riscv_sha512sig1h): New.
(riscv_sha512sig1l): New.
(riscv_sha512sum0r): New.
(riscv_sha512sum1r): New.
(riscv_sha512sig0): New.
(riscv_sha512sig1): New.
(riscv_sha512sum0): New.
(riscv_sha512sum1): New.
* config/riscv/riscv-builtins.cc (AVAIL): And ZKNH's AVAIL.
* config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): And ZKNH's
built-in functions.
(DIRECT_BUILTIN): Add new.
2023-03-05 Liao Shihua <shihua@iscas.ac.cn>
SiYu Wu <siyu@isrc.iscas.ac.cn>
* config/riscv/constraints.md (D03): Add constants of bs and rnum.
(DsA): New.
* config/riscv/crypto.md (riscv_aes32dsi): Add ZKND's and ZKNE's instructions.
(riscv_aes32dsmi): New.
(riscv_aes64ds): New.
(riscv_aes64dsm): New.
(riscv_aes64im): New.
(riscv_aes64ks1i): New.
(riscv_aes64ks2): New.
(riscv_aes32esi): New.
(riscv_aes32esmi): New.
(riscv_aes64es): New.
(riscv_aes64esm): New.
* config/riscv/riscv-builtins.cc (AVAIL): Add ZKND's and ZKNE's AVAIL.
* config/riscv/riscv-scalar-crypto.def (DIRECT_BUILTIN): Add ZKND's and
ZKNE's built-in functions.
2023-03-05 Liao Shihua <shihua@iscas.ac.cn>
SiYu Wu <siyu@isrc.iscas.ac.cn>
* config/riscv/bitmanip.md: Add ZBKB's instructions.
* config/riscv/riscv-builtins.cc (AVAIL): Add new.
* config/riscv/riscv.md: Add new type for crypto instructions.
* config/riscv/crypto.md: Add Scalar Cryptography extension's machine
description file.
* config/riscv/riscv-scalar-crypto.def: Add Scalar Cryptography
extension's built-in function file.
2023-03-05 Liao Shihua <shihua@iscas.ac.cn>
SiYu Wu <siyu@isrc.iscas.ac.cn>
* config/riscv/riscv-builtins.cc (RISCV_FTYPE_NAME2): New.
(RISCV_FTYPE_NAME3): New.
(RISCV_ATYPE_QI): New.
(RISCV_ATYPE_HI): New.
(RISCV_FTYPE_ATYPES2): New.
(RISCV_FTYPE_ATYPES3): New.
* config/riscv/riscv-ftypes.def (2): New.
(3): New.
2023-03-05 Vineet Gupta <vineetg@rivosinc.com>
* config/riscv/riscv.cc (riscv_rtx_costs): Fixed IN_RANGE() to
use exact_log2().
2023-03-05 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
kito-cheng <kito.cheng@sifive.com>
* config/riscv/predicates.md (vector_any_register_operand): New predicate.
* config/riscv/riscv-c.cc (riscv_check_builtin_call): New function.
(riscv_register_pragmas): Add builtin function check call.
* config/riscv/riscv-protos.h (RVV_VUNDEF): Adapt macro.
(check_builtin_call): New function.
* config/riscv/riscv-vector-builtins-bases.cc (class vundefined): New class.
(class vreinterpret): Ditto.
(class vlmul_ext): Ditto.
(class vlmul_trunc): Ditto.
(class vset): Ditto.
(class vget): Ditto.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def (vluxei8): Change name.
(vluxei16): Ditto.
(vluxei32): Ditto.
(vluxei64): Ditto.
(vloxei8): Ditto.
(vloxei16): Ditto.
(vloxei32): Ditto.
(vloxei64): Ditto.
(vsuxei8): Ditto.
(vsuxei16): Ditto.
(vsuxei32): Ditto.
(vsuxei64): Ditto.
(vsoxei8): Ditto.
(vsoxei16): Ditto.
(vsoxei32): Ditto.
(vsoxei64): Ditto.
(vundefined): Add new intrinsic.
(vreinterpret): Ditto.
(vlmul_ext): Ditto.
(vlmul_trunc): Ditto.
(vset): Ditto.
(vget): Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc (struct return_mask_def): New class.
(struct narrow_alu_def): Ditto.
(struct reduc_alu_def): Ditto.
(struct vundefined_def): Ditto.
(struct misc_def): Ditto.
(struct vset_def): Ditto.
(struct vget_def): Ditto.
(SHAPE): Ditto.
* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_EEW8_INTERPRET_OPS): New def.
(DEF_RVV_EEW16_INTERPRET_OPS): Ditto.
(DEF_RVV_EEW32_INTERPRET_OPS): Ditto.
(DEF_RVV_EEW64_INTERPRET_OPS): Ditto.
(DEF_RVV_X2_VLMUL_EXT_OPS): Ditto.
(DEF_RVV_X4_VLMUL_EXT_OPS): Ditto.
(DEF_RVV_X8_VLMUL_EXT_OPS): Ditto.
(DEF_RVV_X16_VLMUL_EXT_OPS): Ditto.
(DEF_RVV_X32_VLMUL_EXT_OPS): Ditto.
(DEF_RVV_X64_VLMUL_EXT_OPS): Ditto.
(DEF_RVV_LMUL1_OPS): Ditto.
(DEF_RVV_LMUL2_OPS): Ditto.
(DEF_RVV_LMUL4_OPS): Ditto.
(vint16mf4_t): Ditto.
(vint16mf2_t): Ditto.
(vint16m1_t): Ditto.
(vint16m2_t): Ditto.
(vint16m4_t): Ditto.
(vint16m8_t): Ditto.
(vint32mf2_t): Ditto.
(vint32m1_t): Ditto.
(vint32m2_t): Ditto.
(vint32m4_t): Ditto.
(vint32m8_t): Ditto.
(vint64m1_t): Ditto.
(vint64m2_t): Ditto.
(vint64m4_t): Ditto.
(vint64m8_t): Ditto.
(vuint16mf4_t): Ditto.
(vuint16mf2_t): Ditto.
(vuint16m1_t): Ditto.
(vuint16m2_t): Ditto.
(vuint16m4_t): Ditto.
(vuint16m8_t): Ditto.
(vuint32mf2_t): Ditto.
(vuint32m1_t): Ditto.
(vuint32m2_t): Ditto.
(vuint32m4_t): Ditto.
(vuint32m8_t): Ditto.
(vuint64m1_t): Ditto.
(vuint64m2_t): Ditto.
(vuint64m4_t): Ditto.
(vuint64m8_t): Ditto.
(vint8mf4_t): Ditto.
(vint8mf2_t): Ditto.
(vint8m1_t): Ditto.
(vint8m2_t): Ditto.
(vint8m4_t): Ditto.
(vint8m8_t): Ditto.
(vuint8mf4_t): Ditto.
(vuint8mf2_t): Ditto.
(vuint8m1_t): Ditto.
(vuint8m2_t): Ditto.
(vuint8m4_t): Ditto.
(vuint8m8_t): Ditto.
(vint8mf8_t): Ditto.
(vuint8mf8_t): Ditto.
(vfloat32mf2_t): Ditto.
(vfloat32m1_t): Ditto.
(vfloat32m2_t): Ditto.
(vfloat32m4_t): Ditto.
(vfloat64m1_t): Ditto.
(vfloat64m2_t): Ditto.
(vfloat64m4_t): Ditto.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_TYPE): Ditto.
(DEF_RVV_EEW8_INTERPRET_OPS): Ditto.
(DEF_RVV_EEW16_INTERPRET_OPS): Ditto.
(DEF_RVV_EEW32_INTERPRET_OPS): Ditto.
(DEF_RVV_EEW64_INTERPRET_OPS): Ditto.
(DEF_RVV_X2_VLMUL_EXT_OPS): Ditto.
(DEF_RVV_X4_VLMUL_EXT_OPS): Ditto.
(DEF_RVV_X8_VLMUL_EXT_OPS): Ditto.
(DEF_RVV_X16_VLMUL_EXT_OPS): Ditto.
(DEF_RVV_X32_VLMUL_EXT_OPS): Ditto.
(DEF_RVV_X64_VLMUL_EXT_OPS): Ditto.
(DEF_RVV_LMUL1_OPS): Ditto.
(DEF_RVV_LMUL2_OPS): Ditto.
(DEF_RVV_LMUL4_OPS): Ditto.
(DEF_RVV_TYPE_INDEX): Ditto.
(required_extensions_p): Adapt for new intrinsic support/
(get_required_extensions): New function.
(check_required_extensions): Ditto.
(unsigned_base_type_p): Remove.
(rvv_arg_type_info::get_scalar_ptr_type): New function.
(get_mode_for_bitsize): Remove.
(rvv_arg_type_info::get_scalar_const_ptr_type): New function.
(rvv_arg_type_info::get_base_vector_type): Ditto.
(rvv_arg_type_info::get_function_type_index): Ditto.
(DEF_RVV_BASE_TYPE): New def.
(function_builder::apply_predication): New class.
(function_expander::mask_mode): Ditto.
(function_checker::function_checker): Ditto.
(function_checker::report_non_ice): Ditto.
(function_checker::report_out_of_range): Ditto.
(function_checker::require_immediate): Ditto.
(function_checker::require_immediate_range): Ditto.
(function_checker::check): Ditto.
(check_builtin_call): Ditto.
* config/riscv/riscv-vector-builtins.def (DEF_RVV_TYPE): New def.
(DEF_RVV_BASE_TYPE): Ditto.
(DEF_RVV_TYPE_INDEX): Ditto.
(vbool64_t): Ditto.
(vbool32_t): Ditto.
(vbool16_t): Ditto.
(vbool8_t): Ditto.
(vbool4_t): Ditto.
(vbool2_t): Ditto.
(vbool1_t): Ditto.
(vuint8mf8_t): Ditto.
(vuint8mf4_t): Ditto.
(vuint8mf2_t): Ditto.
(vuint8m1_t): Ditto.
(vuint8m2_t): Ditto.
(vint8m4_t): Ditto.
(vuint8m4_t): Ditto.
(vint8m8_t): Ditto.
(vuint8m8_t): Ditto.
(vint16mf4_t): Ditto.
(vuint16mf2_t): Ditto.
(vuint16m1_t): Ditto.
(vuint16m2_t): Ditto.
(vuint16m4_t): Ditto.
(vuint16m8_t): Ditto.
(vint32mf2_t): Ditto.
(vuint32m1_t): Ditto.
(vuint32m2_t): Ditto.
(vuint32m4_t): Ditto.
(vuint32m8_t): Ditto.
(vuint64m1_t): Ditto.
(vuint64m2_t): Ditto.
(vuint64m4_t): Ditto.
(vuint64m8_t): Ditto.
(vfloat32mf2_t): Ditto.
(vfloat32m1_t): Ditto.
(vfloat32m2_t): Ditto.
(vfloat32m4_t): Ditto.
(vfloat32m8_t): Ditto.
(vfloat64m1_t): Ditto.
(vfloat64m4_t): Ditto.
(vector): Move it def.
(scalar): Ditto.
(mask): Ditto.
(signed_vector): Ditto.
(unsigned_vector): Ditto.
(unsigned_scalar): Ditto.
(vector_ptr): Ditto.
(scalar_ptr): Ditto.
(scalar_const_ptr): Ditto.
(void): Ditto.
(size): Ditto.
(ptrdiff): Ditto.
(unsigned_long): Ditto.
(long): Ditto.
(eew8_index): Ditto.
(eew16_index): Ditto.
(eew32_index): Ditto.
(eew64_index): Ditto.
(shift_vector): Ditto.
(double_trunc_vector): Ditto.
(quad_trunc_vector): Ditto.
(oct_trunc_vector): Ditto.
(double_trunc_scalar): Ditto.
(double_trunc_signed_vector): Ditto.
(double_trunc_unsigned_vector): Ditto.
(double_trunc_unsigned_scalar): Ditto.
(double_trunc_float_vector): Ditto.
(float_vector): Ditto.
(lmul1_vector): Ditto.
(widen_lmul1_vector): Ditto.
(eew8_interpret): Ditto.
(eew16_interpret): Ditto.
(eew32_interpret): Ditto.
(eew64_interpret): Ditto.
(vlmul_ext_x2): Ditto.
(vlmul_ext_x4): Ditto.
(vlmul_ext_x8): Ditto.
(vlmul_ext_x16): Ditto.
(vlmul_ext_x32): Ditto.
(vlmul_ext_x64): Ditto.
* config/riscv/riscv-vector-builtins.h (DEF_RVV_BASE_TYPE): New def.
(struct function_type_info): New function.
(struct rvv_arg_type_info): Ditto.
(class function_checker): New class.
(rvv_arg_type_info::get_scalar_type): New function.
(rvv_arg_type_info::get_vector_type): Ditto.
(function_expander::ret_mode): New function.
(function_checker::arg_mode): Ditto.
(function_checker::ret_mode): Ditto.
* config/riscv/t-riscv: Add generator.
* config/riscv/vector-iterators.md: New iterators.
* config/riscv/vector.md (vundefined<mode>): New pattern.
(@vundefined<mode>): Ditto.
(@vreinterpret<mode>): Ditto.
(@vlmul_extx2<mode>): Ditto.
(@vlmul_extx4<mode>): Ditto.
(@vlmul_extx8<mode>): Ditto.
(@vlmul_extx16<mode>): Ditto.
(@vlmul_extx32<mode>): Ditto.
(@vlmul_extx64<mode>): Ditto.
(*vlmul_extx2<mode>): Ditto.
(*vlmul_extx4<mode>): Ditto.
(*vlmul_extx8<mode>): Ditto.
(*vlmul_extx16<mode>): Ditto.
(*vlmul_extx32<mode>): Ditto.
(*vlmul_extx64<mode>): Ditto.
* config/riscv/genrvv-type-indexer.cc: New file.
2023-03-05 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-protos.h (enum vlen_enum): New enum.
(slide1_sew64_helper): New function.
* config/riscv/riscv-v.cc (compute_vlmax): Ditto.
(get_unknown_min_value): Ditto.
(force_vector_length_operand): Ditto.
(gen_no_side_effects_vsetvl_rtx): Ditto.
(get_vl_x2_rtx): Ditto.
(slide1_sew64_helper): Ditto.
* config/riscv/riscv-vector-builtins-bases.cc (class slideop): New class.
(class vrgather): Ditto.
(class vrgatherei16): Ditto.
(class vcompress): Ditto.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def (vslideup): Ditto.
(vslidedown): Ditto.
(vslide1up): Ditto.
(vslide1down): Ditto.
(vfslide1up): Ditto.
(vfslide1down): Ditto.
(vrgather): Ditto.
(vrgatherei16): Ditto.
(vcompress): Ditto.
* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_EI16_OPS): New macro.
(vint8mf8_t): Ditto.
(vint8mf4_t): Ditto.
(vint8mf2_t): Ditto.
(vint8m1_t): Ditto.
(vint8m2_t): Ditto.
(vint8m4_t): Ditto.
(vint16mf4_t): Ditto.
(vint16mf2_t): Ditto.
(vint16m1_t): Ditto.
(vint16m2_t): Ditto.
(vint16m4_t): Ditto.
(vint16m8_t): Ditto.
(vint32mf2_t): Ditto.
(vint32m1_t): Ditto.
(vint32m2_t): Ditto.
(vint32m4_t): Ditto.
(vint32m8_t): Ditto.
(vint64m1_t): Ditto.
(vint64m2_t): Ditto.
(vint64m4_t): Ditto.
(vint64m8_t): Ditto.
(vuint8mf8_t): Ditto.
(vuint8mf4_t): Ditto.
(vuint8mf2_t): Ditto.
(vuint8m1_t): Ditto.
(vuint8m2_t): Ditto.
(vuint8m4_t): Ditto.
(vuint16mf4_t): Ditto.
(vuint16mf2_t): Ditto.
(vuint16m1_t): Ditto.
(vuint16m2_t): Ditto.
(vuint16m4_t): Ditto.
(vuint16m8_t): Ditto.
(vuint32mf2_t): Ditto.
(vuint32m1_t): Ditto.
(vuint32m2_t): Ditto.
(vuint32m4_t): Ditto.
(vuint32m8_t): Ditto.
(vuint64m1_t): Ditto.
(vuint64m2_t): Ditto.
(vuint64m4_t): Ditto.
(vuint64m8_t): Ditto.
(vfloat32mf2_t): Ditto.
(vfloat32m1_t): Ditto.
(vfloat32m2_t): Ditto.
(vfloat32m4_t): Ditto.
(vfloat32m8_t): Ditto.
(vfloat64m1_t): Ditto.
(vfloat64m2_t): Ditto.
(vfloat64m4_t): Ditto.
(vfloat64m8_t): Ditto.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_EI16_OPS): Ditto.
* config/riscv/riscv.md: Adjust RVV instruction types.
* config/riscv/vector-iterators.md (down): New iterator.
(=vd,vr): New attribute.
(UNSPEC_VSLIDE1UP): New unspec.
* config/riscv/vector.md (@pred_slide<ud><mode>): New pattern.
(*pred_slide<ud><mode>): Ditto.
(*pred_slide<ud><mode>_extended): Ditto.
(@pred_gather<mode>): Ditto.
(@pred_gather<mode>_scalar): Ditto.
(@pred_gatherei16<mode>): Ditto.
(@pred_compress<mode>): Ditto.
2023-03-05 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vector-builtins.cc: Remove void_type_node.
2023-03-05 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/constraints.md (Wb1): New constraint.
* config/riscv/predicates.md
(vector_least_significant_set_mask_operand): New predicate.
(vector_broadcast_mask_operand): Ditto.
* config/riscv/riscv-protos.h (enum vlmul_type): Adjust.
(gen_scalar_move_mask): New function.
* config/riscv/riscv-v.cc (gen_scalar_move_mask): Ditto.
* config/riscv/riscv-vector-builtins-bases.cc (class vmv): New class.
(class vmv_s): Ditto.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def (vmv_x): Ditto.
(vmv_s): Ditto.
(vfmv_f): Ditto.
(vfmv_s): Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc (struct scalar_move_def): Ditto.
(SHAPE): Ditto.
* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
* config/riscv/riscv-vector-builtins.cc (function_expander::mask_mode): Ditto.
(function_expander::use_exact_insn): New function.
(function_expander::use_contiguous_load_insn): New function.
(function_expander::use_contiguous_store_insn): New function.
(function_expander::use_ternop_insn): New function.
(function_expander::use_widen_ternop_insn): New function.
(function_expander::use_scalar_move_insn): New function.
* config/riscv/riscv-vector-builtins.def (s): New operand suffix.
* config/riscv/riscv-vector-builtins.h
(function_expander::add_scalar_move_mask_operand): New class.
* config/riscv/riscv-vsetvl.cc (ignore_vlmul_insn_p): New function.
(scalar_move_insn_p): Ditto.
(has_vsetvl_killed_avl_p): Ditto.
(anticipatable_occurrence_p): Ditto.
(insert_vsetvl): Ditto.
(get_vl_vtype_info): Ditto.
(calculate_sew): Ditto.
(calculate_vlmul): Ditto.
(incompatible_avl_p): Ditto.
(different_sew_p): Ditto.
(different_lmul_p): Ditto.
(different_ratio_p): Ditto.
(different_tail_policy_p): Ditto.
(different_mask_policy_p): Ditto.
(possible_zero_avl_p): Ditto.
(first_ratio_invalid_for_second_sew_p): Ditto.
(first_ratio_invalid_for_second_lmul_p): Ditto.
(second_ratio_invalid_for_first_sew_p): Ditto.
(second_ratio_invalid_for_first_lmul_p): Ditto.
(second_sew_less_than_first_sew_p): Ditto.
(first_sew_less_than_second_sew_p): Ditto.
(compare_lmul): Ditto.
(second_lmul_less_than_first_lmul_p): Ditto.
(first_lmul_less_than_second_lmul_p): Ditto.
(first_ratio_less_than_second_ratio_p): Ditto.
(second_ratio_less_than_first_ratio_p): Ditto.
(DEF_INCOMPATIBLE_COND): Ditto.
(greatest_sew): Ditto.
(first_sew): Ditto.
(second_sew): Ditto.
(first_vlmul): Ditto.
(second_vlmul): Ditto.
(first_ratio): Ditto.
(second_ratio): Ditto.
(vlmul_for_first_sew_second_ratio): Ditto.
(ratio_for_second_sew_first_vlmul): Ditto.
(DEF_SEW_LMUL_FUSE_RULE): Ditto.
(always_unavailable): Ditto.
(avl_unavailable_p): Ditto.
(sew_unavailable_p): Ditto.
(lmul_unavailable_p): Ditto.
(ge_sew_unavailable_p): Ditto.
(ge_sew_lmul_unavailable_p): Ditto.
(ge_sew_ratio_unavailable_p): Ditto.
(DEF_UNAVAILABLE_COND): Ditto.
(same_sew_lmul_demand_p): Ditto.
(propagate_avl_across_demands_p): Ditto.
(reg_available_p): Ditto.
(avl_info::has_non_zero_avl): Ditto.
(vl_vtype_info::has_non_zero_avl): Ditto.
(vector_insn_info::operator>=): Refactor.
(vector_insn_info::parse_insn): Adjust for scalar move.
(vector_insn_info::demand_vl_vtype): Remove.
(vector_insn_info::compatible_p): New function.
(vector_insn_info::compatible_avl_p): Ditto.
(vector_insn_info::compatible_vtype_p): Ditto.
(vector_insn_info::available_p): Ditto.
(vector_insn_info::merge): Ditto.
(vector_insn_info::fuse_avl): Ditto.
(vector_insn_info::fuse_sew_lmul): Ditto.
(vector_insn_info::fuse_tail_policy): Ditto.
(vector_insn_info::fuse_mask_policy): Ditto.
(vector_insn_info::dump): Ditto.
(vector_infos_manager::release): Ditto.
(pass_vsetvl::compute_local_backward_infos): Adjust for scalar move support.
(pass_vsetvl::get_backward_fusion_type): Adjust for scalar move support.
(pass_vsetvl::hard_empty_block_p): Ditto.
(pass_vsetvl::backward_demand_fusion): Ditto.
(pass_vsetvl::forward_demand_fusion): Ditto.
(pass_vsetvl::refine_vsetvls): Ditto.
(pass_vsetvl::cleanup_vsetvls): Ditto.
(pass_vsetvl::commit_vsetvls): Ditto.
(pass_vsetvl::propagate_avl): Ditto.
* config/riscv/riscv-vsetvl.h (enum demand_status): New class.
(struct demands_pair): Ditto.
(struct demands_cond): Ditto.
(struct demands_fuse_rule): Ditto.
* config/riscv/vector-iterators.md: New iterator.
* config/riscv/vector.md (@pred_broadcast<mode>): New pattern.
(*pred_broadcast<mode>): Ditto.
(*pred_broadcast<mode>_extended_scalar): Ditto.
(@pred_extract_first<mode>): Ditto.
(*pred_extract_first<mode>): Ditto.
(@pred_extract_first_trunc<mode>): Ditto.
* config/riscv/riscv-vsetvl.def: New file.
2023-03-05 Lin Sinan <sinan.lin@linux.alibaba.com>
* config/riscv/bitmanip.md: allow 0 constant in max/min
pattern.
2023-03-05 Lin Sinan <sinan.lin@linux.alibaba.com>
* config/riscv/bitmanip.md: Fix wrong index in the check.
2023-03-04 Jakub Jelinek <jakub@redhat.com>
PR middle-end/109006
* vec.cc (test_auto_alias): Adjust comment for removal of
m_vecdata.
* read-rtl-function.cc (function_reader::parse_block): Likewise.
* gdbhooks.py: Likewise.
2023-03-04 Jakub Jelinek <jakub@redhat.com>
PR testsuite/108973
* selftest-diagnostic.cc
(test_diagnostic_context::test_diagnostic_context): Set
caret_max_width to 80.
2023-03-03 Alexandre Oliva <oliva@adacore.com>
* gimple-ssa-warn-access.cc
(pass_waccess::check_dangling_stores): Skip non-stores.
2023-03-03 Alexandre Oliva <oliva@adacore.com>
* config/arm/vfp.md (*thumb2_movsi_vfp): Drop blank after tab
after vmsr and vmrs, and lower the case of P0.
2023-03-03 Jonathan Wakely <jwakely@redhat.com>
PR middle-end/109006
* gdbhooks.py (VecPrinter): Handle vec<T> as well as vec<T>*.
2023-03-03 Jonathan Wakely <jwakely@redhat.com>
PR middle-end/109006
* gdbhooks.py (VecPrinter): Adjust for new vec layout.
2023-03-03 Jakub Jelinek <jakub@redhat.com>
PR c/108986
* gimple-ssa-warn-access.cc (pass_waccess::maybe_check_access_sizes):
Return immediately if OPT_Wnonnull or OPT_Wstringop_overflow_ is
suppressed on stmt. For [static %E] warning, print access_nelts
rather than access_size. Fix up comment wording.
2023-03-03 Robin Dapp <rdapp@linux.ibm.com>
* config/s390/driver-native.cc (s390_host_detect_local_cpu): Use
arch14 instead of z16.
2023-03-03 Anthony Green <green@moxielogic.com>
* config/moxie/moxie.cc (TARGET_LRA_P): Remove.
2023-03-03 Anthony Green <green@moxielogic.com>
* config/moxie/constraints.md (A, B, W): Change
define_constraint to define_memory_constraint.
2023-03-03 Xi Ruoyao <xry111@xry111.site>
* toplev.cc (process_options): Fix the spelling of
"-fstack-clash-protection".
2023-03-03 Richard Biener <rguenther@suse.de>
PR tree-optimization/109002
* tree-ssa-pre.cc (compute_partial_antic_aux): Properly
PHI-translate ANTIC_IN.
2023-03-03 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/108988
* gimple-fold.cc (gimple_fold_builtin_fputs): Fold len to
size_type_node before passing it as argument to fwrite. Formatting
fixes.
2023-03-03 Richard Biener <rguenther@suse.de>
PR target/108738
* config/i386/i386.opt (--param x86-stv-max-visits): New param.
* doc/invoke.texi (--param x86-stv-max-visits): Document it.
* config/i386/i386-features.h (scalar_chain::max_visits): New.
(scalar_chain::build): Add bitmap parameter, return boolean.
(scalar_chain::add_insn): Likewise.
(scalar_chain::analyze_register_chain): Likewise.
* config/i386/i386-features.cc (scalar_chain::scalar_chain):
Initialize max_visits.
(scalar_chain::analyze_register_chain): When we exhaust
max_visits, abort. Also abort when running into any
disallowed insn.
(scalar_chain::add_insn): Propagate abort.
(scalar_chain::build): Likewise. When aborting amend
the set of disallowed insn with the insns set.
(convert_scalars_to_vector): Adjust. Do not convert aborted
chains.
2023-03-03 Richard Biener <rguenther@suse.de>
PR debug/108772
* dwarf2out.cc (dwarf2out_late_global_decl): Do not
generate a DIE for a function scope static.
2023-03-03 Alexandre Oliva <oliva@adacore.com>
* config/vx-common.h (WINT_TYPE): Alias to "wchar_t".
2023-03-02 Jakub Jelinek <jakub@redhat.com>
PR target/108883
* target.h (emit_support_tinfos_callback): New typedef.
* targhooks.h (default_emit_support_tinfos): Declare.
* targhooks.cc (default_emit_support_tinfos): New function.
* target.def (emit_support_tinfos): New target hook.
* doc/tm.texi.in (emit_support_tinfos): Document it.
* doc/tm.texi: Regenerated.
* config/i386/i386.cc (ix86_emit_support_tinfos): New function.
(TARGET_EMIT_SUPPORT_TINFOS): Redefine.
2023-03-02 Vladimir N. Makarov <vmakarov@redhat.com>
* ira-costs.cc: Include print-rtl.h.
(record_reg_classes, scan_one_insn): Add code to print debug info.
(record_operand_costs): Find and use smaller cost for hard reg
move.
2023-03-02 Kwok Cheung Yeung <kcy@codesourcery.com>
Paul-Antoine Arras <pa@codesourcery.com>
* builtins.cc (mathfn_built_in_explicit): New.
* config/gcn/gcn.cc: Include case-cfn-macros.h.
(mathfn_built_in_explicit): Add prototype.
(gcn_vectorize_builtin_vectorized_function): New.
(gcn_libc_has_function): New.
(TARGET_LIBC_HAS_FUNCTION): Define.
(TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION): Define.
2023-03-02 Richard Sandiford <richard.sandiford@arm.com>
PR tree-optimization/108979
* tree-vect-stmts.cc (vectorizable_operation): Don't mask
operations on invariants.
2023-03-02 Robin Dapp <rdapp@linux.ibm.com>
* config/s390/predicates.md (vll_bias_operand): Add -1 bias.
* config/s390/s390.cc (s390_option_override_internal): Make
partial vector usage the default from z13 on.
* config/s390/vector.md (len_load_v16qi): Add.
(len_store_v16qi): Add.
2023-03-02 Andre Vieira <andre.simoesdiasvieira@arm.com>
* simplify-rtx.cc (simplify_context::simplify_subreg): Use byte instead
of constant 0 offset.
2023-03-02 Robert Suchanek <robert.suchanek@imgtec.com>
* config/mips/mips.cc (mips_set_text_contents_type): Use HOST_WIDE_INT
instead of long.
* config/mips/mips-protos.h (mips_set_text_contents_type): Likewise.
2023-03-02 Junxian Zhu <zhujunxian@oss.cipunited.com>
* config.gcc: add -with-{no-}msa build option.
* config/mips/mips.h: Likewise.
* doc/install.texi: Likewise.
2023-03-02 Richard Sandiford <richard.sandiford@arm.com>
PR tree-optimization/108603
* explow.cc (convert_memory_address_addr_space_1): Only wrap
the result of a recursive call in a CONST if no instructions
were emitted.
2023-03-02 Richard Sandiford <richard.sandiford@arm.com>
PR tree-optimization/108430
* tree-vect-stmts.cc (vectorizable_condition): Fix handling
of inverted condition.
2023-03-02 Jakub Jelinek <jakub@redhat.com>
PR c++/108934
* fold-const.cc (native_interpret_expr) <case REAL_CST>: Before memcmp
comparison copy the bytes from ptr to a temporary buffer and clearing
padding bits in there.
2023-03-01 Tobias Burnus <tobias@codesourcery.com>
PR middle-end/108545
* gimplify.cc (struct tree_operand_hash_no_se): New.
(omp_index_mapping_groups_1, omp_index_mapping_groups,
omp_reindex_mapping_groups, omp_mapped_by_containing_struct,
omp_tsort_mapping_groups_1, omp_tsort_mapping_groups,
oacc_resolve_clause_dependencies, omp_build_struct_sibling_lists,
gimplify_scan_omp_clauses): Use tree_operand_hash_no_se instead
of tree_operand_hash.
2023-03-01 LIU Hao <lh_mouse@126.com>
PR pch/14940
* config/i386/host-mingw32.cc (mingw32_gt_pch_get_address):
Remove the size limit `pch_VA_max_size`
2023-03-01 Tobias Burnus <tobias@codesourcery.com>
PR middle-end/108546
* omp-low.cc (lower_omp_target): Remove optional handling
on the receiver side, i.e. inside target (data), for
use_device_ptr.
2023-03-01 Jakub Jelinek <jakub@redhat.com>
PR debug/108967
* cfgexpand.cc (expand_debug_expr): Handle WIDEN_{PLUS,MINUS}_EXPR
and VEC_WIDEN_{PLUS,MINUS}_{HI,LO}_EXPR.
2023-03-01 Richard Biener <rguenther@suse.de>
PR tree-optimization/108970
* tree-vect-loop-manip.cc (slpeel_can_duplicate_loop_p):
Check we can copy the BBs.
(slpeel_tree_duplicate_loop_to_edge_cfg): Avoid redundant
check.
(vect_do_peeling): Streamline error handling.
2023-03-01 Richard Biener <rguenther@suse.de>
PR tree-optimization/108950
* tree-vect-patterns.cc (vect_recog_widen_sum_pattern):
Check oprnd0 is defined in the loop.
* tree-vect-loop.cc (vectorizable_reduction): Record all
operands vector types, compute that of invariants and
properly update their SLP nodes.
2023-03-01 Kewen Lin <linkw@linux.ibm.com>
PR target/108240
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Allow
implicit powerpc64 setting to be unset if 64 bit is enabled implicitly.
2023-02-28 Qing Zhao <qing.zhao@oracle.com>
PR middle-end/107411
PR middle-end/107411
* gimplify.cc (gimple_add_init_for_auto_var): Use sprintf to replace
xasprintf.
* tree-ssa-uninit.cc (warn_uninit): Handle the case when the
LHS varaible of a .DEFERRED_INIT call doesn't have a DECL_NAME.
2023-02-28 Jakub Jelinek <jakub@redhat.com>
PR sanitizer/108894
* ubsan.cc (ubsan_expand_bounds_ifn): Emit index >= bound
comparison rather than index > bound.
* gimple-fold.cc (gimple_fold_call): Use tree_int_cst_lt
rather than tree_int_cst_le for IFN_UBSAN_BOUND comparison.
* doc/invoke.texi (-fsanitize=bounds): Document that whether
flexible array member-like arrays are instrumented or not depends
on -fstrict-flex-arrays* options of strict_flex_array attributes.
(-fsanitize=bounds-strict): Document that flexible array members
are not instrumented.
2023-02-27 Uroš Bizjak <ubizjak@gmail.com>
PR target/108922
Revert:
* config/i386/i386.md (fmodxf3): Enable for flag_finite_math_only only.
(fmod<mode>3): Ditto.
(fpremxf4_i387): Ditto.
(reminderxf3): Ditto.
(reminder<mode>3): Ditto.
(fprem1xf4_i387): Ditto.
2023-02-27 Roger Sayle <roger@nextmovesoftware.com>
* simplify-rtx.cc (simplify_unary_operation_1) <case FFS>: Avoid
generating FFS with mismatched operand and result modes, by using
an explicit SIGN_EXTEND/ZERO_EXTEND.
<case POPCOUNT>: Likewise, for POPCOUNT of ZERO_EXTEND.
<case PARITY>: Likewise, for PARITY of {ZERO,SIGN}_EXTEND.
2023-02-27 Patrick Palka <ppalka@redhat.com>
* hash-table.h (gt_pch_nx(hash_table<D>)): Remove static.
* lra-int.h (lra_change_class): Likewise.
* recog.h (which_op_alt): Likewise.
* sel-sched-ir.h (sel_bb_empty_or_nop_p): Declare inline
instead of static.
2023-02-27 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa-protos.h (xtensa_match_CLAMPS_imms_p):
New prototype.
* config/xtensa/xtensa.cc (xtensa_match_CLAMPS_imms_p):
New function.
* config/xtensa/xtensa.h (TARGET_CLAMPS): New macro definition.
* config/xtensa/xtensa.md (*xtensa_clamps): New insn pattern.
2023-02-27 Max Filippov <jcmvbkbc@gmail.com>
* config/xtensa/xtensa-dynconfig.cc (xtensa_get_config_v2)
(xtensa_get_config_v3): New functions.
2023-02-27 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-simd.md (aarch64_abs<mode>): Fix typo in comment.
2023-02-27 Lulu Cheng <chenglulu@loongson.cn>
* config/host-linux.cc (TRY_EMPTY_VM_SPACE): Modify the value of
the macro to 0x1000000000.
2023-02-25 Gaius Mulley <gaiusmod2@gmail.com>
PR modula2/108261
* doc/gm2.texi (-fm2-pathname): New option documented.
(-fm2-pathnameI): New option documented.
(-fm2-prefix=): New option documented.
(-fruntime-modules=): Update default module list.
2023-02-25 Max Filippov <jcmvbkbc@gmail.com>
PR target/108919
* config/xtensa/xtensa-protos.h
(xtensa_prepare_expand_call): Rename to xtensa_expand_call.
* config/xtensa/xtensa.cc (xtensa_prepare_expand_call): Rename
to xtensa_expand_call.
(xtensa_expand_call): Emit the call and add a clobber expression
for the static chain to it in case of windowed ABI.
* config/xtensa/xtensa.md (call, call_value, sibcall)
(sibcall_value): Call xtensa_expand_call and complete expansion
right after that call.
2023-02-24 Richard Biener <rguenther@suse.de>
* vec.h (vec<T, A, vl_embed>::m_vecdata): Remove.
(vec<T, A, vl_embed>::m_vecpfx): Align as T to avoid
changing alignment of vec<T, A, vl_embed> and simplifying
address.
(vec<T, A, vl_embed>::address): Compute as this + 1.
(vec<T, A, vl_embed>::embedded_size): Use sizeof the
vector instead of the offset of the m_vecdata member.
(auto_vec<T, N>::m_data): Turn storage into
uninitialized unsigned char.
(auto_vec<T, N>::auto_vec): Allow allocation of one
stack member. Initialize m_vec in a special way to
avoid later stringop overflow diagnostics.
* vec.cc (test_auto_alias): New.
(vec_cc_tests): Call it.
2023-02-24 Richard Biener <rguenther@suse.de>
* vec.h (vec<T, A, vl_embed>::lower_bound): Adjust to
take a const reference to the object, use address to
access data.
(vec<T, A, vl_embed>::contains): Use address to access data.
(vec<T, A, vl_embed>::operator[]): Use address instead of
m_vecdata to access data.
(vec<T, A, vl_embed>::iterate): Likewise.
(vec<T, A, vl_embed>::copy): Likewise.
(vec<T, A, vl_embed>::quick_push): Likewise.
(vec<T, A, vl_embed>::pop): Likewise.
(vec<T, A, vl_embed>::quick_insert): Likewise.
(vec<T, A, vl_embed>::ordered_remove): Likewise.
(vec<T, A, vl_embed>::unordered_remove): Likewise.
(vec<T, A, vl_embed>::block_remove): Likewise.
(vec<T, A, vl_heap>::address): Likewise.
2023-02-24 Martin Liska <mliska@suse.cz>
PR sanitizer/108834
* asan.cc (asan_add_global): Use proper TU name for normal
global variables (and aux_base_name for the artificial one).
2023-02-24 Jakub Jelinek <jakub@redhat.com>
* config/i386/i386-builtin.def: Update description of BDESC
and BDESC_FIRST in file comment to include mask2.
2023-02-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-cores.def (FLAGS): Update comment.
2023-02-24 Jakub Jelinek <jakub@redhat.com>
PR middle-end/108854
* cgraphclones.cc (duplicate_thunk_for_node): If no parameter
changes are needed, copy at least DECL_ARGUMENTS PARM_DECL
nodes and adjust their DECL_CONTEXT.
2023-02-24 Jakub Jelinek <jakub@redhat.com>
PR target/108881
* config/i386/i386-builtin.def (__builtin_ia32_cvtne2ps2bf16_v16bf,
__builtin_ia32_cvtne2ps2bf16_v16bf_mask,
__builtin_ia32_cvtne2ps2bf16_v16bf_maskz,
__builtin_ia32_cvtne2ps2bf16_v8bf,
__builtin_ia32_cvtne2ps2bf16_v8bf_mask,
__builtin_ia32_cvtne2ps2bf16_v8bf_maskz,
__builtin_ia32_cvtneps2bf16_v8sf_mask,
__builtin_ia32_cvtneps2bf16_v8sf_maskz,
__builtin_ia32_cvtneps2bf16_v4sf_mask,
__builtin_ia32_cvtneps2bf16_v4sf_maskz,
__builtin_ia32_dpbf16ps_v8sf, __builtin_ia32_dpbf16ps_v8sf_mask,
__builtin_ia32_dpbf16ps_v8sf_maskz, __builtin_ia32_dpbf16ps_v4sf,
__builtin_ia32_dpbf16ps_v4sf_mask,
__builtin_ia32_dpbf16ps_v4sf_maskz): Require also
OPTION_MASK_ISA_AVX512VL.
2023-02-24 Sebastian Huber <sebastian.huber@embedded-brains.de>
* config/riscv/t-rtems: Keep only -mcmodel=medany 64-bit multilibs.
Add non-compact 32-bit multilibs.
2023-02-24 Junxian Zhu <zhujunxian@oss.cipunited.com>
* config/mips/mips.md (*clo<mode>2): New pattern.
2023-02-24 Prachi Godbole <prachi.godbole@imgtec.com>
* config/mips/mips.h (machine_function): New variable
use_hazard_barrier_return_p.
* config/mips/mips.md (UNSPEC_JRHB): New unspec.
(mips_hb_return_internal): New insn pattern.
* config/mips/mips.cc (mips_attribute_table): Add attribute
use_hazard_barrier_return.
(mips_use_hazard_barrier_return_p): New static function.
(mips_function_attr_inlinable_p): Likewise.
(mips_compute_frame_info): Set use_hazard_barrier_return_p.
Emit error for unsupported architecture choice.
(mips_function_ok_for_sibcall, mips_can_use_return_insn):
Return false for use_hazard_barrier_return.
(mips_expand_epilogue): Emit hazard barrier return.
* doc/extend.texi: Document use_hazard_barrier_return.
2023-02-23 Max Filippov <jcmvbkbc@gmail.com>
* config/xtensa/xtensa-dynconfig.cc (config.h, system.h)
(coretypes.h, diagnostic.h, intl.h): Use "..." instead of <...>
for the gcc-internal headers.
2023-02-23 Max Filippov <jcmvbkbc@gmail.com>
* config/xtensa/t-xtensa (xtensa-dynconfig.o): Use $(COMPILE)
and $(POSTCOMPILE) instead of manual dependency listing.
* config/xtensa/xtensa-dynconfig.c: Rename to ...
* config/xtensa/xtensa-dynconfig.cc: ... this.
2023-02-23 Arsen Arsenović <arsen@aarsen.me>
* doc/cfg.texi: Reorder index entries around @items.
* doc/cpp.texi: Ditto.
* doc/cppenv.texi: Ditto.
* doc/cppopts.texi: Ditto.
* doc/generic.texi: Ditto.
* doc/install.texi: Ditto.
* doc/extend.texi: Ditto.
* doc/invoke.texi: Ditto.
* doc/md.texi: Ditto.
* doc/rtl.texi: Ditto.
* doc/tm.texi.in: Ditto.
* doc/trouble.texi: Ditto.
* doc/tm.texi: Regenerate.
2023-02-23 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.md: New peephole2 pattern that eliminates
the occurrence of general-purpose register used only once and for
transferring intermediate value.
2023-02-23 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.cc (machine_function): Add new member
'eliminated_callee_saved_bmp'.
(xtensa_can_eliminate_callee_saved_reg_p): New function to
determine whether the register can be eliminated or not.
(xtensa_expand_prologue): Add invoking the above function and
elimination the use of callee-saved register by using its stack
slot through the stack pointer (or the frame pointer if needed)
directly.
(xtensa_expand_prologue): Modify to not emit register restoration
insn from its stack slot if the register is already eliminated.
2023-02-23 Jakub Jelinek <jakub@redhat.com>
PR translation/108890
* config/xtensa/xtensa-dynconfig.c (xtensa_load_config): Drop _()s
around fatal_error format strings.
2023-02-23 Richard Biener <rguenther@suse.de>
* tree-ssa-structalias.cc (handle_lhs_call): Do not
re-create rhsc, only truncate it.
2023-02-23 Jakub Jelinek <jakub@redhat.com>
PR middle-end/106258
* ipa-prop.cc (try_make_edge_direct_virtual_call): Handle
BUILT_IN_UNREACHABLE_TRAP like BUILT_IN_UNREACHABLE.
2023-02-23 Richard Biener <rguenther@suse.de>
* tree-if-conv.cc (tree_if_conversion): Properly manage
memory of refs and the contained data references.
2023-02-23 Richard Biener <rguenther@suse.de>
PR tree-optimization/108888
* tree-if-conv.cc (if_convertible_stmt_p): Set PLF_2 on
calls to predicate.
(predicate_statements): Only predicate calls with PLF_2.
2023-02-23 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.md
(zero_cost_loop_start, zero_cost_loop_end, loop_end):
Add missing "SI:" to PLUS RTXes.
2023-02-23 Max Filippov <jcmvbkbc@gmail.com>
PR target/108876
* config/xtensa/xtensa.cc (xtensa_expand_epilogue):
Emit (use (reg:SI A0_REG)) at the end in the sibling call
(i.e. the same place as (return) in the normal call).
2023-02-23 Max Filippov <jcmvbkbc@gmail.com>
Revert:
2023-02-21 Max Filippov <jcmvbkbc@gmail.com>
PR target/108876
* config/xtensa/xtensa.cc (xtensa_expand_epilogue): Drop emit_use
for A0_REG.
* config/xtensa/xtensa.md (sibcall, sibcall_internal)
(sibcall_value, sibcall_value_internal): Add 'use' expression
for A0_REG.
2023-02-23 Arsen Arsenović <arsen@aarsen.me>
* doc/cppdiropts.texi: Reorder @opindex commands to precede
@items they relate to.
* doc/cppopts.texi: Ditto.
* doc/cppwarnopts.texi: Ditto.
* doc/invoke.texi: Ditto.
* doc/lto.texi: Ditto.
2023-02-22 Andrew Stubbs <ams@codesourcery.com>
* internal-fn.cc (expand_MASK_CALL): New.
* internal-fn.def (MASK_CALL): New.
* internal-fn.h (expand_MASK_CALL): New prototype.
* omp-simd-clone.cc (simd_clone_adjust_argument_types): Set vector_type
for mask arguments also.
* tree-if-conv.cc: Include cgraph.h.
(if_convertible_stmt_p): Do if conversions for calls to SIMD calls.
(predicate_statements): Convert functions to IFN_MASK_CALL.
* tree-vect-loop.cc (vect_get_datarefs_in_loop): Recognise
IFN_MASK_CALL as a SIMD function call.
* tree-vect-stmts.cc (vectorizable_simd_clone_call): Handle
IFN_MASK_CALL as an inbranch SIMD function call.
Generate the mask vector arguments.
2023-02-22 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vector-builtins-bases.cc (class reducop): New class.
(class widen_reducop): Ditto.
(class freducop): Ditto.
(class widen_freducop): Ditto.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def (vredsum): Add reduction support.
(vredmaxu): Ditto.
(vredmax): Ditto.
(vredminu): Ditto.
(vredmin): Ditto.
(vredand): Ditto.
(vredor): Ditto.
(vredxor): Ditto.
(vwredsum): Ditto.
(vwredsumu): Ditto.
(vfredusum): Ditto.
(vfredosum): Ditto.
(vfredmax): Ditto.
(vfredmin): Ditto.
(vfwredosum): Ditto.
(vfwredusum): Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc (struct reduc_alu_def): Ditto.
(SHAPE): Ditto.
* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_WI_OPS): New macro.
(DEF_RVV_WU_OPS): Ditto.
(DEF_RVV_WF_OPS): Ditto.
(vint8mf8_t): Ditto.
(vint8mf4_t): Ditto.
(vint8mf2_t): Ditto.
(vint8m1_t): Ditto.
(vint8m2_t): Ditto.
(vint8m4_t): Ditto.
(vint8m8_t): Ditto.
(vint16mf4_t): Ditto.
(vint16mf2_t): Ditto.
(vint16m1_t): Ditto.
(vint16m2_t): Ditto.
(vint16m4_t): Ditto.
(vint16m8_t): Ditto.
(vint32mf2_t): Ditto.
(vint32m1_t): Ditto.
(vint32m2_t): Ditto.
(vint32m4_t): Ditto.
(vint32m8_t): Ditto.
(vuint8mf8_t): Ditto.
(vuint8mf4_t): Ditto.
(vuint8mf2_t): Ditto.
(vuint8m1_t): Ditto.
(vuint8m2_t): Ditto.
(vuint8m4_t): Ditto.
(vuint8m8_t): Ditto.
(vuint16mf4_t): Ditto.
(vuint16mf2_t): Ditto.
(vuint16m1_t): Ditto.
(vuint16m2_t): Ditto.
(vuint16m4_t): Ditto.
(vuint16m8_t): Ditto.
(vuint32mf2_t): Ditto.
(vuint32m1_t): Ditto.
(vuint32m2_t): Ditto.
(vuint32m4_t): Ditto.
(vuint32m8_t): Ditto.
(vfloat32mf2_t): Ditto.
(vfloat32m1_t): Ditto.
(vfloat32m2_t): Ditto.
(vfloat32m4_t): Ditto.
(vfloat32m8_t): Ditto.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_WI_OPS): Ditto.
(DEF_RVV_WU_OPS): Ditto.
(DEF_RVV_WF_OPS): Ditto.
(required_extensions_p): Add reduction support.
(rvv_arg_type_info::get_base_vector_type): Ditto.
(rvv_arg_type_info::get_tree_type): Ditto.
* config/riscv/riscv-vector-builtins.h (enum rvv_base_type): Ditto.
* config/riscv/riscv.md: Ditto.
* config/riscv/vector-iterators.md (minu): Ditto.
* config/riscv/vector.md (@pred_reduc_<reduc><mode><vlmul1>): New patern.
(@pred_reduc_<reduc><mode><vlmul1_zve32>): Ditto.
(@pred_widen_reduc_plus<v_su><mode><vwlmul1>): Ditto.
(@pred_widen_reduc_plus<v_su><mode><vwlmul1_zve32>):Ditto.
(@pred_reduc_plus<order><mode><vlmul1>): Ditto.
(@pred_reduc_plus<order><mode><vlmul1_zve32>): Ditto.
(@pred_widen_reduc_plus<order><mode><vwlmul1>): Ditto.
2023-02-22 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/iterators.md: New iterator.
* config/riscv/riscv-vector-builtins-bases.cc (class widen_binop): New class.
(enum ternop_type): New enum.
(class vmacc): New class.
(class imac): Ditto.
(class vnmsac): Ditto.
(enum widen_ternop_type): New enum.
(class vmadd): Ditto.
(class vnmsub): Ditto.
(class iwmac): Ditto.
(class vwmacc): Ditto.
(class vwmaccu): Ditto.
(class vwmaccsu): Ditto.
(class vwmaccus): Ditto.
(class reverse_binop): Ditto.
(class vfmacc): Ditto.
(class vfnmsac): Ditto.
(class vfmadd): Ditto.
(class vfnmsub): Ditto.
(class vfnmacc): Ditto.
(class vfmsac): Ditto.
(class vfnmadd): Ditto.
(class vfmsub): Ditto.
(class vfwmacc): Ditto.
(class vfwnmacc): Ditto.
(class vfwmsac): Ditto.
(class vfwnmsac): Ditto.
(class float_misc): Ditto.
(class fcmp): Ditto.
(class vfclass): Ditto.
(class vfcvt_x): Ditto.
(class vfcvt_rtz_x): Ditto.
(class vfcvt_f): Ditto.
(class vfwcvt_x): Ditto.
(class vfwcvt_rtz_x): Ditto.
(class vfwcvt_f): Ditto.
(class vfncvt_x): Ditto.
(class vfncvt_rtz_x): Ditto.
(class vfncvt_f): Ditto.
(class vfncvt_rod_f): Ditto.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h:
* config/riscv/riscv-vector-builtins-functions.def (vzext): Ditto.
(vsext): Ditto.
(vfadd): Ditto.
(vfsub): Ditto.
(vfrsub): Ditto.
(vfwadd): Ditto.
(vfwsub): Ditto.
(vfmul): Ditto.
(vfdiv): Ditto.
(vfrdiv): Ditto.
(vfwmul): Ditto.
(vfmacc): Ditto.
(vfnmsac): Ditto.
(vfmadd): Ditto.
(vfnmsub): Ditto.
(vfnmacc): Ditto.
(vfmsac): Ditto.
(vfnmadd): Ditto.
(vfmsub): Ditto.
(vfwmacc): Ditto.
(vfwnmacc): Ditto.
(vfwmsac): Ditto.
(vfwnmsac): Ditto.
(vfsqrt): Ditto.
(vfrsqrt7): Ditto.
(vfrec7): Ditto.
(vfmin): Ditto.
(vfmax): Ditto.
(vfsgnj): Ditto.
(vfsgnjn): Ditto.
(vfsgnjx): Ditto.
(vfneg): Ditto.
(vfabs): Ditto.
(vmfeq): Ditto.
(vmfne): Ditto.
(vmflt): Ditto.
(vmfle): Ditto.
(vmfgt): Ditto.
(vmfge): Ditto.
(vfclass): Ditto.
(vfmerge): Ditto.
(vfmv_v): Ditto.
(vfcvt_x): Ditto.
(vfcvt_xu): Ditto.
(vfcvt_rtz_x): Ditto.
(vfcvt_rtz_xu): Ditto.
(vfcvt_f): Ditto.
(vfwcvt_x): Ditto.
(vfwcvt_xu): Ditto.
(vfwcvt_rtz_x): Ditto.
(vfwcvt_rtz_xu): Ditto.
(vfwcvt_f): Ditto.
(vfncvt_x): Ditto.
(vfncvt_xu): Ditto.
(vfncvt_rtz_x): Ditto.
(vfncvt_rtz_xu): Ditto.
(vfncvt_f): Ditto.
(vfncvt_rod_f): Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): Ditto.
(struct move_def): Ditto.
* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_WEXTF_OPS): New macro.
(DEF_RVV_CONVERT_I_OPS): Ditto.
(DEF_RVV_CONVERT_U_OPS): Ditto.
(DEF_RVV_WCONVERT_I_OPS): Ditto.
(DEF_RVV_WCONVERT_U_OPS): Ditto.
(DEF_RVV_WCONVERT_F_OPS): Ditto.
(vfloat64m1_t): Ditto.
(vfloat64m2_t): Ditto.
(vfloat64m4_t): Ditto.
(vfloat64m8_t): Ditto.
(vint32mf2_t): Ditto.
(vint32m1_t): Ditto.
(vint32m2_t): Ditto.
(vint32m4_t): Ditto.
(vint32m8_t): Ditto.
(vint64m1_t): Ditto.
(vint64m2_t): Ditto.
(vint64m4_t): Ditto.
(vint64m8_t): Ditto.
(vuint32mf2_t): Ditto.
(vuint32m1_t): Ditto.
(vuint32m2_t): Ditto.
(vuint32m4_t): Ditto.
(vuint32m8_t): Ditto.
(vuint64m1_t): Ditto.
(vuint64m2_t): Ditto.
(vuint64m4_t): Ditto.
(vuint64m8_t): Ditto.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_CONVERT_I_OPS): Ditto.
(DEF_RVV_CONVERT_U_OPS): Ditto.
(DEF_RVV_WCONVERT_I_OPS): Ditto.
(DEF_RVV_WCONVERT_U_OPS): Ditto.
(DEF_RVV_WCONVERT_F_OPS): Ditto.
(DEF_RVV_F_OPS): Ditto.
(DEF_RVV_WEXTF_OPS): Ditto.
(required_extensions_p): Adjust for floating-point support.
(check_required_extensions): Ditto.
(unsigned_base_type_p): Ditto.
(get_mode_for_bitsize): Ditto.
(rvv_arg_type_info::get_base_vector_type): Ditto.
(rvv_arg_type_info::get_tree_type): Ditto.
* config/riscv/riscv-vector-builtins.def (v_f): New define.
(f): New define.
(f_v): New define.
(xu_v): New define.
(f_w): New define.
(xu_w): New define.
* config/riscv/riscv-vector-builtins.h (enum rvv_base_type): New enum.
(function_expander::arg_mode): New function.
* config/riscv/vector-iterators.md (sof): New iterator.
(vfrecp): Ditto.
(copysign): Ditto.
(n): Ditto.
(msac): Ditto.
(msub): Ditto.
(fixuns_trunc): Ditto.
(floatuns): Ditto.
* config/riscv/vector.md (@pred_broadcast<mode>): New pattern.
(@pred_<optab><mode>): Ditto.
(@pred_<optab><mode>_scalar): Ditto.
(@pred_<optab><mode>_reverse_scalar): Ditto.
(@pred_<copysign><mode>): Ditto.
(@pred_<copysign><mode>_scalar): Ditto.
(@pred_mul_<optab><mode>): Ditto.
(pred_mul_<optab><mode>_undef_merge): Ditto.
(*pred_<madd_nmsub><mode>): Ditto.
(*pred_<macc_nmsac><mode>): Ditto.
(*pred_mul_<optab><mode>): Ditto.
(@pred_mul_<optab><mode>_scalar): Ditto.
(*pred_mul_<optab><mode>_undef_merge_scalar): Ditto.
(*pred_<madd_nmsub><mode>_scalar): Ditto.
(*pred_<macc_nmsac><mode>_scalar): Ditto.
(*pred_mul_<optab><mode>_scalar): Ditto.
(@pred_neg_mul_<optab><mode>): Ditto.
(pred_neg_mul_<optab><mode>_undef_merge): Ditto.
(*pred_<nmadd_msub><mode>): Ditto.
(*pred_<nmacc_msac><mode>): Ditto.
(*pred_neg_mul_<optab><mode>): Ditto.
(@pred_neg_mul_<optab><mode>_scalar): Ditto.
(*pred_neg_mul_<optab><mode>_undef_merge_scalar): Ditto.
(*pred_<nmadd_msub><mode>_scalar): Ditto.
(*pred_<nmacc_msac><mode>_scalar): Ditto.
(*pred_neg_mul_<optab><mode>_scalar): Ditto.
(@pred_<misc_op><mode>): Ditto.
(@pred_class<mode>): Ditto.
(@pred_dual_widen_<optab><mode>): Ditto.
(@pred_dual_widen_<optab><mode>_scalar): Ditto.
(@pred_single_widen_<plus_minus:optab><mode>): Ditto.
(@pred_single_widen_<plus_minus:optab><mode>_scalar): Ditto.
(@pred_widen_mul_<optab><mode>): Ditto.
(@pred_widen_mul_<optab><mode>_scalar): Ditto.
(@pred_widen_neg_mul_<optab><mode>): Ditto.
(@pred_widen_neg_mul_<optab><mode>_scalar): Ditto.
(@pred_cmp<mode>): Ditto.
(*pred_cmp<mode>): Ditto.
(*pred_cmp<mode>_narrow): Ditto.
(@pred_cmp<mode>_scalar): Ditto.
(*pred_cmp<mode>_scalar): Ditto.
(*pred_cmp<mode>_scalar_narrow): Ditto.
(@pred_eqne<mode>_scalar): Ditto.
(*pred_eqne<mode>_scalar): Ditto.
(*pred_eqne<mode>_scalar_narrow): Ditto.
(@pred_merge<mode>_scalar): Ditto.
(@pred_fcvt_x<v_su>_f<mode>): Ditto.
(@pred_<fix_cvt><mode>): Ditto.
(@pred_<float_cvt><mode>): Ditto.
(@pred_widen_fcvt_x<v_su>_f<mode>): Ditto.
(@pred_widen_<fix_cvt><mode>): Ditto.
(@pred_widen_<float_cvt><mode>): Ditto.
(@pred_extend<mode>): Ditto.
(@pred_narrow_fcvt_x<v_su>_f<mode>): Ditto.
(@pred_narrow_<fix_cvt><mode>): Ditto.
(@pred_narrow_<float_cvt><mode>): Ditto.
(@pred_trunc<mode>): Ditto.
(@pred_rod_trunc<mode>): Ditto.
2023-02-22 Jakub Jelinek <jakub@redhat.com>
PR middle-end/106258
* cgraph.cc (cgraph_edge::redirect_call_stmt_to_callee,
cgraph_update_edges_for_call_stmt_node, cgraph_node::verify_node):
Handle BUILT_IN_UNREACHABLE_TRAP like BUILT_IN_UNREACHABLE.
* cgraphclones.cc (cgraph_node::create_clone): Likewise.
2023-02-22 Thomas Schwinge <thomas@codesourcery.com>
* common.opt (-Wcomplain-wrong-lang): New.
* doc/invoke.texi (-Wno-complain-wrong-lang): Document it.
* opts-common.cc (prune_options): Handle it.
* opts-global.cc (complain_wrong_lang): Use it.
2023-02-21 David Malcolm <dmalcolm@redhat.com>
PR analyzer/108830
* doc/invoke.texi: Document -fno-analyzer-suppress-followups.
2023-02-21 Max Filippov <jcmvbkbc@gmail.com>
PR target/108876
* config/xtensa/xtensa.cc (xtensa_expand_epilogue): Drop emit_use
for A0_REG.
* config/xtensa/xtensa.md (sibcall, sibcall_internal)
(sibcall_value, sibcall_value_internal): Add 'use' expression
for A0_REG.
2023-02-21 Richard Biener <rguenther@suse.de>
PR tree-optimization/108691
* tree-ssa-dce.cc (eliminate_unnecessary_stmts): Remove
assert about calls_setjmp not becoming true when it was false.
2023-02-21 Richard Biener <rguenther@suse.de>
PR tree-optimization/108793
* tree-ssa-loop-niter.cc (number_of_iterations_until_wrap):
Use convert operands to niter_type when computing num.
2023-02-21 Richard Biener <rguenther@suse.de>
Revert:
2023-02-13 Richard Biener <rguenther@suse.de>
PR tree-optimization/108691
* tree-cfg.cc (notice_special_calls): When the CFG is built
honor gimple_call_ctrl_altering_p.
* cfgexpand.cc (expand_call_stmt): Clear cfun->calls_setjmp
temporarily if the call is not control-altering.
* calls.cc (emit_call_1): Do not add REG_SETJMP if
cfun->calls_setjmp is not set. Do not alter cfun->calls_setjmp.
2023-02-21 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.cc (xtensa_call_save_reg): Change to return
true if register A0 (return address register) when -Og is specified.
2023-02-20 Uroš Bizjak <ubizjak@gmail.com>
* config/i386/predicates.md
(general_x64constmem_operand): New predicate.
* config/i386/i386.md (*cmpqi_ext<mode>_1):
Use nonimm_x64constmem_operand.
(*cmpqi_ext<mode>_3): Use general_x64constmem_operand.
(*addqi_ext<mode>_1): Ditto.
(*testqi_ext<mode>_1): Ditto.
(*andqi_ext<mode>_1): Ditto.
(*andqi_ext<mode>_1_cc): Ditto.
(*<any_or:code>qi_ext<mode>_1): Ditto.
(*xorqi_ext<mode>_1_cc): Ditto.
2023-02-20 Jakub Jelinek <jakub2redhat.com>
PR target/108862
* config/rs6000/rs6000.md (umaddditi4): Swap gen_maddlddi4 with
gen_umadddi4_highpart{,_le}.
2023-02-20 Kito Cheng <kito.cheng@sifive.com>
* config/riscv/riscv.md (prefetch): Use r instead of p for the
address operand.
(riscv_prefetchi_<mode>): Ditto.
2023-02-20 Richard Biener <rguenther@suse.de>
PR tree-optimization/108816
* tree-vect-loop-manip.cc (vect_loop_versioning): Adjust
versioning condition split prerequesite, assert required
invariant.
2023-02-20 Richard Biener <rguenther@suse.de>
PR tree-optimization/108825
* tree-ssa-loop-manip.cc (verify_loop_closed_ssa): For
loop-local verfication only verify there's no pending SSA
update.
2023-02-20 Richard Biener <rguenther@suse.de>
PR tree-optimization/108819
* tree-ssa-loop-niter.cc (number_of_iterations_cltz): Check
we have an SSA name as iv_2 as expected.
2023-02-18 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/108819
* tree-ssa-reassoc.cc (update_ops): Fold new stmt in place.
2023-02-18 Jakub Jelinek <jakub@redhat.com>
PR target/108832
* config/i386/i386-protos.h (ix86_replace_reg_with_reg): Declare.
* config/i386/i386-expand.cc (ix86_replace_reg_with_reg): New
function.
* config/i386/i386.md: Replace replace_rtx calls in all peephole2s
with ix86_replace_reg_with_reg.
2023-02-18 Gerald Pfeifer <gerald@pfeifer.com>
* doc/invoke.texi (AVR Options): Update link to AVR-LibC.
2023-02-18 Xi Ruoyao <xry111@xry111.site>
* config.gcc (triplet_abi): Set its value based on $with_abi,
instead of $target.
(la_canonical_triplet): Set it after $triplet_abi is set
correctly.
* config/loongarch/t-linux (MULTILIB_OSDIRNAMES): Make the
multiarch tuple for lp64d "loongarch64-linux-gnu" (without
"f64" suffix).
2023-02-18 Andrew Pinski <apinski@marvell.com>
* match.pd: Remove #if GIMPLE around the
"1 - a" pattern
2023-02-18 Andrew Pinski <apinski@marvell.com>
* value-query.h (get_range_query): Return the global ranges
for a nullptr func.
2023-02-17 Siddhesh Poyarekar <siddhesh@gotplt.org>
* doc/invoke.texi (@item -Wall): Fix typo in
-Wuse-after-free.
2023-02-17 Uroš Bizjak <ubizjak@gmail.com>
PR target/108831
* config/i386/predicates.md
(nonimm_x64constmem_operand): New predicate.
* config/i386/i386.md (*addqi_ext<mode>_0): New insn pattern.
(*subqi_ext<mode>_0): Ditto.
(*andqi_ext<mode>_0): Ditto.
(*<any_or:code>qi_ext<mode>_0): Ditto.
2023-02-17 Uroš Bizjak <ubizjak@gmail.com>
PR target/108805
* simplify-rtx.cc (simplify_context::simplify_subreg): Use
int_outermode instead of GET_MODE (tem) to prevent
VOIDmode from entering simplify_gen_subreg.
2023-02-17 Richard Biener <rguenther@suse.de>
PR tree-optimization/108821
* tree-ssa-loop-im.cc (sm_seq_valid_bb): We can also not
move volatile accesses.
2023-02-17 Richard Biener <rguenther@suse.de>
* tree-ssa.cc (ssa_undefined_value_p): Assert we are not
called on virtual operands.
* tree-ssa-sccvn.cc (vn_phi_lookup): Guard
ssa_undefined_value_p calls.
(vn_phi_insert): Likewise.
(set_ssa_val_to): Likewise.
(visit_phi): Avoid extra work with equivalences for
virtual operand PHIs.
2023-02-17 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vector-builtins-bases.cc (class mask_logic): New
class.
(class mask_nlogic): Ditto.
(class mask_notlogic): Ditto.
(class vmmv): Ditto.
(class vmclr): Ditto.
(class vmset): Ditto.
(class vmnot): Ditto.
(class vcpop): Ditto.
(class vfirst): Ditto.
(class mask_misc): Ditto.
(class viota): Ditto.
(class vid): Ditto.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def (vmand): Ditto.
(vmnand): Ditto.
(vmandn): Ditto.
(vmxor): Ditto.
(vmor): Ditto.
(vmnor): Ditto.
(vmorn): Ditto.
(vmxnor): Ditto.
(vmmv): Ditto.
(vmclr): Ditto.
(vmset): Ditto.
(vmnot): Ditto.
(vcpop): Ditto.
(vfirst): Ditto.
(vmsbf): Ditto.
(vmsif): Ditto.
(vmsof): Ditto.
(viota): Ditto.
(vid): Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): Ditto.
(struct mask_alu_def): Ditto.
(SHAPE): Ditto.
* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
* config/riscv/riscv-vector-builtins.cc: Ditto.
* config/riscv/riscv-vsetvl.cc (pass_vsetvl::cleanup_insns): Fix bug
for dest it scalar RVV intrinsics.
* config/riscv/vector-iterators.md (sof): New iterator.
* config/riscv/vector.md (@pred_<optab>n<mode>): New pattern.
(@pred_<optab>not<mode>): New pattern.
(@pred_popcount<VB:mode><P:mode>): New pattern.
(@pred_ffs<VB:mode><P:mode>): New pattern.
(@pred_<misc_op><mode>): New pattern.
(@pred_iota<mode>): New pattern.
(@pred_series<mode>): New pattern.
2023-02-17 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vector-builtins-functions.def (vadc): Rename.
(vsbc): Ditto.
(vmerge): Ditto.
(vmv_v): Ditto.
* config/riscv/riscv-vector-builtins.cc: Ditto.
2023-02-17 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
kito-cheng <kito.cheng@sifive.com>
* config/riscv/riscv-protos.h (sew64_scalar_helper): New function.
* config/riscv/riscv-v.cc (has_vi_variant_p): Adjust.
(sew64_scalar_helper): New function.
* config/riscv/vector.md: Normalization.
2023-02-17 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vector-builtins-functions.def (vsetvlmax): Rearrange.
(vsm): Ditto.
(vsse): Ditto.
(vsoxei64): Ditto.
(vsub): Ditto.
(vand): Ditto.
(vor): Ditto.
(vxor): Ditto.
(vsll): Ditto.
(vsra): Ditto.
(vsrl): Ditto.
(vmin): Ditto.
(vmax): Ditto.
(vminu): Ditto.
(vmaxu): Ditto.
(vmul): Ditto.
(vmulh): Ditto.
(vmulhu): Ditto.
(vmulhsu): Ditto.
(vdiv): Ditto.
(vrem): Ditto.
(vdivu): Ditto.
(vremu): Ditto.
(vnot): Ditto.
(vsext): Ditto.
(vzext): Ditto.
(vwadd): Ditto.
(vwsub): Ditto.
(vwmul): Ditto.
(vwmulu): Ditto.
(vwmulsu): Ditto.
(vwaddu): Ditto.
(vwsubu): Ditto.
(vsbc): Ditto.
(vmsbc): Ditto.
(vnsra): Ditto.
(vmerge): Ditto.
(vmv_v): Ditto.
(vmsne): Ditto.
(vmslt): Ditto.
(vmsgt): Ditto.
(vmsle): Ditto.
(vmsge): Ditto.
(vmsltu): Ditto.
(vmsgtu): Ditto.
(vmsleu): Ditto.
(vmsgeu): Ditto.
(vnmsac): Ditto.
(vmadd): Ditto.
(vnmsub): Ditto.
(vwmacc): Ditto.
(vsadd): Ditto.
(vssub): Ditto.
(vssubu): Ditto.
(vaadd): Ditto.
(vasub): Ditto.
(vasubu): Ditto.
(vsmul): Ditto.
(vssra): Ditto.
(vssrl): Ditto.
(vnclip): Ditto.
2023-02-17 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/vector.md (@pred_<optab><mode>): Rearrange.
(@pred_<optab><mode>_scalar): Ditto.
(*pred_<optab><mode>_scalar): Ditto.
(*pred_<optab><mode>_extended_scalar): Ditto.
2023-02-17 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-protos.h (riscv_run_selftests): Remove 'extern'.
(init_builtins): Ditto.
(mangle_builtin_type): Ditto.
(verify_type_context): Ditto.
(handle_pragma_vector): Ditto.
(builtin_decl): Ditto.
(expand_builtin): Ditto.
(const_vec_all_same_in_range_p): Ditto.
(legitimize_move): Ditto.
(emit_vlmax_op): Ditto.
(emit_nonvlmax_op): Ditto.
(get_vlmul): Ditto.
(get_ratio): Ditto.
(get_ta): Ditto.
(get_ma): Ditto.
(get_avl_type): Ditto.
(calculate_ratio): Ditto.
(enum vlmul_type): Ditto.
(simm5_p): Ditto.
(neg_simm5_p): Ditto.
(has_vi_variant_p): Ditto.
2023-02-17 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-protos.h (simm32_p): Remove.
* config/riscv/riscv-v.cc (simm32_p): Ditto.
* config/riscv/vector.md: Use immediate_operand
instead of riscv_vector::simm32_p.
2023-02-16 Gerald Pfeifer <gerald@pfeifer.com>
* doc/invoke.texi (Optimize Options): Reword the explanation
getting minimal, maximal and default values of a parameter.
2023-02-16 Patrick Palka <ppalka@redhat.com>
* addresses.h: Mechanically drop 'static' from 'static inline'
functions via s/^static inline/inline/g.
* asan.h: Likewise.
* attribs.h: Likewise.
* basic-block.h: Likewise.
* bitmap.h: Likewise.
* cfghooks.h: Likewise.
* cfgloop.h: Likewise.
* cgraph.h: Likewise.
* cselib.h: Likewise.
* data-streamer.h: Likewise.
* debug.h: Likewise.
* df.h: Likewise.
* diagnostic.h: Likewise.
* dominance.h: Likewise.
* dumpfile.h: Likewise.
* emit-rtl.h: Likewise.
* except.h: Likewise.
* expmed.h: Likewise.
* expr.h: Likewise.
* fixed-value.h: Likewise.
* gengtype.h: Likewise.
* gimple-expr.h: Likewise.
* gimple-iterator.h: Likewise.
* gimple-predict.h: Likewise.
* gimple-range-fold.h: Likewise.
* gimple-ssa.h: Likewise.
* gimple.h: Likewise.
* graphite.h: Likewise.
* hard-reg-set.h: Likewise.
* hash-map.h: Likewise.
* hash-set.h: Likewise.
* hash-table.h: Likewise.
* hwint.h: Likewise.
* input.h: Likewise.
* insn-addr.h: Likewise.
* internal-fn.h: Likewise.
* ipa-fnsummary.h: Likewise.
* ipa-icf-gimple.h: Likewise.
* ipa-inline.h: Likewise.
* ipa-modref.h: Likewise.
* ipa-prop.h: Likewise.
* ira-int.h: Likewise.
* ira.h: Likewise.
* lra-int.h: Likewise.
* lra.h: Likewise.
* lto-streamer.h: Likewise.
* memmodel.h: Likewise.
* omp-general.h: Likewise.
* optabs-query.h: Likewise.
* optabs.h: Likewise.
* plugin.h: Likewise.
* pretty-print.h: Likewise.
* range.h: Likewise.
* read-md.h: Likewise.
* recog.h: Likewise.
* regs.h: Likewise.
* rtl-iter.h: Likewise.
* rtl.h: Likewise.
* sbitmap.h: Likewise.
* sched-int.h: Likewise.
* sel-sched-ir.h: Likewise.
* sese.h: Likewise.
* sparseset.h: Likewise.
* ssa-iterators.h: Likewise.
* system.h: Likewise.
* target-globals.h: Likewise.
* target.h: Likewise.
* timevar.h: Likewise.
* tree-chrec.h: Likewise.
* tree-data-ref.h: Likewise.
* tree-iterator.h: Likewise.
* tree-outof-ssa.h: Likewise.
* tree-phinodes.h: Likewise.
* tree-scalar-evolution.h: Likewise.
* tree-sra.h: Likewise.
* tree-ssa-alias.h: Likewise.
* tree-ssa-live.h: Likewise.
* tree-ssa-loop-manip.h: Likewise.
* tree-ssa-loop.h: Likewise.
* tree-ssa-operands.h: Likewise.
* tree-ssa-propagate.h: Likewise.
* tree-ssa-sccvn.h: Likewise.
* tree-ssa.h: Likewise.
* tree-ssanames.h: Likewise.
* tree-streamer.h: Likewise.
* tree-switch-conversion.h: Likewise.
* tree-vectorizer.h: Likewise.
* tree.h: Likewise.
* wide-int.h: Likewise.
2023-02-16 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/108657
* tree-ssa-dse.cc (initialize_ao_ref_for_dse): If lhs of stmt
exists and is not a SSA_NAME, call ao_ref_init even if the stmt
is a call to internal or builtin function.
2023-02-16 Jonathan Wakely <jwakely@redhat.com>
* doc/invoke.texi (C++ Dialect Options): Suggest adding a
using-declaration to unhide functions.
2023-02-16 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/108783
* tree-ssa-reassoc.cc (eliminate_redundant_comparison): If lcode
is equal to TREE_CODE (t), op1 to newop1 and op2 to newop2, set
t to curr->op. Otherwise, punt if either newop1 or newop2 are
SSA_NAME_OCCURS_IN_ABNORMAL_PHI SSA_NAMEs.
2023-02-16 Richard Biener <rguenther@suse.de>
PR tree-optimization/108791
* tree-ssa-forwprop.cc (optimize_vector_load): Build
the ADDR_EXPR of a TARGET_MEM_REF using a more meaningful
type.
2023-02-15 Eric Botcazou <ebotcazou@adacore.com>
PR target/90458
* config/i386/i386.cc (ix86_compute_frame_layout): Disable the
effects of -fstack-clash-protection for TARGET_STACK_PROBE.
(ix86_expand_prologue): Likewise.
2023-02-15 Jan-Benedict Glaw <jbglaw@lug-owl.de>
* config/bpf/bpf.cc (bpf_option_override): Fix doubled space.
2023-02-15 Uroš Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (*cmpqi_ext<mode>_1): Use
int248_register_operand predicate in zero_extract sub-RTX.
(*cmpqi_ext<mode>_2): Ditto.
(*cmpqi_ext<mode>_3): Ditto.
(*cmpqi_ext<mode>_4): Ditto.
(*extzvqi_mem_rex64): Ditto.
(*extzvqi): Ditto.
(*insvqi_1_mem_rex64): Ditto.
(@insv<mode>_1): Ditto.
(*insvqi_1): Ditto.
(*insvqi_2): Ditto.
(*insvqi_3): Ditto.
(*extendqi<SWI24:mode>_ext_1): Ditto.
(*addqi_ext<mode>_1): Ditto.
(*addqi_ext<mode>_2): Ditto.
(*subqi_ext<mode>_2): Ditto.
(*testqi_ext<mode>_1): Ditto.
(*testqi_ext<mode>_2): Ditto.
(*andqi_ext<mode>_1): Ditto.
(*andqi_ext<mode>_1_cc): Ditto.
(*andqi_ext<mode>_2): Ditto.
(*<any_or:code>qi_ext<mode>_1): Ditto.
(*<any_or:code>qi_ext<mode>_2): Ditto.
(*xorqi_ext<mode>_1_cc): Ditto.
(*negqi_ext<mode>_2): Ditto.
(*ashlqi_ext<mode>_2): Ditto.
(*<any_shiftrt:insn>qi_ext<mode>_2): Ditto.
2023-02-15 Uroš Bizjak <ubizjak@gmail.com>
* config/i386/predicates.md (int248_register_operand):
Rename from extr_register_operand.
* config/i386/i386.md (*extv<mode>): Update for renamed predicate.
(*extzx<mode>): Ditto.
(*ashl<dwi>3_doubleword_mask): Use int248_register_operand predicate.
(*ashl<mode>3_mask): Ditto.
(*<any_shiftrt:insn><mode>3_mask): Ditto.
(*<any_shiftrt:insn><dwi>3_doubleword_mask): Ditto.
(*<any_rotate:insn><mode>3_mask): Ditto.
(*<btsc><mode>_mask): Ditto.
(*btr<mode>_mask): Ditto.
(*jcc_bt<mode>_mask_1): Ditto.
2023-02-15 Richard Biener <rguenther@suse.de>
PR middle-end/26854
* df-core.cc (df_worklist_propagate_forward): Put later
blocks on worklist and only earlier blocks on pending.
(df_worklist_propagate_backward): Likewise.
(df_worklist_dataflow_doublequeue): Change the iteration
to process new blocks in the same iteration if that
maintains the iteration order.
2023-02-15 Marek Polacek <polacek@redhat.com>
PR middle-end/106080
* gimple-ssa-warn-access.cc (is_auto_decl): Remove. Use auto_var_p
instead.
2023-02-15 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/predicates.md: Refine codes.
* config/riscv/riscv-protos.h (RVV_VUNDEF): New macro.
* config/riscv/riscv-v.cc: Refine codes.
* config/riscv/riscv-vector-builtins-bases.cc (enum ternop_type): New
enum.
(class imac): New class.
(enum widen_ternop_type): New enum.
(class iwmac): New class.
(BASE): New class.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def (vmacc): Ditto.
(vnmsac): Ditto.
(vmadd): Ditto.
(vnmsub): Ditto.
(vwmacc): Ditto.
(vwmaccu): Ditto.
(vwmaccsu): Ditto.
(vwmaccus): Ditto.
* config/riscv/riscv-vector-builtins.cc
(function_builder::apply_predication): Adjust for multiply-add support.
(function_expander::add_vundef_operand): Refine codes.
(function_expander::use_ternop_insn): New function.
(function_expander::use_widen_ternop_insn): Ditto.
* config/riscv/riscv-vector-builtins.h: New function.
* config/riscv/vector.md (@pred_mul_<optab><mode>): New pattern.
(pred_mul_<optab><mode>_undef_merge): Ditto.
(*pred_<madd_nmsub><mode>): Ditto.
(*pred_<macc_nmsac><mode>): Ditto.
(*pred_mul_<optab><mode>): Ditto.
(@pred_mul_<optab><mode>_scalar): Ditto.
(*pred_mul_<optab><mode>_undef_merge_scalar): Ditto.
(*pred_<madd_nmsub><mode>_scalar): Ditto.
(*pred_<macc_nmsac><mode>_scalar): Ditto.
(*pred_mul_<optab><mode>_scalar): Ditto.
(*pred_mul_<optab><mode>_undef_merge_extended_scalar): Ditto.
(*pred_<madd_nmsub><mode>_extended_scalar): Ditto.
(*pred_<macc_nmsac><mode>_extended_scalar): Ditto.
(*pred_mul_<optab><mode>_extended_scalar): Ditto.
(@pred_widen_mul_plus<su><mode>): Ditto.
(@pred_widen_mul_plus<su><mode>_scalar): Ditto.
(@pred_widen_mul_plussu<mode>): Ditto.
(@pred_widen_mul_plussu<mode>_scalar): Ditto.
(@pred_widen_mul_plusus<mode>_scalar): Ditto.
2023-02-15 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/predicates.md (vector_mask_operand): Refine the codes.
(vector_all_trues_mask_operand): New predicate.
(vector_undef_operand): New predicate.
(ltge_operator): New predicate.
(comparison_except_ltge_operator): New predicate.
(comparison_except_eqge_operator): New predicate.
(ge_operator): New predicate.
* config/riscv/riscv-v.cc (has_vi_variant_p): Add compare support.
* config/riscv/riscv-vector-builtins-bases.cc (class icmp): New class.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def (vmseq): Ditto.
(vmsne): Ditto.
(vmslt): Ditto.
(vmsgt): Ditto.
(vmsle): Ditto.
(vmsge): Ditto.
(vmsltu): Ditto.
(vmsgtu): Ditto.
(vmsleu): Ditto.
(vmsgeu): Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc
(struct return_mask_def): Adjust for compare support.
* config/riscv/riscv-vector-builtins.cc
(function_expander::use_compare_insn): New function.
* config/riscv/riscv-vector-builtins.h
(function_expander::add_integer_operand): Ditto.
* config/riscv/riscv.cc (riscv_print_operand): Add compare support.
* config/riscv/riscv.md: Add vector min/max attributes.
* config/riscv/vector-iterators.md (xnor): New iterator.
* config/riscv/vector.md (@pred_cmp<mode>): New pattern.
(*pred_cmp<mode>): Ditto.
(*pred_cmp<mode>_narrow): Ditto.
(@pred_ltge<mode>): Ditto.
(*pred_ltge<mode>): Ditto.
(*pred_ltge<mode>_narrow): Ditto.
(@pred_cmp<mode>_scalar): Ditto.
(*pred_cmp<mode>_scalar): Ditto.
(*pred_cmp<mode>_scalar_narrow): Ditto.
(@pred_eqne<mode>_scalar): Ditto.
(*pred_eqne<mode>_scalar): Ditto.
(*pred_eqne<mode>_scalar_narrow): Ditto.
(*pred_cmp<mode>_extended_scalar): Ditto.
(*pred_cmp<mode>_extended_scalar_narrow): Ditto.
(*pred_eqne<mode>_extended_scalar): Ditto.
(*pred_eqne<mode>_extended_scalar_narrow): Ditto.
(@pred_ge<mode>_scalar): Ditto.
(@pred_<optab><mode>): Ditto.
(@pred_n<optab><mode>): Ditto.
(@pred_<optab>n<mode>): Ditto.
(@pred_not<mode>): Ditto.
2023-02-15 Martin Jambor <mjambor@suse.cz>
PR ipa/108679
* ipa-sra.cc (push_param_adjustments_for_index): Do not omit
creation of non-scalar replacements even if IPA-CP knows their
contents.
2023-02-15 Jakub Jelinek <jakub@redhat.com>
PR target/108787
PR target/103109
* config/rs6000/rs6000.md (<u>maddditi4): Change into umaddditi4 only
expander, change operand 3 to be TImode, emit maddlddi4 and
umadddi4_highpart{,_le} with its low half and finally add the high
half to the result.
2023-02-15 Martin Liska <mliska@suse.cz>
* doc/invoke.texi: Document --param=asan-kernel-mem-intrinsic-prefix.
2023-02-15 Richard Biener <rguenther@suse.de>
* sanopt.cc (sanitize_asan_mark_unpoison): Use bitmap
for with_poison and alias worklist to it.
(sanitize_asan_mark_poison): Likewise.
2023-02-15 Richard Biener <rguenther@suse.de>
PR target/108738
* config/i386/i386-features.cc (scalar_chain::add_to_queue):
Combine bitmap test and set.
(scalar_chain::add_insn): Likewise.
(scalar_chain::analyze_register_chain): Remove redundant
attempt to add to queue and instead strengthen assert.
Sink common attempts to mark the def dual-mode.
(scalar_chain::add_to_queue): Remove redundant insn bitmap
check.
2023-02-15 Richard Biener <rguenther@suse.de>
PR target/108738
* config/i386/i386-features.cc (convert_scalars_to_vector):
Switch candidates bitmaps to tree view before building the chains.
2023-02-15 Hans-Peter Nilsson <hp@axis.com>
* reload1.cc (gen_reload): Correct rtx parameter for fatal_insn
"failure trying to reload" call.
2023-02-15 Hans-Peter Nilsson <hp@axis.com>
* gdbinit.in (phrs): New command.
* sel-sched-dump.cc (debug_hard_reg_set): Remove debug-function.
* ira-color.cc (debug_hard_reg_set): New, calling print_hard_reg_set.
2023-02-14 David Faust <david.faust@oracle.com>
PR target/108790
* config/bpf/constraints.md (q): New memory constraint.
* config/bpf/bpf.md (zero_extendhidi2): Use it here.
(zero_extendqidi2): Likewise.
(zero_extendsidi2): Likewise.
(*mov<MM:mode>): Likewise.
2023-02-14 Andrew Pinski <apinski@marvell.com>
PR tree-optimization/108355
PR tree-optimization/96921
* match.pd: Add pattern for "1 - bool_val".
2023-02-14 Richard Biener <rguenther@suse.de>
* tree-ssa-sccvn.cc (vn_phi_compute_hash): Key skipping
basic block index hashing on the availability of ->cclhs.
(vn_phi_eq): Avoid re-doing sanity checks for CSE but
rely on ->cclhs availability.
(vn_phi_lookup): Set ->cclhs only when we are eventually
going to CSE the PHI.
(vn_phi_insert): Likewise.
2023-02-14 Eric Botcazou <ebotcazou@adacore.com>
* gimplify.cc (gimplify_save_expr): Add missing guard.
2023-02-14 Richard Biener <rguenther@suse.de>
PR tree-optimization/108782
* tree-vect-loop.cc (vect_phi_first_order_recurrence_p):
Make sure we're not vectorizing an inner loop.
2023-02-14 Jakub Jelinek <jakub@redhat.com>
PR sanitizer/108777
* params.opt (-param=asan-kernel-mem-intrinsic-prefix=): New param.
* asan.h (asan_memfn_rtl): Declare.
* asan.cc (asan_memfn_rtls): New variable.
(asan_memfn_rtl): New function.
* builtins.cc (expand_builtin): If
param_asan_kernel_mem_intrinsic_prefix and function is
kernel-{,hw}address sanitized, emit calls to
__{,hw}asan_{memcpy,memmove,memset} rather than
{memcpy,memmove,memset}. Use sanitize_flags_p (SANITIZE_ADDRESS)
instead of flag_sanitize & SANITIZE_ADDRESS to check if
asan_intercepted_p functions shouldn't be expanded inline.
2023-02-14 Richard Sandiford <richard.sandiford@arm.com>
PR tree-optimization/96373
* tree-vect-stmts.cc (vectorizable_operation): Predicate trapping
operations on the loop mask. Reject partial vectors if this isn't
possible.
2023-02-13 Richard Sandiford <richard.sandiford@arm.com>
PR rtl-optimization/108681
* lra-spills.cc (lra_final_code_change): Extend subreg replacement
code to handle bare uses and clobbers.
2023-02-13 Vladimir N. Makarov <vmakarov@redhat.com>
* ira.cc (ira_update_equiv_info_by_shuffle_insn): Clear equiv
caller_save_p flag when clearing defined_p flag.
(setup_reg_equiv): Ditto.
* lra-constraints.cc (lra_constraints): Ditto.
2023-02-13 Uroš Bizjak <ubizjak@gmail.com>
PR target/108516
* config/i386/predicates.md (extr_register_operand):
New special predicate.
* config/i386/i386.md (*extv<mode>): Use extr_register_operand
as operand 1 predicate.
(*exzv<mode>): Ditto.
(*extendqi<SWI24:mode>_ext_1): New insn pattern.
2023-02-13 Richard Biener <rguenther@suse.de>
PR tree-optimization/28614
* tree-ssa-sccvn.cc (can_track_predicate_on_edge): Avoid
walking all edges in most cases.
(vn_nary_op_insert_pieces_predicated): Avoid repeated
calls to can_track_predicate_on_edge unless checking is
enabled.
(process_bb): Instead call it once here for each edge
we register possibly multiple predicates on.
2023-02-13 Richard Biener <rguenther@suse.de>
PR tree-optimization/108691
* tree-cfg.cc (notice_special_calls): When the CFG is built
honor gimple_call_ctrl_altering_p.
* cfgexpand.cc (expand_call_stmt): Clear cfun->calls_setjmp
temporarily if the call is not control-altering.
* calls.cc (emit_call_1): Do not add REG_SETJMP if
cfun->calls_setjmp is not set. Do not alter cfun->calls_setjmp.
2023-02-13 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
PR target/108102
* config/s390/s390.cc (s390_bb_fallthru_entry_likely): Remove.
(struct s390_sched_state): Initialise to zero.
(s390_sched_variable_issue): For better debuggability also emit
the current side.
(s390_sched_init): Unconditionally reset scheduler state.
2023-02-13 Richard Sandiford <richard.sandiford@arm.com>
* ifcvt.h (noce_if_info::cond_inverted): New field.
* ifcvt.cc (cond_move_convert_if_block): Swap the then and else
values when cond_inverted is true.
(noce_find_if_block): Allow the condition to be inverted when
handling conditional moves.
2023-02-13 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
* config/s390/predicates.md (execute_operation): Use
constrain_operands instead of extract_constrain_insn in order to
determine wheter there exists a valid alternative.
2023-02-13 Claudiu Zissulescu <claziss@gmail.com>
* common/config/arc/arc-common.cc (arc_option_optimization_table):
Remove millicode from list.
2023-02-13 Martin Liska <mliska@suse.cz>
* doc/invoke.texi: Document ira-simple-lra-insn-threshold.
2023-02-13 Richard Biener <rguenther@suse.de>
PR tree-optimization/106722
* tree-ssa-dce.cc (mark_last_stmt_necessary): Return
whether we marked a stmt.
(mark_control_dependent_edges_necessary): When
mark_last_stmt_necessary didn't mark any stmt make sure
to mark its control dependent edges.
(propagate_necessity): Likewise.
2023-02-13 Kito Cheng <kito.cheng@sifive.com>
* config/riscv/riscv.h (RISCV_DWARF_VLENB): New.
(DWARF_FRAME_REGISTERS): New.
(DWARF_REG_TO_UNWIND_COLUMN): New.
2023-02-12 Gerald Pfeifer <gerald@pfeifer.com>
* doc/sourcebuild.texi: Remove (broken) direct reference to
"The GNU configure and build system".
2023-02-12 Jin Ma <jinma@linux.alibaba.com>
* config/riscv/riscv.cc (riscv_adjust_libcall_cfi_prologue): Change
gen_add3_insn to gen_rtx_SET.
(riscv_adjust_libcall_cfi_epilogue): Likewise.
2023-02-12 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vector-builtins-bases.cc (class sat_op): New class.
(class vnclip): Ditto.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def (vaadd): Ditto.
(vasub): Ditto.
(vaaddu): Ditto.
(vasubu): Ditto.
(vsmul): Ditto.
(vssra): Ditto.
(vssrl): Ditto.
(vnclipu): Ditto.
(vnclip): Ditto.
* config/riscv/vector-iterators.md (su): Add instruction.
(aadd): Ditto.
(vaalu): Ditto.
* config/riscv/vector.md (@pred_<sat_op><mode>): New pattern.
(@pred_<sat_op><mode>_scalar): Ditto.
(*pred_<sat_op><mode>_scalar): Ditto.
(*pred_<sat_op><mode>_extended_scalar): Ditto.
(@pred_narrow_clip<v_su><mode>): Ditto.
(@pred_narrow_clip<v_su><mode>_scalar): Ditto.
2023-02-12 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/constraints.md (Wbr): Remove unused constraint.
* config/riscv/predicates.md: Fix move operand predicate.
* config/riscv/riscv-vector-builtins-bases.cc (class vnshift): New class.
(class vncvt_x): Ditto.
(class vmerge): Ditto.
(class vmv_v): Ditto.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def (vsra): Ditto.
(vsrl): Ditto.
(vnsrl): Ditto.
(vnsra): Ditto.
(vncvt_x): Ditto.
(vmerge): Ditto.
(vmv_v): Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc (struct narrow_alu_def): Ditto.
(struct move_def): Ditto.
(SHAPE): Ditto.
* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_WEXTI_OPS): New variable.
(DEF_RVV_WEXTU_OPS): Ditto
* config/riscv/riscv-vector-builtins.def (x_x_w): Fix type for suffix.
(v_v): Ditto.
(v_x): Ditto.
(x_w): Ditto.
(x): Ditto.
* config/riscv/riscv.cc (riscv_print_operand): Refine ASM printting rule.
* config/riscv/vector-iterators.md (nmsac):New iterator.
(nmsub): New iterator.
* config/riscv/vector.md (@pred_merge<mode>): New pattern.
(@pred_merge<mode>_scalar): New pattern.
(*pred_merge<mode>_scalar): New pattern.
(*pred_merge<mode>_extended_scalar): New pattern.
(@pred_narrow_<optab><mode>): New pattern.
(@pred_narrow_<optab><mode>_scalar): New pattern.
(@pred_trunc<mode>): New pattern.
2023-02-12 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vector-builtins-bases.cc (class vmadc): New class.
(class vmsbc): Ditto.
(BASE): Define new class.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def (vmadc): New define.
(vmsbc): Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc (struct return_mask_def):
New class.
(SHAPE): Ditto.
* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
* config/riscv/riscv-vector-builtins.cc
(function_expander::use_exact_insn): Adjust for new support
* config/riscv/riscv-vector-builtins.h
(function_base::has_merge_operand_p): New function.
* config/riscv/vector-iterators.md: New iterator.
* config/riscv/vector.md (@pred_madc<mode>): New pattern.
(@pred_msbc<mode>): Ditto.
(@pred_madc<mode>_scalar): Ditto.
(@pred_msbc<mode>_scalar): Ditto.
(*pred_madc<mode>_scalar): Ditto.
(*pred_madc<mode>_extended_scalar): Ditto.
(*pred_msbc<mode>_scalar): Ditto.
(*pred_msbc<mode>_extended_scalar): Ditto.
(@pred_madc<mode>_overflow): Ditto.
(@pred_msbc<mode>_overflow): Ditto.
(@pred_madc<mode>_overflow_scalar): Ditto.
(@pred_msbc<mode>_overflow_scalar): Ditto.
(*pred_madc<mode>_overflow_scalar): Ditto.
(*pred_madc<mode>_overflow_extended_scalar): Ditto.
(*pred_msbc<mode>_overflow_scalar): Ditto.
(*pred_msbc<mode>_overflow_extended_scalar): Ditto.
2023-02-12 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-protos.h (simm5_p): Add vadc/vsbc support.
* config/riscv/riscv-v.cc (simm32_p): Ditto.
* config/riscv/riscv-vector-builtins-bases.cc (class vadc): New class.
(class vsbc): Ditto.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def (vadc): Ditto.
(vsbc): Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc
(struct no_mask_policy_def): Ditto.
(SHAPE): Ditto.
* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
* config/riscv/riscv-vector-builtins.cc
(rvv_arg_type_info::get_base_vector_type): Add vadc/vsbc support.
(rvv_arg_type_info::get_tree_type): Ditto.
(function_expander::use_exact_insn): Ditto.
* config/riscv/riscv-vector-builtins.h (enum rvv_base_type): Ditto.
(function_base::use_mask_predication_p): New function.
* config/riscv/vector-iterators.md: New iterator.
* config/riscv/vector.md (@pred_adc<mode>): New pattern.
(@pred_sbc<mode>): Ditto.
(@pred_adc<mode>_scalar): Ditto.
(@pred_sbc<mode>_scalar): Ditto.
(*pred_adc<mode>_scalar): Ditto.
(*pred_adc<mode>_extended_scalar): Ditto.
(*pred_sbc<mode>_scalar): Ditto.
(*pred_sbc<mode>_extended_scalar): Ditto.
2023-02-12 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/vector.md: use "zero" reg.
2023-02-12 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vector-builtins-bases.cc (class widen_binop): New
class.
(class vwmulsu): Ditto.
(class vwcvt): Ditto.
(BASE): Add integer widening support.
* config/riscv/riscv-vector-builtins-bases.h: Ditto
* config/riscv/riscv-vector-builtins-functions.def (vwadd): New class.
(vwsub): New class.
(vwmul): New class.
(vwmulu): New class.
(vwmulsu): New class.
(vwaddu): New class.
(vwsubu): New class.
(vwcvt_x): New class.
(vwcvtu_x): New class.
* config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): New
class.
(struct widen_alu_def): New class.
(SHAPE): New class.
* config/riscv/riscv-vector-builtins-shapes.h: New class.
* config/riscv/riscv-vector-builtins.cc
(rvv_arg_type_info::get_base_vector_type): Add integer widening support.
(rvv_arg_type_info::get_tree_type): Ditto.
* config/riscv/riscv-vector-builtins.def (x_x_v): Change into "x_v"
(x_v): Ditto.
* config/riscv/riscv-vector-builtins.h (enum rvv_base_type): Add integer
widening support.
* config/riscv/riscv-vsetvl.cc (change_insn): Fix reg_equal use bug.
* config/riscv/riscv.h (X0_REGNUM): New constant.
* config/riscv/vector-iterators.md: New iterators.
* config/riscv/vector.md
(@pred_dual_widen_<any_widen_binop:optab><any_extend:su><mode>): New
pattern.
(@pred_dual_widen_<any_widen_binop:optab><any_extend:su><mode>_scalar):
Ditto.
(@pred_single_widen_<plus_minus:optab><any_extend:su><mode>): Ditto.
(@pred_single_widen_<plus_minus:optab><any_extend:su><mode>_scalar):
Ditto.
(@pred_widen_mulsu<mode>): Ditto.
(@pred_widen_mulsu<mode>_scalar): Ditto.
(@pred_<optab><mode>): Ditto.
2023-02-12 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
kito-cheng <kito.cheng@sifive.com>
* common/config/riscv/riscv-common.cc: Add flag for 'V' extension.
* config/riscv/riscv-vector-builtins-bases.cc (class vmulh): New class.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def (vmulh): Add vmulh
API support.
(vmulhu): Ditto.
(vmulhsu): Ditto.
* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_FULL_V_I_OPS):
New macro.
(DEF_RVV_FULL_V_U_OPS): Ditto.
(vint8mf8_t): Ditto.
(vint8mf4_t): Ditto.
(vint8mf2_t): Ditto.
(vint8m1_t): Ditto.
(vint8m2_t): Ditto.
(vint8m4_t): Ditto.
(vint8m8_t): Ditto.
(vint16mf4_t): Ditto.
(vint16mf2_t): Ditto.
(vint16m1_t): Ditto.
(vint16m2_t): Ditto.
(vint16m4_t): Ditto.
(vint16m8_t): Ditto.
(vint32mf2_t): Ditto.
(vint32m1_t): Ditto.
(vint32m2_t): Ditto.
(vint32m4_t): Ditto.
(vint32m8_t): Ditto.
(vint64m1_t): Ditto.
(vint64m2_t): Ditto.
(vint64m4_t): Ditto.
(vint64m8_t): Ditto.
(vuint8mf8_t): Ditto.
(vuint8mf4_t): Ditto.
(vuint8mf2_t): Ditto.
(vuint8m1_t): Ditto.
(vuint8m2_t): Ditto.
(vuint8m4_t): Ditto.
(vuint8m8_t): Ditto.
(vuint16mf4_t): Ditto.
(vuint16mf2_t): Ditto.
(vuint16m1_t): Ditto.
(vuint16m2_t): Ditto.
(vuint16m4_t): Ditto.
(vuint16m8_t): Ditto.
(vuint32mf2_t): Ditto.
(vuint32m1_t): Ditto.
(vuint32m2_t): Ditto.
(vuint32m4_t): Ditto.
(vuint32m8_t): Ditto.
(vuint64m1_t): Ditto.
(vuint64m2_t): Ditto.
(vuint64m4_t): Ditto.
(vuint64m8_t): Ditto.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_FULL_V_I_OPS): Ditto.
(DEF_RVV_FULL_V_U_OPS): Ditto.
(check_required_extensions): Add vmulh support.
(rvv_arg_type_info::get_tree_type): Ditto.
* config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_FULL_V): Ditto.
(enum rvv_base_type): Ditto.
* config/riscv/riscv.opt: Add 'V' extension flag.
* config/riscv/vector-iterators.md (su): New iterator.
* config/riscv/vector.md (@pred_mulh<v_su><mode>): New pattern.
(@pred_mulh<v_su><mode>_scalar): Ditto.
(*pred_mulh<v_su><mode>_scalar): Ditto.
(*pred_mulh<v_su><mode>_extended_scalar): Ditto.
2023-02-12 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/iterators.md: Add sign_extend/zero_extend.
* config/riscv/riscv-vector-builtins-bases.cc (class ext): New class.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Add vsext/vzext support.
* config/riscv/riscv-vector-builtins-functions.def (vsext): New macro
define.
(vzext): Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): Adjust
for vsext/vzext support.
* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_WEXTI_OPS): New
macro define.
(DEF_RVV_QEXTI_OPS): Ditto.
(DEF_RVV_OEXTI_OPS): Ditto.
(DEF_RVV_WEXTU_OPS): Ditto.
(DEF_RVV_QEXTU_OPS): Ditto.
(DEF_RVV_OEXTU_OPS): Ditto.
(vint16mf4_t): Ditto.
(vint16mf2_t): Ditto.
(vint16m1_t): Ditto.
(vint16m2_t): Ditto.
(vint16m4_t): Ditto.
(vint16m8_t): Ditto.
(vint32mf2_t): Ditto.
(vint32m1_t): Ditto.
(vint32m2_t): Ditto.
(vint32m4_t): Ditto.
(vint32m8_t): Ditto.
(vint64m1_t): Ditto.
(vint64m2_t): Ditto.
(vint64m4_t): Ditto.
(vint64m8_t): Ditto.
(vuint16mf4_t): Ditto.
(vuint16mf2_t): Ditto.
(vuint16m1_t): Ditto.
(vuint16m2_t): Ditto.
(vuint16m4_t): Ditto.
(vuint16m8_t): Ditto.
(vuint32mf2_t): Ditto.
(vuint32m1_t): Ditto.
(vuint32m2_t): Ditto.
(vuint32m4_t): Ditto.
(vuint32m8_t): Ditto.
(vuint64m1_t): Ditto.
(vuint64m2_t): Ditto.
(vuint64m4_t): Ditto.
(vuint64m8_t): Ditto.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_WEXTI_OPS): Ditto.
(DEF_RVV_QEXTI_OPS): Ditto.
(DEF_RVV_OEXTI_OPS): Ditto.
(DEF_RVV_WEXTU_OPS): Ditto.
(DEF_RVV_QEXTU_OPS): Ditto.
(DEF_RVV_OEXTU_OPS): Ditto.
(rvv_arg_type_info::get_base_vector_type): Add sign_exted/zero_extend
support.
(rvv_arg_type_info::get_tree_type): Ditto.
* config/riscv/riscv-vector-builtins.h (enum rvv_base_type): Ditto.
* config/riscv/vector-iterators.md (z): New attribute.
* config/riscv/vector.md (@pred_<optab><mode>_vf2): New pattern.
(@pred_<optab><mode>_vf4): Ditto.
(@pred_<optab><mode>_vf8): Ditto.
2023-02-12 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/iterators.md: Add saturating Addition && Subtraction.
* config/riscv/riscv-v.cc (has_vi_variant_p): Ditto.
* config/riscv/riscv-vector-builtins-bases.cc (BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def (vsadd): New def.
(vssub): Ditto.
(vsaddu): Ditto.
(vssubu): Ditto.
* config/riscv/vector-iterators.md (sll.vi): Adjust for Saturating
support.
(sll.vv): Ditto.
(%3,%v4): Ditto.
(%3,%4): Ditto.
* config/riscv/vector.md (@pred_<optab><mode>): New pattern.
(@pred_<optab><mode>_scalar): New pattern.
(*pred_<optab><mode>_scalar): New pattern.
(*pred_<optab><mode>_extended_scalar): New pattern.
2023-02-12 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/iterators.md: Add neg and not.
* config/riscv/riscv-vector-builtins-bases.cc (class unop): New class.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def (vadd): Rename binop
into alu.
(vsub): Ditto.
(vand): Ditto.
(vor): Ditto.
(vxor): Ditto.
(vsll): Ditto.
(vsra): Ditto.
(vsrl): Ditto.
(vmin): Ditto.
(vmax): Ditto.
(vminu): Ditto.
(vmaxu): Ditto.
(vmul): Ditto.
(vdiv): Ditto.
(vrem): Ditto.
(vdivu): Ditto.
(vremu): Ditto.
(vrsub): Ditto.
(vneg): Ditto.
(vnot): Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc (struct binop_def): Ditto.
(struct alu_def): Ditto.
(SHAPE): Ditto.
* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
* config/riscv/riscv-vector-builtins.cc: Support unary C/C/++.
* config/riscv/vector-iterators.md: New iterator.
* config/riscv/vector.md (@pred_<optab><mode>): New pattern
2023-02-12 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vsetvl.cc (pass_vsetvl::compute_probabilities): Skip exit block.
2023-02-11 Jakub Jelinek <jakub@redhat.com>
PR ipa/108605
* ipa-cp.cc (ipa_agg_value_from_jfunc): Return NULL_TREE also if
item->offset bit position is too large to be representable as
unsigned int byte position.
2023-02-11 Gerald Pfeifer <gerald@pfeifer.com>
* doc/extend.texi (Other Builtins): Adjust link to WG14 N965.
2023-02-10 Vladimir N. Makarov <vmakarov@redhat.com>
* ira.cc (update_equiv_regs): Set up ira_reg_equiv for
valid_combine only when ira_use_lra_p is true.
2023-02-10 Vladimir N. Makarov <vmakarov@redhat.com>
* params.opt (ira-simple-lra-insn-threshold): Add new param.
* ira.cc (ira): Use the param to switch on simple LRA.
2023-02-10 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/108687
* gimple-range-cache.cc (ranger_cache::range_on_edge): Revert
back to RFD_NONE mode for calculations.
(ranger_cache::propagate_cache): Call the internal edge range API
with RFD_READ_ONLY instead of changing the external routine.
2023-02-10 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/108520
* gimple-range-infer.cc (check_assume_func): Invoke
gimple_range_global directly instead using global_range_query.
* value-query.cc (get_range_global): Add function context and
avoid calling nonnull_arg_p if not cfun.
(gimple_range_global): Add function context pointer.
* value-query.h (imple_range_global): Add function context.
2023-02-10 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/constraints.md (Wdm): Adjust constraint.
(Wbr): New constraint.
* config/riscv/predicates.md (reg_or_int_operand): New predicate.
* config/riscv/riscv-protos.h (emit_pred_op): Remove function.
(emit_vlmax_op): New function.
(emit_nonvlmax_op): Ditto.
(simm32_p): Ditto.
(neg_simm5_p): Ditto.
(has_vi_variant_p): Ditto.
* config/riscv/riscv-v.cc (emit_pred_op): Adjust function.
(emit_vlmax_op): New function.
(emit_nonvlmax_op): Ditto.
(expand_const_vector): Adjust function.
(legitimize_move): Ditto.
(simm32_p): New function.
(simm5_p): Ditto.
(neg_simm5_p): Ditto.
(has_vi_variant_p): Ditto.
* config/riscv/riscv-vector-builtins-bases.cc (class vrsub): New class.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def (vmin): Remove
unsigned cases.
(vmax): Ditto.
(vminu): Remove signed cases.
(vmaxu): Ditto.
(vdiv): Remove unsigned cases.
(vrem): Ditto.
(vdivu): Remove signed cases.
(vremu): Ditto.
(vadd): Adjust.
(vsub): Ditto.
(vrsub): New class.
(vand): Adjust.
(vor): Ditto.
(vxor): Ditto.
(vmul): Ditto.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_U_OPS): New macro.
* config/riscv/riscv.h: change VL/VTYPE as fixed reg.
* config/riscv/vector-iterators.md: New iterators.
* config/riscv/vector.md (@pred_broadcast<mode>): Adjust pattern for vx
support.
(@pred_<optab><mode>_scalar): New pattern.
(@pred_sub<mode>_reverse_scalar): Ditto.
(*pred_<optab><mode>_scalar): Ditto.
(*pred_<optab><mode>_extended_scalar): Ditto.
(*pred_sub<mode>_reverse_scalar): Ditto.
(*pred_sub<mode>_extended_reverse_scalar): Ditto.
2023-02-10 Richard Biener <rguenther@suse.de>
PR tree-optimization/108724
* tree-vect-stmts.cc (vectorizable_operation): Avoid
using word_mode vectors when vector lowering will
decompose them to elementwise operations.
2023-02-10 Jakub Jelinek <jakub@redhat.com>
Revert:
2023-02-09 Martin Liska <mliska@suse.cz>
PR target/100758
* doc/extend.texi: Document that the function
does not work correctly for old VIA processors.
2023-02-10 Andrew Pinski <apinski@marvell.com>
Andrew Macleod <amacleod@redhat.com>
PR tree-optimization/108684
* tree-ssa-dce.cc (simple_dce_from_worklist):
Check all ssa names and not just non-vdef ones
before accepting the inline-asm.
Call unlink_stmt_vdef on the statement before
removing it.
2023-02-09 Vladimir N. Makarov <vmakarov@redhat.com>
* ira.h (struct ira_reg_equiv_s): Add new field caller_save_p.
* ira.cc (validate_equiv_mem): Check memref address variance.
(no_equiv): Clear caller_save_p flag.
(update_equiv_regs): Define caller save equivalence for
valid_combine.
(setup_reg_equiv): Clear defined_p flag for caller save equivalence.
* lra-constraints.cc (lra_copy_reg_equiv): Add new arg
call_save_p. Use caller save equivalence depending on the arg.
(split_reg): Adjust the call.
2023-02-09 Jakub Jelinek <jakub@redhat.com>
PR target/100758
* common/config/i386/cpuinfo.h (get_zhaoxin_cpu): Formatting fixes.
(cpu_indicator_init): Call get_available_features for all CPUs with
max_level >= 1, rather than just Intel, AMD or Zhaoxin. Formatting
fixes.
2023-02-09 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/108688
* match.pd (bit_field_ref [bit_insert]): Simplify BIT_FIELD_REF
of BIT_INSERT_EXPR extracting exactly all inserted bits even
when without mode precision. Formatting fixes.
2023-02-09 Andrew Pinski <apinski@marvell.com>
PR tree-optimization/108688
* match.pd (bit_field_ref [bit_insert]): Avoid generating
BIT_FIELD_REFs of non-mode-precision integral operands.
2023-02-09 Martin Liska <mliska@suse.cz>
PR target/100758
* doc/extend.texi: Document that the function
does not work correctly for old VIA processors.
2023-02-09 Andreas Schwab <schwab@suse.de>
* lto-wrapper.cc (merge_and_complain): Handle
-funwind-tables and -fasynchronous-unwind-tables.
(append_compiler_options): Likewise.
2023-02-09 Richard Biener <rguenther@suse.de>
PR tree-optimization/26854
* tree-into-ssa.cc (update_ssa): Turn blocks_to_update to tree
view around insert_updated_phi_nodes_for.
* tree-ssa-alias.cc (maybe_skip_until): Allocate visited bitmap
in tree view.
(walk_aliased_vdefs_1): Likewise.
2023-02-08 Gerald Pfeifer <gerald@pfeifer.com>
* doc/include/gpl_v3.texi: Change fsf.org to www.fsf.org.
2023-02-08 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
PR target/108505
* config.gcc (tm_mlib_file): Define new variable.
2023-02-08 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/108692
* tree-vect-patterns.cc (vect_widened_op_tree): If rhs_code is
widened_code which is different from code, don't call
vect_look_through_possible_promotion but instead just check op is
SSA_NAME with integral type for which vect_is_simple_use is true
and call set_op on this_unprom.
2023-02-08 Andrea Corallo <andrea.corallo@arm.com>
* config/aarch64/aarch64-protos.h (aarch_ra_sign_key): Remove
declaration.
* config/aarch64/aarch64.cc (aarch_ra_sign_key): Remove
definition.
* config/aarch64/aarch64.opt (aarch64_ra_sign_key): Rename
to 'aarch_ra_sign_key'.
* config/arm/aarch-common.cc (aarch_ra_sign_key): Remove
declaration.
* config/arm/arm-protos.h (aarch_ra_sign_key): Likewise.
* config/arm/arm.cc (enum aarch_key_type): Remove definition.
* config/arm/arm.opt: Define.
2023-02-08 Richard Sandiford <richard.sandiford@arm.com>
PR tree-optimization/108316
* tree-vect-stmts.cc (get_load_store_type): When using
internal functions for gather/scatter, make sure that the type
of the offset argument is consistent with the offset vector type.
2023-02-08 Vladimir N. Makarov <vmakarov@redhat.com>
Revert:
2023-02-07 Vladimir N. Makarov <vmakarov@redhat.com>
* ira.h (struct ira_reg_equiv_s): Add new field caller_save_p.
* ira.cc (validate_equiv_mem): Check memref address variance.
(update_equiv_regs): Define caller save equivalence for
valid_combine.
(setup_reg_equiv): Clear defined_p flag for caller save equivalence.
* lra-constraints.cc (lra_copy_reg_equiv): Add new arg
call_save_p. Use caller save equivalence depending on the arg.
(split_reg): Adjust the call.
2023-02-08 Jakub Jelinek <jakub@redhat.com>
* tree.def (SAD_EXPR): Remove outdated comment about missing
WIDEN_MINUS_EXPR.
2023-02-07 Marek Polacek <polacek@redhat.com>
* doc/invoke.texi: Update -fchar8_t documentation.
2023-02-07 Vladimir N. Makarov <vmakarov@redhat.com>
* ira.h (struct ira_reg_equiv_s): Add new field caller_save_p.
* ira.cc (validate_equiv_mem): Check memref address variance.
(update_equiv_regs): Define caller save equivalence for
valid_combine.
(setup_reg_equiv): Clear defined_p flag for caller save equivalence.
* lra-constraints.cc (lra_copy_reg_equiv): Add new arg
call_save_p. Use caller save equivalence depending on the arg.
(split_reg): Adjust the call.
2023-02-07 Richard Biener <rguenther@suse.de>
PR tree-optimization/26854
* gimple-fold.cc (has_use_on_stmt): Look at stmt operands
instead of immediate uses.
2023-02-07 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/106923
* ipa-split.cc (execute_split_functions): Don't split returns_twice
functions.
2023-02-07 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/106433
* cgraph.cc (set_const_flag_1): Recurse on simd clones too.
(cgraph_node::set_pure_flag): Call set_pure_flag_1 on simd clones too.
2023-02-07 Jan Hubicka <jh@suse.cz>
* config/i386/x86-tune.def (X86_TUNE_AVX256_OPTIMAL): Turn off
for znver4.
2023-02-06 Andrew Stubbs <ams@codesourcery.com>
* config/gcn/mkoffload.cc (gcn_stack_size): New global variable.
(process_asm): Create a constructor for GCN_STACK_SIZE.
(main): Parse the -mstack-size option.
2023-02-06 Alex Coplan <alex.coplan@arm.com>
PR target/104921
* config/aarch64/aarch64-simd.md (aarch64_bfmlal<bt>_lane<q>v4sf):
Use correct constraint for operand 3.
2023-02-06 Martin Jambor <mjambor@suse.cz>
* ipa-sra.cc (adjust_parameter_descriptions): Fix a typo in a dump.
2023-02-06 Xi Ruoyao <xry111@xry111.site>
* config/loongarch/loongarch.md (bytepick_w_ashift_amount):
New define_int_iterator.
(bytepick_d_ashift_amount): Likewise.
(bytepick_imm): New define_int_attr.
(bytepick_w_lshiftrt_amount): Likewise.
(bytepick_d_lshiftrt_amount): Likewise.
(bytepick_w_<bytepick_imm>): New define_insn template.
(bytepick_w_<bytepick_imm>_extend): Likewise.
(bytepick_d_<bytepick_imm>): Likewise.
(bytepick_w): Remove unused define_insn.
(bytepick_d): Likewise.
(UNSPEC_BYTEPICK_W): Remove unused unspec.
(UNSPEC_BYTEPICK_D): Likewise.
* config/loongarch/predicates.md (const_0_to_3_operand):
Remove unused define_predicate.
(const_0_to_7_operand): Likewise.
2023-02-06 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/108655
* ubsan.cc (sanitize_unreachable_fn): For -funreachable-traps
or -fsanitize=unreachable -fsanitize-trap=unreachable return
BUILT_IN_UNREACHABLE_TRAP decl rather than BUILT_IN_TRAP.
2023-02-05 Gerald Pfeifer <gerald@pfeifer.com>
* doc/install.texi (Specific): Remove PW32.
2023-02-03 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/108647
* range-op.cc (operator_equal::op1_range,
operator_not_equal::op1_range): Don't test op2 bound
equality if op2.undefined_p (), instead set_varying.
(operator_lt::op1_range, operator_le::op1_range,
operator_gt::op1_range, operator_ge::op1_range): Return false if
op2.undefined_p ().
(operator_lt::op2_range, operator_le::op2_range,
operator_gt::op2_range, operator_ge::op2_range): Return false if
op1.undefined_p ().
2023-02-03 Aldy Hernandez <aldyh@redhat.com>
PR tree-optimization/108639
* value-range.cc (irange::legacy_equal_p): Compare nonzero bits as
widest_int.
(irange::operator==): Same.
2023-02-03 Aldy Hernandez <aldyh@redhat.com>
PR tree-optimization/108647
* range-op-float.cc (foperator_lt::op1_range): Handle undefined ranges.
(foperator_lt::op2_range): Same.
(foperator_le::op1_range): Same.
(foperator_le::op2_range): Same.
(foperator_gt::op1_range): Same.
(foperator_gt::op2_range): Same.
(foperator_ge::op1_range): Same.
(foperator_ge::op2_range): Same.
(foperator_unordered_lt::op1_range): Same.
(foperator_unordered_lt::op2_range): Same.
(foperator_unordered_le::op1_range): Same.
(foperator_unordered_le::op2_range): Same.
(foperator_unordered_gt::op1_range): Same.
(foperator_unordered_gt::op2_range): Same.
(foperator_unordered_ge::op1_range): Same.
(foperator_unordered_ge::op2_range): Same.
2023-02-03 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/107570
* tree-vrp.cc (remove_and_update_globals): Reset SCEV.
2023-02-03 Gaius Mulley <gaiusmod2@gmail.com>
* doc/gm2.texi (Internals): Remove from menu.
(Using): Comment out ifnohtml conditional.
(Documentation): Use gcc url.
(License): Node simplified.
(Copying): New node. Include gpl_v3_without_node.
(Contributing): Node simplified.
(Internals): Commented out.
(Libraries): Node simplified.
(Indices): Ditto.
(Contents): Ditto.
(Functions): Ditto.
2023-02-03 Christophe Lyon <christophe.lyon@arm.com>
* config/arm/mve.md (mve_vabavq_p_<supf><mode>): Add length
attribute.
(mve_vqshluq_m_n_s<mode>): Likewise.
(mve_vshlq_m_<supf><mode>): Likewise.
(mve_vsriq_m_n_<supf><mode>): Likewise.
(mve_vsubq_m_<supf><mode>): Likewise.
2023-02-03 Martin Jambor <mjambor@suse.cz>
PR ipa/108384
* ipa-sra.cc (push_param_adjustments_for_index): Remove a size check
when comparing to an IPA-CP value.
(dump_list_of_param_indices): New function.
(adjust_parameter_descriptions): Check for mismatching IPA-CP values.
Dump removed candidates using dump_list_of_param_indices.
* ipa-param-manipulation.cc
(ipa_param_body_adjustments::modify_expression): Add assert checking
sizes of a VIEW_CONVERT_EXPR will match.
(ipa_param_body_adjustments::modify_assignment): Likewise.
2023-02-03 Monk Chiang <monk.chiang@sifive.com>
* config/riscv/riscv.h: Remove VL_REGS, VTYPE_REGS class.
* config/riscv/riscv.cc: Ditto.
2023-02-03 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/vector-iterators.md (sll.vi): Fix constraint bug.
(sll.vv): Ditto.
(%3,%4): Ditto.
(%3,%v4): Ditto.
* config/riscv/vector.md: Ditto.
2023-02-03 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/predicates.md (pmode_reg_or_uimm5_operand): New predicate.
* config/riscv/riscv-vector-builtins-bases.cc: New class.
* config/riscv/riscv-vector-builtins-functions.def (vsll): Ditto.
(vsra): Ditto.
(vsrl): Ditto.
* config/riscv/riscv-vector-builtins.cc: Ditto.
* config/riscv/vector.md (@pred_<optab><mode>_scalar): New pattern.
2023-02-02 Iain Sandoe <iain@sandoe.co.uk>
* toplev.cc (toplev::main): Only print the version information header
from toplevel main().
2023-02-02 Paul-Antoine Arras <pa@codesourcery.com>
* config/gcn/gcn-valu.md (cond_<expander><mode>): Add
cond_{ashl|ashr|lshr}
2023-02-02 Richard Sandiford <richard.sandiford@arm.com>
PR rtl-optimization/108086
* rtl-ssa/insns.h (insn_info): Make m_num_defs a full unsigned int.
Adjust size-related commentary accordingly.
2023-02-02 Richard Sandiford <richard.sandiford@arm.com>
PR rtl-optimization/108508
* rtl-ssa/accesses.cc (function_info::split_clobber_group): When
the splay tree search gives the first clobber in the second group,
make sure that the root of the first clobber group is updated
correctly. Enter the new clobber group into the definition splay
tree.
2023-02-02 Jin Ma <jinma@linux.alibaba.com>
* common/config/riscv/riscv-common.cc (riscv_compute_multilib):
Fix finding best match score.
2023-02-02 Jakub Jelinek <jakub@redhat.com>
PR debug/106746
PR rtl-optimization/108463
PR target/108484
* cselib.cc (cselib_current_insn): Move declaration earlier.
(cselib_hasher::equal): For debug only locs, temporarily override
cselib_current_insn to their l->setting_insn for the
rtx_equal_for_cselib_1 call, so that unsuccessful comparisons don't
promote some debug locs.
* sched-deps.cc (sched_analyze_2) <case MEM>: For MEMs in DEBUG_INSNs
when using cselib call cselib_lookup_from_insn on the address but
don't substitute it.
2023-02-02 Richard Biener <rguenther@suse.de>
PR middle-end/108625
* genmatch.cc (expr::gen_transform): Also disallow resimplification
from pushing to lseq with force_leaf.
(dt_simplify::gen_1): Likewise.
2023-02-02 Andrew Stubbs <ams@codesourcery.com>
* config/gcn/gcn-run.cc: Include libgomp-gcn.h.
(struct kernargs): Replace the common content with kernargs_abi.
(struct heap): Delete.
(main): Read GCN_STACK_SIZE envvar.
Allocate space for the device stacks.
Write the new kernargs fields.
* config/gcn/gcn.cc (gcn_option_override): Remove stack_size_opt.
(default_requested_args): Remove PRIVATE_SEGMENT_BUFFER_ARG and
PRIVATE_SEGMENT_WAVE_OFFSET_ARG.
(gcn_addr_space_convert): Mask the QUEUE_PTR_ARG content.
(gcn_expand_prologue): Move the TARGET_PACKED_WORK_ITEMS to the top.
Set up the stacks from the values in the kernargs, not private.
(gcn_expand_builtin_1): Match the stack configuration in the prologue.
(gcn_hsa_declare_function_name): Turn off the private segment.
(gcn_conditional_register_usage): Ensure QUEUE_PTR is fixed.
* config/gcn/gcn.h (FIXED_REGISTERS): Fix the QUEUE_PTR register.
* config/gcn/gcn.opt (mstack-size): Change the description.
2023-02-02 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR target/108443
* config/arm/arm.h (VALID_MVE_PRED_MODE): Add V2QI.
* config/arm/arm.cc (thumb2_legitimate_address_p): Use HImode for
addressing MVE predicate modes.
(mve_bool_vec_to_const): Change to represent correct MVE predicate
format.
(arm_hard_regno_mode_ok): Use VALID_MVE_PRED_MODE instead of checking
modes.
(arm_vector_mode_supported_p): Likewise.
(arm_mode_to_pred_mode): Add V2QI.
* config/arm/arm-builtins.cc (UNOP_PRED_UNONE_QUALIFIERS): New
qualifier.
(UNOP_PRED_PRED_QUALIFIERS): New qualifier
(BINOP_PRED_UNONE_PRED_QUALIFIERS): New qualifier.
(v2qi_UP): New macro.
(v4bi_UP): New macro.
(v8bi_UP): New macro.
(v16bi_UP): New macro.
(arm_expand_builtin_args): Make it able to expand the new predicate
modes.
* config/arm/arm-modes.def (V2QI): New mode.
* config/arm/arm-simd-builtin-types.def (Pred1x16_t, Pred2x8_t
Pred4x4_t): Remove unused predicate builtin types.
* config/arm/arm_mve.h (__arm_vctp16q, __arm_vctp32q, __arm_vctp64q,
__arm_vctp8q, __arm_vpnot, __arm_vctp8q_m, __arm_vctp64q_m,
__arm_vctp32q_m, __arm_vctp16q_m): Use predicate modes.
* config/arm/arm_mve_builtins.def (vctp16q, vctp32q, vctp64q, vctp8q,
vpnot, vctp8q_m, vctp16q_m, vctp32q_m, vctp64q_m): Likewise.
* config/arm/constraints.md (DB): Check for VALID_MVE_PRED_MODE instead
of MODE_VECTOR_BOOL.
* config/arm/iterators.md (MVE_7, MVE_7_HI): Add V2QI
(MVE_VPRED): Likewise.
(MVE_vpred): Add V2QI and map upper case predicate modes to lower case.
(MVE_vctp): New mode attribute.
(mode1): Remove.
(VCTPQ): Remove.
(VCTPQ_M): Remove.
* config/arm/mve.md (mve_vctp<mode1>qhi): Rename this...
(mve_vctp<MVE_vctp>q<MVE_vpred>): ... to this. And use new mode
attributes.
(mve_vpnothi): Rename this...
(mve_vpnotv16bi): ... to this.
(mve_vctp<mode1>q_mhi): Rename this...
(mve_vctp<MVE_vctp>q_m<MVE_vpred>):... to this.
(mve_vldrdq_gather_base_z_<supf>v2di,
mve_vldrdq_gather_offset_z_<supf>v2di,
mve_vldrdq_gather_shifted_offset_z_<supf>v2di,
mve_vstrdq_scatter_base_p_<supf>v2di,
mve_vstrdq_scatter_offset_p_<supf>v2di,
mve_vstrdq_scatter_offset_p_<supf>v2di_insn,
mve_vstrdq_scatter_shifted_offset_p_<supf>v2di,
mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn,
mve_vstrdq_scatter_base_wb_p_<supf>v2di,
mve_vldrdq_gather_base_wb_z_<supf>v2di,
mve_vldrdq_gather_base_nowb_z_<supf>v2di,
mve_vldrdq_gather_base_wb_z_<supf>v2di_insn): Use V2QI insead of HI for
predicates.
* config/arm/unspecs.md (VCTP8Q, VCTP16Q, VCTP32Q, VCTP64Q): Replace
these...
(VCTP): ... with this.
(VCTP8Q_M, VCTP16Q_M, VCTP32Q_M, VCTP64Q_M): Replace these...
(VCTP_M): ... with this.
* config/arm/vfp.md (*thumb2_movhi_vfp, *thumb2_movhi_fp16): Use
VALID_MVE_PRED_MODE instead of checking for MODE_VECTOR_BOOL class.
2023-02-02 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR target/107674
* config/arm/arm.cc (arm_hard_regno_mode_ok): Use new MACRO.
(arm_modes_tieable_p): Make MVE predicate modes tieable.
* config/arm/arm.h (VALID_MVE_PRED_MODE): New define.
* simplify-rtx.cc (simplify_context::simplify_subreg): Teach
simplify_subreg to simplify subregs where the outermode is not scalar.
2023-02-02 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR target/107674
* config/arm/arm-builtins.cc (arm_simd_builtin_type): Rewrite to use
new qualifiers parameter and use unsigned short type for MVE predicate.
(arm_init_builtin): Call arm_simd_builtin_type with qualifiers
parameter.
(arm_init_crypto_builtins): Likewise.
2023-02-02 Jakub Jelinek <jakub@redhat.com>
PR ipa/107300
* builtins.def (BUILT_IN_UNREACHABLE_TRAP): New builtin.
* internal-fn.def (TRAP): Remove.
* internal-fn.cc (expand_TRAP): Remove.
* tree.cc (build_common_builtin_nodes): Define
BUILT_IN_UNREACHABLE_TRAP if not yet defined.
(builtin_decl_unreachable): Use BUILT_IN_UNREACHABLE_TRAP
instead of BUILT_IN_TRAP.
* gimple.cc (gimple_build_builtin_unreachable): Remove
emitting internal function for BUILT_IN_TRAP.
* asan.cc (maybe_instrument_call): Handle BUILT_IN_UNREACHABLE_TRAP.
* cgraph.cc (cgraph_edge::verify_corresponds_to_fndecl): Handle
BUILT_IN_UNREACHABLE_TRAP instead of BUILT_IN_TRAP.
* ipa-devirt.cc (possible_polymorphic_call_target_p): Handle
BUILT_IN_UNREACHABLE_TRAP.
* builtins.cc (expand_builtin, is_inexpensive_builtin): Likewise.
* tree-cfg.cc (verify_gimple_call,
pass_warn_function_return::execute): Likewise.
* attribs.cc (decl_attributes): Don't report exclusions on
BUILT_IN_UNREACHABLE_TRAP either.
2023-02-02 liuhongt <hongtao.liu@intel.com>
PR tree-optimization/108601
* tree-vectorizer.h (vect_can_peel_nonlinear_iv_p): Removed.
* tree-vect-loop.cc
(vectorizable_nonlinear_induction): Remove
vect_can_peel_nonlinear_iv_p.
(vect_can_peel_nonlinear_iv_p): Don't peel
nonlinear iv(mult or shift) for epilog when vf is not
constant and moved the defination to ..
* tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p):
.. Here.
2023-02-02 Jakub Jelinek <jakub@redhat.com>
PR middle-end/108435
* tree-nested.cc (convert_nonlocal_omp_clauses)
<case OMP_CLAUSE_LASTPRIVATE>: If info->new_local_var_chain and *seq
is not a GIMPLE_BIND, wrap the sequence into a new GIMPLE_BIND
before calling declare_vars.
(convert_nonlocal_omp_clauses) <case OMP_CLAUSE_LINEAR>: Merge
with the OMP_CLAUSE_LASTPRIVATE handling except for whether
seq is initialized to &OMP_CLAUSE_LASTPRIVATE_GIMPLE_SEQ (clause)
or &OMP_CLAUSE_LINEAR_GIMPLE_SEQ (clause).
2023-02-01 Tamar Christina <tamar.christina@arm.com>
* common/config/aarch64/aarch64-common.cc
(struct aarch64_option_extension): Add native_detect and document struct
a bit more.
(all_extensions): Set new field native_detect.
* config/aarch64/aarch64.cc (struct aarch64_option_extension): Delete
unused struct.
2023-02-01 Martin Liska <mliska@suse.cz>
* ipa-devirt.cc (odr_types_equivalent_p): Respect *warned
value if set.
2023-02-01 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/108356
* gimple-range-cache.cc (ranger_cache::range_on_edge): Always
do a search of the DOM tree for a range.
2023-02-01 Martin Liska <mliska@suse.cz>
PR ipa/108509
* cgraphunit.cc (walk_polymorphic_call_targets): Insert
ony non-null values.
* ipa.cc (walk_polymorphic_call_targets): Likewise.
2023-02-01 Martin Liska <mliska@suse.cz>
PR driver/108572
* gcc.cc (LINK_COMPRESS_DEBUG_SPEC): Report error only for
-gz=zstd.
2023-02-01 Jakub Jelinek <jakub@redhat.com>
PR debug/108573
* ree.cc (combine_reaching_defs): Don't return false for paradoxical
subregs in DEBUG_INSNs.
2023-02-01 Richard Sandiford <richard.sandiford@arm.com>
* compare-elim.cc (find_flags_uses_in_insn): Guard use of SET_SRC.
2023-02-01 Andreas Krebbel <krebbel@linux.ibm.com>
* config/s390/s390.cc (s390_restore_gpr_p): New function.
(s390_preserve_gpr_arg_in_range_p): New function.
(s390_preserve_gpr_arg_p): New function.
(s390_preserve_fpr_arg_p): New function.
(s390_register_info_stdarg_fpr): Rename to ...
(s390_register_info_arg_fpr): ... this. Add -mpreserve-args handling.
(s390_register_info_stdarg_gpr): Rename to ...
(s390_register_info_arg_gpr): ... this. Add -mpreserve-args handling.
(s390_register_info): Use the renamed functions above.
(s390_optimize_register_info): Likewise.
(save_fpr): Generate CFI for -mpreserve-args.
(save_gprs): Generate CFI for -mpreserve-args. Drop return value.
(s390_emit_prologue): Adjust to changed calling convention of save_gprs.
(s390_optimize_prologue): Likewise.
* config/s390/s390.opt: New option -mpreserve-args
2023-02-01 Andreas Krebbel <krebbel@linux.ibm.com>
* config/s390/s390.cc (save_gprs): Use gen_frame_mem.
(restore_gprs): Likewise.
(s390_emit_stack_tie): Make the stack_tie to be dependent on the
frame pointer if a frame-pointer is used.
(s390_emit_prologue): Emit stack_tie when frame-pointer is needed.
* config/s390/s390.md (stack_tie): Add a register operand and
rename to ...
(@stack_tie<mode>): ... this.
2023-02-01 Andreas Krebbel <krebbel@linux.ibm.com>
* dwarf2cfi.cc (dwarf2out_frame_debug_cfa_restore): Add
EMIT_CFI parameter.
(dwarf2out_frame_debug): Add case for REG_CFA_NORESTORE.
* reg-notes.def (REG_CFA_NOTE): New reg note definition.
2023-02-01 Richard Biener <rguenther@suse.de>
PR middle-end/108500
* dominance.cc (assign_dfs_numbers): Replace recursive DFS
with tree traversal algorithm.
2023-02-01 Jason Merrill <jason@redhat.com>
* doc/invoke.texi: Document -Wno-changes-meaning.
2023-02-01 David Malcolm <dmalcolm@redhat.com>
* doc/invoke.texi (Static Analyzer Options): Add notes about
limitations of -fanalyzer.
2023-01-31 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/constraints.md (vj): New.
(vk): Ditto
* config/riscv/iterators.md: Add more opcode.
* config/riscv/predicates.md (vector_arith_operand): New.
(vector_neg_arith_operand): New.
(vector_shift_operand): New.
* config/riscv/riscv-vector-builtins-bases.cc (class binop): New.
* config/riscv/riscv-vector-builtins-bases.h: (vadd): New.
(vsub): Ditto.
(vand): Ditto.
(vor): Ditto.
(vxor): Ditto.
(vsll): Ditto.
(vsra): Ditto.
(vsrl): Ditto.
(vmin): Ditto.
(vmax): Ditto.
(vminu): Ditto.
(vmaxu): Ditto.
(vmul): Ditto.
(vdiv): Ditto.
(vrem): Ditto.
(vdivu): Ditto.
(vremu): Ditto.
* config/riscv/riscv-vector-builtins-functions.def (vadd): New.
(vsub): Ditto.
(vand): Ditto.
(vor): Ditto.
(vxor): Ditto.
(vsll): Ditto.
(vsra): Ditto.
(vsrl): Ditto.
(vmin): Ditto.
(vmax): Ditto.
(vminu): Ditto.
(vmaxu): Ditto.
(vmul): Ditto.
(vdiv): Ditto.
(vrem): Ditto.
(vdivu): Ditto.
(vremu): Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc (struct binop_def): New.
* config/riscv/riscv-vector-builtins-shapes.h (binop): New.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_I_OPS): New.
(DEF_RVV_U_OPS): New.
(rvv_arg_type_info::get_base_vector_type): Handle
RVV_BASE_shift_vector.
(rvv_arg_type_info::get_tree_type): Ditto.
* config/riscv/riscv-vector-builtins.h (enum rvv_base_type): Add
RVV_BASE_shift_vector.
* config/riscv/riscv.cc (riscv_print_operand): Handle 'V'.
* config/riscv/vector-iterators.md: Handle more opcode.
* config/riscv/vector.md (@pred_<optab><mode>): New.
2023-01-31 Philipp Tomsich <philipp.tomsich@vrull.eu>
PR target/108589
* config/aarch64/aarch64.cc (aarch_macro_fusion_pair_p): Check
REG_P on SET_DEST.
2023-01-31 Richard Sandiford <richard.sandiford@arm.com>
PR tree-optimization/108608
* tree-vect-loop.cc (vect_transform_reduction): Handle single
def-use cycles that involve function calls rather than tree codes.
2023-01-31 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/108385
* gimple-range-gori.cc (gori_compute::compute_operand_range):
Allow VARYING computations to continue if there is a relation.
* range-op.cc (pointer_plus_operator::op2_range): New.
2023-01-31 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/108359
* range-op.cc (range_operator::wi_fold_in_parts_equiv): New.
(range_operator::fold_range): If op1 is equivalent to op2 then
invoke new fold_in_parts_equiv to operate on sub-components.
* range-op.h (wi_fold_in_parts_equiv): New prototype.
2023-01-31 Andrew MacLeod <amacleod@redhat.com>
* gimple-range-gori.cc (gori_compute::compute_operand_range): Do
not abort calculations if there is a valid relation available.
(gori_compute::refine_using_relation): Pass correct relation trio.
(gori_compute::compute_operand1_range): Create trio and use it.
(gori_compute::compute_operand2_range): Ditto.
* range-op.cc (operator_plus::op1_range): Use correct trio member.
(operator_minus::op1_range): Use correct trio member.
* value-relation.cc (value_relation::create_trio): New.
* value-relation.h (value_relation::create_trio): New prototype.
2023-01-31 Jakub Jelinek <jakub@redhat.com>
PR target/108599
* config/i386/i386-expand.cc
(ix86_convert_const_wide_int_to_broadcast): Return nullptr if
CONST_WIDE_INT_NUNITS (op) times HOST_BITS_PER_WIDE_INT isn't
equal to bitsize of mode.
2023-01-31 Jakub Jelinek <jakub@redhat.com>
PR rtl-optimization/108596
* bb-reorder.cc (fix_up_fall_thru_edges): Handle the case where cur_bb
ends with asm goto and has a crossing fallthrough edge to the same bb
that contains at least one of its labels by restoring EDGE_CROSSING
flag even on possible edge from cur_bb to new_bb successor.
2023-01-31 Jakub Jelinek <jakub@redhat.com>
PR c++/105593
* config/i386/avx512erintrin.h (_mm512_exp2a23_round_pd,
_mm512_exp2a23_round_ps, _mm512_rcp28_round_pd, _mm512_rcp28_round_ps,
_mm512_rsqrt28_round_pd, _mm512_rsqrt28_round_ps): Use
_mm512_undefined_pd () or _mm512_undefined_ps () instead of using
uninitialized automatic variable __W.
2023-01-31 Gerald Pfeifer <gerald@pfeifer.com>
* doc/include/fdl.texi: Change fsf.org to www.fsf.org.
2023-01-30 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-protos.h (get_vector_mode): New function.
* config/riscv/riscv-v.cc (get_vector_mode): Ditto.
* config/riscv/riscv-vector-builtins-bases.cc (enum lst_type): New enum.
(class loadstore): Adjust for indexed loads/stores support.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: New function declare.
* config/riscv/riscv-vector-builtins-functions.def (vluxei8): Ditto.
(vluxei16): Ditto.
(vluxei32): Ditto.
(vluxei64): Ditto.
(vloxei8): Ditto.
(vloxei16): Ditto.
(vloxei32): Ditto.
(vloxei64): Ditto.
(vsuxei8): Ditto.
(vsuxei16): Ditto.
(vsuxei32): Ditto.
(vsuxei64): Ditto.
(vsoxei8): Ditto.
(vsoxei16): Ditto.
(vsoxei32): Ditto.
(vsoxei64): Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc
(struct indexed_loadstore_def): New class.
(SHAPE): Ditto.
* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
* config/riscv/riscv-vector-builtins.cc (required_extensions_p): Adjust
for indexed loads/stores support.
(check_required_extensions): Ditto.
(rvv_arg_type_info::get_base_vector_type): New function.
(rvv_arg_type_info::get_tree_type): Ditto.
(function_builder::add_unique_function): Adjust for indexed loads/stores
support.
(function_expander::use_exact_insn): New function.
* config/riscv/riscv-vector-builtins.h (enum rvv_base_type): Adjust for
indexed loads/stores support.
(struct rvv_arg_type_info): Ditto.
(function_expander::index_mode): New function.
(function_base::apply_tail_policy_p): Ditto.
(function_base::apply_mask_policy_p): Ditto.
* config/riscv/vector-iterators.md (unspec): New unspec.
* config/riscv/vector.md (unspec): Ditto.
(@pred_indexed_<order>load<VNX1_QHSD:mode><VNX1_QHSDI:mode>): New
pattern.
(@pred_indexed_<order>store<VNX1_QHSD:mode><VNX1_QHSDI:mode>): Ditto.
(@pred_indexed_<order>load<VNX2_QHSD:mode><VNX2_QHSDI:mode>): Ditto.
(@pred_indexed_<order>store<VNX2_QHSD:mode><VNX2_QHSDI:mode>): Ditto.
(@pred_indexed_<order>load<VNX4_QHSD:mode><VNX4_QHSDI:mode>): Ditto.
(@pred_indexed_<order>store<VNX4_QHSD:mode><VNX4_QHSDI:mode>): Ditto.
(@pred_indexed_<order>load<VNX8_QHSD:mode><VNX8_QHSDI:mode>): Ditto.
(@pred_indexed_<order>store<VNX8_QHSD:mode><VNX8_QHSDI:mode>): Ditto.
(@pred_indexed_<order>load<VNX16_QHS:mode><VNX16_QHSI:mode>): Ditto.
(@pred_indexed_<order>store<VNX16_QHS:mode><VNX16_QHSI:mode>): Ditto.
(@pred_indexed_<order>load<VNX32_QH:mode><VNX32_QHI:mode>): Ditto.
(@pred_indexed_<order>store<VNX32_QH:mode><VNX32_QHI:mode>): Ditto.
(@pred_indexed_<order>load<VNX64_Q:mode><VNX64_Q:mode>): Ditto.
(@pred_indexed_<order>store<VNX64_Q:mode><VNX64_Q:mode>): Ditto.
2023-01-30 Flavio Cruz <flaviocruz@gmail.com>
* config.gcc: Recognize x86_64-*-gnu* targets and include
i386/gnu64.h.
* config/i386/gnu64.h: Define configuration for new target
including ld.so location.
2023-01-30 Philipp Tomsich <philipp.tomsich@vrull.eu>
* config/aarch64/aarch64-cores.def (AARCH64_CORE): Update
ampere1a to include SM4.
2023-01-30 Andrew Pinski <apinski@marvell.com>
PR tree-optimization/108582
* tree-ssa-phiopt.cc (match_simplify_replacement): Add check
for middlebb to have no phi nodes.
2023-01-30 Richard Biener <rguenther@suse.de>
PR tree-optimization/108574
* tree-ssa-sccvn.cc (visit_phi): Instead of swapping
sameval and def, ignore the equivalence if there's the
danger of oscillating between two values.
2023-01-30 Andreas Schwab <schwab@suse.de>
* common/config/riscv/riscv-common.cc
(riscv_option_optimization_table)
[TARGET_DEFAULT_ASYNC_UNWIND_TABLES]: Enable
-fasynchronous-unwind-tables and -funwind-tables.
* config.gcc (riscv*-*-linux*): Define
TARGET_DEFAULT_ASYNC_UNWIND_TABLES.
2023-01-30 YunQiang Su <yunqiang.su@cipunited.com>
* Makefile.in (CROSS_SYSTEM_HEADER_DIR): set according the
value of includedir.
2023-01-30 Richard Biener <rguenther@suse.de>
PR ipa/108511
* cgraph.cc (possibly_call_in_translation_unit_p): Relax
assert.
2023-01-30 liuhongt <hongtao.liu@intel.com>
* config/i386/i386.opt: Change AVX512FP16 to AVX512-FP16.
* doc/invoke.texi: Ditto.
2023-01-29 Jan Hubicka <hubicka@ucw.cz>
* ipa-utils.cc: Include calls.h, cfgloop.h and cfganal.h
(stmt_may_terminate_function_p): If assuming return or EH
volatile asm is safe.
(find_always_executed_bbs): Fix handling of terminating BBS and
infinite loops; add debug output.
* tree-ssa-alias.cc (stmt_kills_ref_p): Fix debug output
2023-01-28 Philipp Tomsich <philipp.tomsich@vrull.eu>
* config/aarch64/aarch64.cc (aarch64_uxt_size): fix an
off-by-one in checking the permissible shift-amount.
2023-01-28 Gerald Pfeifer <gerald@pfeifer.com>
* doc/extend.texi (Named Address Spaces): Update link to the
AVR-Libc manual.
2023-01-28 Gerald Pfeifer <gerald@pfeifer.com>
* doc/standards.texi (Standards): Fix markup.
2023-01-28 Gerald Pfeifer <gerald@pfeifer.com>
* doc/standards.texi (Standards): Update link to Objective-C book.
2023-01-28 Gerald Pfeifer <gerald@pfeifer.com>
* doc/invoke.texi (Instrumentation Options): Update reference to
AddressSanitizer.
2023-01-28 Gerald Pfeifer <gerald@pfeifer.com>
* doc/standards.texi: Update Go1 link.
2023-01-28 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/predicates.md (pmode_reg_or_0_operand): New predicate.
* config/riscv/riscv-vector-builtins-bases.cc (class loadstore):
Support vlse/vsse.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def (vlse): New class.
(vsse): New class.
* config/riscv/riscv-vector-builtins.cc
(function_expander::use_contiguous_load_insn): Support vlse/vsse.
* config/riscv/vector.md (@pred_strided_load<mode>): New md pattern.
(@pred_strided_store<mode>): Ditto.
2023-01-28 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/vector.md (tail_policy_op_idx): Remove.
(mask_policy_op_idx): Remove.
(avl_type_op_idx): Remove.
2023-01-27 Richard Sandiford <richard.sandiford@arm.com>
PR tree-optimization/96373
* tree.h (sign_mask_for): Declare.
* tree.cc (sign_mask_for): New function.
(signed_or_unsigned_type_for): For vector types, try to use the
related_int_vector_mode.
* genmatch.cc (commutative_op): Handle conditional internal functions.
* match.pd: Fold an IFN_COND_MUL+copysign into an IFN_COND_XOR+and.
2023-01-27 Richard Sandiford <richard.sandiford@arm.com>
* tree-vectorizer.cc (vector_costs::compare_inside_loop_cost):
Use the likely minimum VF when bounding the denominators to
the estimated number of iterations.
2023-01-27 Richard Biener <rguenther@suse.de>
PR target/55522
* doc/invoke.texi (-shared): Clarify effect on -ffast-math
and -Ofast FP environment side-effects.
2023-01-27 Richard Biener <rguenther@suse.de>
PR target/55522
* config/mips/gnu-user.h (GNU_USER_TARGET_MATHFILE_SPEC):
Don't add crtfastmath.o for -shared.
2023-01-27 Richard Biener <rguenther@suse.de>
PR target/55522
* config/ia64/linux.h (ENDFILE_SPEC): Don't add crtfastmath.o
for -shared.
2023-01-27 Richard Biener <rguenther@suse.de>
PR target/55522
* config/alpha/linux.h (ENDFILE_SPEC): Don't add
crtfastmath.o for -shared.
2023-01-27 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/108306
* range-op.cc (operator_lshift::fold_range): Return [0, 0] not
varying for shifts that are always out of void range.
(operator_rshift::fold_range): Return [0, 0] not
varying for shifts that are always out of void range.
2023-01-27 Andrew MacLeod <amacleod@redhat.com>
PR tree-optimization/108447
* gimple-range-fold.cc (old_using_range::relation_fold_and_or):
Do not attempt to fold HONOR_NAN types.
2023-01-27 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vector-builtins-shapes.cc (struct loadstore_def):
Remove _m suffix for "vop_m" C++ overloaded API name.
2023-01-27 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vector-builtins-bases.cc (BASE): Add vlm/vsm support.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def (vlm): New define.
(vsm): Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc (struct loadstore_def): Add vlm/vsm support.
* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_B_OPS): Ditto.
(vbool64_t): Ditto.
(vbool32_t): Ditto.
(vbool16_t): Ditto.
(vbool8_t): Ditto.
(vbool4_t): Ditto.
(vbool2_t): Ditto.
(vbool1_t): Ditto.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_B_OPS): Ditto.
(rvv_arg_type_info::get_tree_type): Ditto.
(function_expander::use_contiguous_load_insn): Ditto.
* config/riscv/vector.md (@pred_store<mode>): Ditto.
2023-01-27 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vsetvl.cc (vsetvl_insn_p): Add condition to avoid ICE.
(vsetvl_discard_result_insn_p): New function.
(reg_killed_by_bb_p): rename to find_reg_killed_by.
(find_reg_killed_by): New name.
(get_vl): allow it to be called by more functions.
(has_vsetvl_killed_avl_p): Add condition.
(get_avl): allow it to be called by more functions.
(insn_should_be_added_p): New function.
(get_all_nonphi_defs): Refine function.
(get_all_sets): Ditto.
(get_same_bb_set): New function.
(any_insn_in_bb_p): Ditto.
(any_set_in_bb_p): Ditto.
(get_vl_vtype_info): Add VLMAX forward optimization.
(source_equal_p): Fix issues.
(extract_single_source): Refine.
(avl_info::multiple_source_equal_p): New function.
(avl_info::operator==): Adjust for final version.
(vl_vtype_info::operator==): Ditto.
(vl_vtype_info::same_avl_p): Ditto.
(vector_insn_info::parse_insn): Ditto.
(vector_insn_info::available_p): New function.
(vector_insn_info::merge): Adjust for final version.
(vector_insn_info::dump): Add hard_empty.
(pass_vsetvl::hard_empty_block_p): New function.
(pass_vsetvl::backward_demand_fusion): Adjust for final version.
(pass_vsetvl::forward_demand_fusion): Ditto.
(pass_vsetvl::demand_fusion): Ditto.
(pass_vsetvl::cleanup_illegal_dirty_blocks): New function.
(pass_vsetvl::compute_local_properties): Adjust for final version.
(pass_vsetvl::can_refine_vsetvl_p): Ditto.
(pass_vsetvl::refine_vsetvls): Ditto.
(pass_vsetvl::commit_vsetvls): Ditto.
(pass_vsetvl::propagate_avl): New function.
(pass_vsetvl::lazy_vsetvl): Adjust for new version.
* config/riscv/riscv-vsetvl.h (enum def_type): New enum.
2023-01-27 Jakub Jelinek <jakub@redhat.com>
PR other/108560
* doc/extend.texi: Fix up return type of __builtin_va_arg_pack_len
from size_t to int.
2023-01-27 Jakub Jelinek <jakub@redhat.com>
PR ipa/106061
* cgraph.cc (cgraph_edge::verify_corresponds_to_fndecl): Allow
redirection of calls to __builtin_trap in addition to redirection
to __builtin_unreachable.
2023-01-27 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vsetvl.cc (before_p): Fix bug.
2023-01-27 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vsetvl.cc (gen_vsetvl_pat): Refine function args.
(emit_vsetvl_insn): Ditto.
2023-01-27 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/vector.md: Fix constraints.
2023-01-27 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/vector-iterators.md: Add TARGET_MIN_VLEN > 32 predicates.
2023-01-27 Patrick Palka <ppalka@redhat.com>
Jakub Jelinek <jakub@redhat.com>
* tree-core.h (tree_code_type, tree_code_length): For
C++17 and later, add inline keyword, otherwise don't define
the arrays, but declare extern arrays.
* tree.cc (tree_code_type, tree_code_length): Define these
arrays for C++14 and older.
2023-01-27 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vsetvl.h: Change it into public.
2023-01-27 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-passes.def (INSERT_PASS_BEFORE): Reorder VSETVL
pass.
2023-01-27 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vsetvl.cc (pass_vsetvl::execute): Always call split_all_insns.
2023-01-27 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/vector.md: Fix incorrect attributes.
2023-01-27 Richard Biener <rguenther@suse.de>
PR target/55522
* config/loongarch/gnu-user.h (GNU_USER_TARGET_MATHFILE_SPEC):
Don't add crtfastmath.o for -shared.
2023-01-27 Alexandre Oliva <oliva@gnu.org>
* doc/options.texi (option, RejectNegative): Mention that
-g-started options are also implicitly negatable.
2023-01-26 Kito Cheng <kito.cheng@sifive.com>
* config/riscv/riscv-vector-builtins.cc (register_builtin_types):
Use get_typenode_from_name to get fixed-width integer type
nodes.
* config/riscv/riscv-vector-builtins.def: Update define with
fixed-width integer type nodes.
2023-01-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vsetvl.cc (same_bb_and_before_p): Remove it.
(real_insn_and_same_bb_p): New function.
(same_bb_and_after_or_equal_p): Remove it.
(before_p): New function.
(reg_killed_by_bb_p): Ditto.
(has_vsetvl_killed_avl_p): Ditto.
(get_vl): Move location so that we can call it.
(anticipatable_occurrence_p): Fix issue of AVL=REG support.
(available_occurrence_p): Ditto.
(dominate_probability_p): Remove it.
(can_backward_propagate_p): Remove it.
(get_all_nonphi_defs): New function.
(get_all_predecessors): Ditto.
(any_insn_in_bb_p): Ditto.
(insert_vsetvl): Adjust AVL REG.
(source_equal_p): New function.
(extract_single_source): Ditto.
(avl_info::single_source_equal_p): Ditto.
(avl_info::operator==): Adjust for AVL=REG.
(vl_vtype_info::same_avl_p): Ditto.
(vector_insn_info::set_demand_info): Remove it.
(vector_insn_info::compatible_p): Adjust for AVL=REG.
(vector_insn_info::compatible_avl_p): New function.
(vector_insn_info::merge): Adjust AVL=REG.
(vector_insn_info::dump): Ditto.
(pass_vsetvl::merge_successors): Remove it.
(enum fusion_type): New enum.
(pass_vsetvl::get_backward_fusion_type): New function.
(pass_vsetvl::backward_demand_fusion): Adjust for AVL=REG.
(pass_vsetvl::forward_demand_fusion): Ditto.
(pass_vsetvl::demand_fusion): Ditto.
(pass_vsetvl::prune_expressions): Ditto.
(pass_vsetvl::compute_local_properties): Ditto.
(pass_vsetvl::cleanup_vsetvls): Ditto.
(pass_vsetvl::commit_vsetvls): Ditto.
(pass_vsetvl::init): Ditto.
* config/riscv/riscv-vsetvl.h (enum fusion_type): New enum.
(enum merge_type): New enum.
2023-01-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vsetvl.cc
(vector_infos_manager::vector_infos_manager): Add probability.
(vector_infos_manager::dump): Ditto.
(pass_vsetvl::compute_probabilities): Ditto.
* config/riscv/riscv-vsetvl.h (struct vector_block_info): Ditto.
2023-01-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vsetvl.cc (vector_insn_info::operator==): Remove dirty_pat.
(vector_insn_info::merge): Ditto.
(vector_insn_info::dump): Ditto.
(pass_vsetvl::merge_successors): Ditto.
(pass_vsetvl::backward_demand_fusion): Ditto.
(pass_vsetvl::forward_demand_fusion): Ditto.
(pass_vsetvl::commit_vsetvls): Ditto.
* config/riscv/riscv-vsetvl.h: Ditto.
2023-01-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vsetvl.cc (add_label_notes): Rename insn to
rinsn.
2023-01-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vsetvl.cc (pass_vsetvl::backward_demand_fusion): Refine codes.
2023-01-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vsetvl.cc (pass_vsetvl::forward_demand_fusion):
Add pre-check for redundant flow.
2023-01-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vsetvl.cc (vector_infos_manager::create_bitmap_vectors): New function.
(vector_infos_manager::free_bitmap_vectors): Ditto.
(pass_vsetvl::pre_vsetvl): Adjust codes.
* config/riscv/riscv-vsetvl.h: New function declaration.
2023-01-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vsetvl.cc (can_backward_propagate_p): Fix for null iter_bb.
(vector_insn_info::set_demand_info): New function.
(pass_vsetvl::emit_local_forward_vsetvls): Adjust for refinement of Phase 3.
(pass_vsetvl::merge_successors): Ditto.
(pass_vsetvl::compute_global_backward_infos): Ditto.
(pass_vsetvl::backward_demand_fusion): Ditto.
(pass_vsetvl::forward_demand_fusion): Ditto.
(pass_vsetvl::demand_fusion): New function.
(pass_vsetvl::lazy_vsetvl): Adjust for refinement of phase 3.
* config/riscv/riscv-vsetvl.h: New function declaration.
2023-01-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vsetvl.cc (vector_insn_info::operator>=): Fix available condition.
2023-01-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vsetvl.cc (change_vsetvl_insn): New function.
(pass_vsetvl::compute_global_backward_infos): Simplify codes.
2023-01-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vsetvl.cc (loop_basic_block_p): Adjust function.
(backward_propagate_worthwhile_p): Fix non-worthwhile.
2023-01-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vsetvl.cc (change_insn): Adjust in_group in validate_change.
2023-01-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vsetvl.cc (vector_infos_manager::all_same_avl_p): New function.
(pass_vsetvl::can_refine_vsetvl_p): Add AVL check.
(pass_vsetvl::commit_vsetvls): Ditto.
* config/riscv/riscv-vsetvl.h: New function declaration.
2023-01-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/vector.md:
2023-01-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vector-builtins-bases.cc (class loadstore): use
pred_store for vse.
* config/riscv/riscv-vector-builtins.cc
(function_expander::add_mem_operand): Refine function.
(function_expander::use_contiguous_load_insn): Adjust new
implementation.
(function_expander::use_contiguous_store_insn): Ditto.
* config/riscv/riscv-vector-builtins.h: Refine function.
* config/riscv/vector.md (@pred_store<mode>): New pattern.
2023-01-26 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv-vector-builtins.cc: Change to scalar pointer.
2023-01-26 Marek Polacek <polacek@redhat.com>
PR middle-end/108543
* opts.cc (parse_sanitizer_options): Don't always clear SANITIZE_ADDRESS
if it was previously set.
2023-01-26 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/108540
* range-op-float.cc (foperator_equal::fold_range): If both op1 and op2
are singletons, use range_true even if op1 != op2
when one range is [-0.0, -0.0] and another [0.0, 0.0]. Similarly,
even if intersection of the ranges is empty and one has
zero low bound and another zero high bound, use range_true_and_false
rather than range_false.
(foperator_not_equal::fold_range): If both op1 and op2
are singletons, use range_false even if op1 != op2
when one range is [-0.0, -0.0] and another [0.0, 0.0]. Similarly,
even if intersection of the ranges is empty and one has
zero low bound and another zero high bound, use range_true_and_false
rather than range_true.
2023-01-26 Jakub Jelinek <jakub@redhat.com>
* value-relation.cc (kind_string): Add const.
(rr_negate_table, rr_swap_table, rr_intersect_table,
rr_union_table, rr_transitive_table): Add static const, change
element type from relation_kind to unsigned char.
(relation_negate, relation_swap, relation_intersect, relation_union,
relation_transitive): Cast rr_*_table element to relation_kind.
(relation_to_code): Add static const.
(relation_tests): Assert VREL_LAST is smaller than UCHAR_MAX.
2023-01-26 Richard Biener <rguenther@suse.de>
PR tree-optimization/108547
* gimple-predicate-analysis.cc (value_sat_pred_p):
Use widest_int.
2023-01-26 Siddhesh Poyarekar <siddhesh@gotplt.org>
PR tree-optimization/108522
* tree-object-size.cc (compute_object_offset): Make EXPR
argument non-const. Call component_ref_field_offset.
2023-01-26 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-option-extensions.def (cssc): Specify
FEATURE_STRING field.
2023-01-26 Gerald Pfeifer <gerald@pfeifer.com>
* doc/sourcebuild.texi: Refer to projects as GCC and GDB.
2023-01-25 Iain Sandoe <iain@sandoe.co.uk>
PR modula2/102343
PR modula2/108182
* gcc.cc: Provide default specs for Modula-2 so that when the
language is not built-in better diagnostics are emitted for
attempts to use .mod or .m2i file extensions.
2023-01-25 Andrea Corallo <andrea.corallo@arm.com>
* config/arm/mve.md (mve_vqnegq_s<mode>): Fix spacing.
2023-01-25 Andrea Corallo <andrea.corallo@arm.com>
* config/arm/mve.md (mve_vqabsq_s<mode>): Fix spacing.
2023-01-25 Andrea Corallo <andrea.corallo@arm.com>
* config/arm/mve.md (mve_vnegq_f<mode>, mve_vnegq_s<mode>):
Fix spacing.
2023-01-25 Andrea Corallo <andrea.corallo@arm.com>
* config/arm/mve.md (@mve_vclzq_s<mode>): Fix spacing.
2023-01-25 Andrea Corallo <andrea.corallo@arm.com>
* config/arm/mve.md (mve_vclsq_s<mode>): Fix spacing.
2023-01-25 Richard Biener <rguenther@suse.de>
PR tree-optimization/108523
* tree-ssa-sccvn.cc (visit_phi): Avoid using the exclusive
backedge value for the result when using predication to
prove equivalence.
2023-01-25 Richard Biener <rguenther@suse.de>
* doc/lto.texi (Command line options): Reword and update reference
to removed lto_read_all_file_options.
2023-01-25 Richard Sandiford <richard.sandiford@arm.com>
* config/aarch64/aarch64.md (umax<mode>3): Separate the CNT and CSSC
tests.
2023-01-25 Gerald Pfeifer <gerald@pfeifer.com>
* doc/contrib.texi: Add Jose E. Marchesi.
2023-01-25 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/108498
* gimple-ssa-store-merging.cc (class store_operand_info):
End coment with full stop rather than comma.
(split_group): Likewise.
(merged_store_group::apply_stores): Clear string_concatenation if
start or end aren't on a byte boundary.
2023-01-25 Siddhesh Poyarekar <siddhesh@gotplt.org>
Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/108522
* tree-object-size.cc (compute_object_offset): Use
TREE_OPERAND(ref, 2) for COMPONENT_REF when available.
2023-01-24 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.md:
Fix exit from loops detecting references before overwriting in the
split pattern.
2023-01-24 Vladimir N. Makarov <vmakarov@redhat.com>
* lra-constraints.cc (get_hard_regno): Remove final_p arg. Always
do elimination but only for hard register.
(operands_match_p, uses_hard_regs_p, process_alt_operands): Adjust
calls of get_hard_regno.
2023-01-24 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
* config/s390/s390-d.cc (s390_d_target_versions): Fix detection
of CPU version.
2023-01-24 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR target/108177
* config/arm/mve.md (mve_vstrbq_p_<supf><mode>, mve_vstrhq_p_fv8hf,
mve_vstrhq_p_<supf><mode>, mve_vstrwq_p_<supf>v4si): Add memory operand
as input operand.
2023-01-24 Xianmiao Qu <cooper.qu@linux.alibaba.com>
* config.gcc(csky-*-linux*): Define CSKY_ENABLE_MULTILIB
and only include 'csky/t-csky-linux' when enable multilib.
* config/csky/csky-linux-elf.h(SYSROOT_SUFFIX_SPEC): Don't
define it when disable multilib.
2023-01-24 Richard Biener <rguenther@suse.de>
PR tree-optimization/108500
* dominance.h (calculate_dominance_info): Add parameter
to indicate fast-query compute, defaulted to true.
* dominance.cc (calculate_dominance_info): Honor
fast-query compute parameter.
* tree-cfgcleanup.cc (cleanup_tree_cfg_noloop): Do
not compute the dominator fast-query DFS numbers.
2023-01-24 Eric Biggers <ebiggers@google.com>
PR bootstrap/90543
* optc-save-gen.awk: Fix copy-and-paste error.
2023-01-24 Jakub Jelinek <jakub@redhat.com>
PR c++/108474
* cgraphbuild.cc: Include gimplify.h.
(record_reference): Replace VAR_DECLs with DECL_HAS_VALUE_EXPR_P with
their corresponding DECL_VALUE_EXPR expressions after unsharing.
2023-01-24 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
PR target/108505
* config.gcc (tm_file): Move the variable out of loop.
2023-01-24 Lulu Cheng <chenglulu@loongson.cn>
Yang Yujie <yangyujie@loongson.cn>
PR target/107731
* config/loongarch/loongarch.cc (loongarch_classify_address):
Add precessint for CONST_INT.
(loongarch_print_operand_reloc): Operand modifier 'c' is supported.
(loongarch_print_operand): Increase the processing of '%c'.
* doc/extend.texi: Adds documents for LoongArch operand modifiers.
And port the public operand modifiers information to this document.
2023-01-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* doc/invoke.texi (-mbranch-protection): Update documentation.
2023-01-23 Richard Biener <rguenther@suse.de>
PR target/55522
* config/sparc/freebsd.h (ENDFILE_SPEC): Don't add crtfastmath.o
for -shared.
* config/sparc/linux.h (ENDFILE_SPEC): Likewise.
* config/sparc/linux64.h (ENDFILE_SPEC): Likewise.
* config/sparc/sp-elf.h (ENDFILE_SPEC): Likewise.
* config/sparc/sp64-elf.h (ENDFILE_SPEC): Likewise.
2023-01-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/arm/aout.h (ra_auth_code): Add entry in enum.
* config/arm/arm.cc (emit_multi_reg_push): Add RA_AUTH_CODE register
to dwarf frame expression.
(arm_emit_multi_reg_pop): Restore RA_AUTH_CODE register.
(arm_expand_prologue): Update frame related information and reg notes
for pac/pacbit insn.
(arm_regno_class): Check for pac pseudo reigster.
(arm_dbx_register_number): Assign ra_auth_code register number in dwarf.
(arm_init_machine_status): Set pacspval_needed to zero.
(arm_debugger_regno): Check for PAC register.
(arm_unwind_emit_sequence): Print .save directive with ra_auth_code
register.
(arm_unwind_emit_set): Add entry for IP_REGNUM in switch case.
(arm_unwind_emit): Update REG_CFA_REGISTER case._
* config/arm/arm.h (FIRST_PSEUDO_REGISTER): Modify.
(DWARF_PAC_REGNUM): Define.
(IS_PAC_REGNUM): Likewise.
(enum reg_class): Add PAC_REG entry.
(machine_function): Add pacbti_needed state to structure.
* config/arm/arm.md (RA_AUTH_CODE): Define.
2023-01-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config.gcc ($tm_file): Update variable.
* config/arm/arm-mlib.h: Create new header file.
* config/arm/t-rmprofile (MULTI_ARCH_DIRS_RM): Rename mbranch-protection
multilib arch directory.
(MULTILIB_REUSE): Add multilib reuse rules.
(MULTILIB_MATCHES): Add multilib match rules.
2023-01-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/arm/arm-cpus.in (cortex-m85): Define new CPU.
* config/arm/arm-tables.opt: Regenerate.
* config/arm/arm-tune.md: Likewise.
* doc/invoke.texi (Arm Options): Document -mcpu=cortex-m85.
* (-mfix-cmse-cve-2021-35465): Likewise.
2023-01-23 Richard Biener <rguenther@suse.de>
PR tree-optimization/108482
* tree-vect-generic.cc (expand_vector_operations): Fold remaining
.LOOP_DIST_ALIAS calls.
2023-01-23 Andrea Corallo <andrea.corallo@arm.com>
* config.gcc (arm*-*-*): Add 'aarch-bti-insert.o' object.
* config/arm/arm-protos.h: Update.
* config/arm/aarch-common-protos.h: Declare
'aarch_bti_arch_check'.
* config/arm/arm.cc (aarch_bti_enabled) Update.
(aarch_bti_j_insn_p, aarch_pac_insn_p, aarch_gen_bti_c)
(aarch_gen_bti_j, aarch_bti_arch_check): New functions.
* config/arm/arm.md (bti_nop): New insn.
* config/arm/t-arm (PASSES_EXTRA): Add 'arm-passes.def'.
(aarch-bti-insert.o): New target.
* config/arm/unspecs.md (VUNSPEC_BTI_NOP): New unspec.
* config/arm/aarch-bti-insert.cc (rest_of_insert_bti): Verify arch
compatibility.
(gate): Make use of 'aarch_bti_arch_check'.
* config/arm/arm-passes.def: New file.
* config/aarch64/aarch64.cc (aarch_bti_arch_check): New function.
2023-01-23 Andrea Corallo <andrea.corallo@arm.com>
* config.gcc (aarch64*-*-*): Rename 'aarch64-bti-insert.o' into
'aarch-bti-insert.o'.
* config/aarch64/aarch64-protos.h: Remove 'aarch64_bti_enabled'
proto.
* config/aarch64/aarch64.cc (aarch_bti_enabled): Rename.
(aarch_bti_j_insn_p, aarch_pac_insn_p): New functions.
(aarch64_output_mi_thunk)
(aarch64_print_patchable_function_entry)
(aarch64_file_end_indicate_exec_stack): Update renamed function
calls to renamed functions.
* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Likewise.
* config/aarch64/t-aarch64 (aarch-bti-insert.o): Update
target.
* config/aarch64/aarch64-bti-insert.cc: Delete.
* config/arm/aarch-bti-insert.cc: New file including and
generalizing code from aarch64-bti-insert.cc.
* config/arm/aarch-common-protos.h: Update.
2023-01-23 Andrea Corallo <andrea.corallo@arm.com>
* config/arm/arm.h (arm_arch8m_main): Declare it.
* config/arm/arm-protos.h (arm_current_function_pac_enabled_p):
Declare it.
* config/arm/arm.cc (arm_arch8m_main): Define it.
(arm_option_reconfigure_globals): Set arm_arch8m_main.
(arm_compute_frame_layout, arm_expand_prologue)
(thumb2_expand_return, arm_expand_epilogue)
(arm_conditional_register_usage): Update for pac codegen.
(arm_current_function_pac_enabled_p): New function.
(aarch_bti_enabled) New function.
(use_return_insn): Return zero when pac is enabled.
* config/arm/arm.md (pac_ip_lr_sp, pacbti_ip_lr_sp, aut_ip_lr_sp):
Add new patterns.
* config/arm/unspecs.md (UNSPEC_PAC_NOP)
(VUNSPEC_PACBTI_NOP, VUNSPEC_AUT_NOP): Add unspecs.
2023-01-23 Andrea Corallo <andrea.corallo@arm.com>
* config/arm/t-rmprofile: Add multilib rules for march +pacbti and
mbranch-protection.
2023-01-23 Andrea Corallo <andrea.corallo@arm.com>
Tejas Belagod <tbelagod@arm.com>
* config/arm/arm.cc (arm_file_start): Emit EABI attributes for
Tag_PAC_extension, Tag_BTI_extension, TAG_BTI_use, TAG_PACRET_use.
2023-01-23 Andrea Corallo <andrea.corallo@arm.com>
Tejas Belagod <tbelagod@arm.com>
Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* ginclude/unwind-arm-common.h (_Unwind_VRS_RegClass): Introduce
new pseudo register class _UVRSC_PAC.
2023-01-23 Andrea Corallo <andrea.corallo@arm.com>
Tejas Belagod <tbelagod@arm.com>
* config/arm/arm-c.cc (arm_cpu_builtins): Define
__ARM_FEATURE_BTI_DEFAULT, __ARM_FEATURE_PAC_DEFAULT,
__ARM_FEATURE_PAUTH and __ARM_FEATURE_BTI.
2023-01-23 Andrea Corallo <andrea.corallo@arm.com>
Tejas Belagod <tbelagod@arm.com>
* doc/sourcebuild.texi: Document arm_pacbti_hw.
2023-01-23 Andrea Corallo <andrea.corallo@arm.com>
Tejas Belagod <tbelagod@arm.com>
Richard Earnshaw <Richard.Earnshaw@arm.com>
* config/arm/arm.cc (arm_configure_build_target): Parse and validate
-mbranch-protection option and initialize appropriate data structures.
* config/arm/arm.opt (-mbranch-protection): New option.
* doc/invoke.texi (Arm Options): Document it.
2023-01-23 Andrea Corallo <andrea.corallo@arm.com>
Tejas Belagod <tbelagod@arm.com>
* config/arm/arm.h (TARGET_HAVE_PACBTI): New macro.
* config/arm/arm-cpus.in (pacbti): New feature.
* doc/invoke.texi (Arm Options): Document it.
2023-01-23 Andrea Corallo <andrea.corallo@arm.com>
Tejas Belagod <tbelagod@arm.com>
* common/config/aarch64/aarch64-common.cc: Include aarch-common.h.
(all_architectures): Fix comment.
(aarch64_parse_extension): Rename return type, enum value names.
* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Rename
factored out aarch_ra_sign_scope and aarch_ra_sign_key variables.
Also rename corresponding enum values.
* config/aarch64/aarch64-opts.h (aarch64_function_type): Factor
out aarch64_function_type and move it to common code as
aarch_function_type in aarch-common.h.
* config/aarch64/aarch64-protos.h: Include common types header,
move out types aarch64_parse_opt_result and aarch64_key_type to
aarch-common.h
* config/aarch64/aarch64.cc: Move mbranch-protection parsing types
and functions out into aarch-common.h and aarch-common.cc. Fix up
all the name changes resulting from the move.
* config/aarch64/aarch64.md: Fix up aarch64_ra_sign_key type name change
and enum value.
* config/aarch64/aarch64.opt: Include aarch-common.h to import
type move. Fix up name changes from factoring out common code and
data.
* config/arm/aarch-common-protos.h: Export factored out routines to both
backends.
* config/arm/aarch-common.cc: Include newly factored out types.
Move all mbranch-protection code and data structures from
aarch64.cc.
* config/arm/aarch-common.h: New header that declares types shared
between aarch32 and aarch64 backends.
* config/arm/arm-protos.h: Declare types and variables that are
made common to aarch64 and aarch32 backends - aarch_ra_sign_key,
aarch_ra_sign_scope and aarch_enable_bti.
* config/arm/arm.opt (config/arm/aarch-common.h): Include header.
(aarch_ra_sign_scope, aarch_enable_bti): Declare variable.
* config/arm/arm.cc: Add missing includes.
2023-01-23 Tobias Burnus <tobias@codesourcery.com>
* doc/install.texi (amdgcn, nvptx): Require newlib 4.3.0.
2023-01-23 Richard Biener <rguenther@suse.de>
PR tree-optimization/108449
* cgraphunit.cc (check_global_declaration): Do not turn
undefined statics into externs.
2023-01-22 Dimitar Dimitrov <dimitar@dinux.eu>
* config/pru/pru.h (CLZ_DEFINED_VALUE_AT_ZERO): Fix value for QI
and HI input modes.
* config/pru/pru.md (clz): Fix generated code for QI and HI
input modes.
2023-01-22 Cupertino Miranda <cupertino.miranda@oracle.com>
* config/v850/v850.cc (v850_select_section): Put const volatile
objects into read-only sections.
2023-01-20 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/arm_neon.h (vmull_p64, vmull_high_p64, vaeseq_u8,
vaesdq_u8, vaesmcq_u8, vaesimcq_u8): Gate under "nothing+aes".
(vsha1*_u32, vsha256*_u32): Gate under "nothing+sha2".
2023-01-20 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/108457
* tree-ssa-loop-niter.cc (build_cltz_expr): Use
SCALAR_INT_TYPE_MODE (utype) directly as C[LT]Z_DEFINED_VALUE_AT_ZERO
argument instead of a temporary. Formatting fixes.
2023-01-19 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/108447
* value-relation.cc (rr_union_table): Fix VREL_UNDEFINED row order.
(relation_tests): Add self-tests for relation_{intersect,union}
commutativity.
* selftest.h (relation_tests): Declare.
* function-tests.cc (test_ranges): Call it.
2023-01-19 H.J. Lu <hjl.tools@gmail.com>
PR target/108436
* config/i386/i386-expand.cc (ix86_expand_builtin): Check
invalid third argument to __builtin_ia32_prefetch.
2023-01-19 Jakub Jelinek <jakub@redhat.com>
PR middle-end/108459
* omp-expand.cc (expand_omp_for_init_counts): Use fold_build1 rather
than fold_unary for NEGATE_EXPR.
2023-01-19 Christophe Lyon <christophe.lyon@arm.com>
PR target/108411
* config/aarch64/aarch64.cc (aarch64_layout_arg): Improve
comment. Move assert about alignment a bit later.
2023-01-19 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/108440
* tree-ssa-forwprop.cc: Include gimple-range.h.
(simplify_rotate): For the forms with T2 wider than T and shift counts of
Y and B - Y add & (B - 1) masking for the rotate count if Y could be equal
to B. For the forms with T2 wider than T and shift counts of
Y and (-Y) & (B - 1), don't punt if range could be [B, B2], but only if
range doesn't guarantee Y < B or Y = N * B. If range doesn't guarantee
Y < B, also add & (B - 1) masking for the rotate count. Use lazily created
pass specific ranger instead of get_global_range_query.
(pass_forwprop::execute): Disable that ranger at the end of pass if it has
been created.
2023-01-19 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
* config/aarch64/aarch64-simd.md (aarch64_simd_vec_set<mode>): Use
exact_log2 (INTVAL (operands[2])) >= 0 as condition for gating
the pattern.
(aarch64_simd_vec_copy_lane<mode>): Likewise.
(aarch64_simd_vec_copy_lane_<vswap_width_name><mode>): Likewise.
2023-01-19 Alexandre Oliva <oliva@adacore.com>
PR debug/106746
* sched-deps.cc (sched_analyze_2): Skip cselib address lookup
within debug insns.
2023-01-18 Martin Jambor <mjambor@suse.cz>
PR ipa/107944
* cgraph.cc (cgraph_node::remove): Check whether nodes up the
lcone_of chain also do not need the body.
2023-01-18 Richard Biener <rguenther@suse.de>
Revert:
2022-12-16 Richard Biener <rguenther@suse.de>
PR middle-end/108086
* tree-inline.cc (remap_ssa_name): Do not unshare the
result from the decl_map.
2023-01-18 Murray Steele <murray.steele@arm.com>
PR target/108442
* config/arm/arm_mve.h (__arm_vst1q_p_u8): Use prefixed intrinsic
function.
(__arm_vst1q_p_s8): Likewise.
(__arm_vld1q_z_u8): Likewise.
(__arm_vld1q_z_s8): Likewise.
(__arm_vst1q_p_u16): Likewise.
(__arm_vst1q_p_s16): Likewise.
(__arm_vld1q_z_u16): Likewise.
(__arm_vld1q_z_s16): Likewise.
(__arm_vst1q_p_u32): Likewise.
(__arm_vst1q_p_s32): Likewise.
(__arm_vld1q_z_u32): Likewise.
(__arm_vld1q_z_s32): Likewise.
(__arm_vld1q_z_f16): Likewise.
(__arm_vst1q_p_f16): Likewise.
(__arm_vld1q_z_f32): Likewise.
(__arm_vst1q_p_f32): Likewise.
2023-01-18 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.md (xorsi3_internal):
Rename from the original of "xorsi3".
(xorsi3): New expansion pattern that emits addition rather than
bitwise-XOR when the second source is a constant of -2147483648
if TARGET_DENSITY.
2023-01-18 Kewen Lin <linkw@linux.ibm.com>
Andrew Pinski <apinski@marvell.com>
PR target/108396
* config/rs6000/rs6000-overload.def (VEC_VSUBCUQ): Fix typo
vec_vsubcuqP with vec_vsubcuq.
2023-01-18 Kewen Lin <linkw@linux.ibm.com>
PR target/108348
* config/rs6000/rs6000.cc (rs6000_opaque_type_invalid_use_p): Add the
support for invalid uses of MMA opaque type in function arguments.
2023-01-18 liuhongt <hongtao.liu@intel.com>
PR target/55522
* config/i386/cygwin.h (ENDFILE_SPEC): Link crtfastmath.o
whenever -mdaz-ftz is specified. Don't link crtfastmath.o when
-share or -mno-daz-ftz is specified.
* config/i386/darwin.h (ENDFILE_SPEC): Ditto.
* config/i386/mingw32.h (ENDFILE_SPEC): Ditto.
2023-01-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/bpf/bpf.cc (bpf_option_override): Disable
-fstack-protector.
2023-01-17 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/106523
* tree-ssa-forwprop.cc (simplify_rotate): For the
patterns with (-Y) & (B - 1) in one operand's shift
count and Y in another, if T2 has wider precision than T,
punt if Y could have a value in [B, B2 - 1] range.
2023-01-16 H.J. Lu <hjl.tools@gmail.com>
PR target/105980
* config/i386/i386.cc (x86_output_mi_thunk): Disable
-mforce-indirect-call for PIC in 32-bit mode.
2023-01-16 Jan Hubicka <hubicka@ucw.cz>
PR ipa/106077
* ipa-modref.cc (modref_access_analysis::analyze): Use
find_always_executed_bbs.
* ipa-sra.cc (process_scan_results): Likewise.
* ipa-utils.cc (stmt_may_terminate_function_p): New function.
(find_always_executed_bbs): New function.
* ipa-utils.h (stmt_may_terminate_function_p): Declare.
(find_always_executed_bbs): Declare.
2023-01-16 Jan Hubicka <jh@suse.cz>
* config/i386/i386.cc (ix86_vectorize_builtin_scatter): Guard scatter
by TARGET_USE_SCATTER.
* config/i386/i386.h (TARGET_USE_SCATTER_2PARTS,
TARGET_USE_SCATTER_4PARTS, TARGET_USE_SCATTER): New macros.
* config/i386/x86-tune.def (TARGET_USE_SCATTER_2PARTS,
TARGET_USE_SCATTER_4PARTS, TARGET_USE_SCATTER): New tunes.
(X86_TUNE_AVOID_256FMA_CHAINS, X86_TUNE_AVOID_512FMA_CHAINS): Disable
for znver4. (X86_TUNE_USE_GATHER): Disable for zen4.
2023-01-16 Richard Biener <rguenther@suse.de>
PR target/55522
* config/sol2.h (ENDFILE_SPEC): Don't add crtfastmath.o for -shared.
2023-01-16 Stam Markianos-Wright <stam.markianos-wright@arm.com>
PR target/96795
PR target/107515
* config/arm/arm_mve.h (__ARM_mve_coerce2): Split types.
(__ARM_mve_coerce3): Likewise.
2023-01-16 Andrew Carlotti <andrew.carlotti@arm.com>
* tree-ssa-loop-niter.cc (build_popcount_expr): Add IFN support.
2023-01-16 Andrew Carlotti <andrew.carlotti@arm.com>
* tree-ssa-loop-niter.cc (number_of_iterations_cltz): New.
(number_of_iterations_bitcount): Add call to the above.
(number_of_iterations_exit_assumptions): Add EQ_EXPR case for
c[lt]z idiom recognition.
2023-01-16 Andrew Carlotti <andrew.carlotti@arm.com>
* doc/sourcebuild.texi: Add missing target attributes.
2023-01-16 Andrew Carlotti <andrew.carlotti@arm.com>
PR tree-optimization/94793
* tree-scalar-evolution.cc (expression_expensive_p): Add checks
for c[lt]z optabs.
* tree-ssa-loop-niter.cc (build_cltz_expr): New.
(number_of_iterations_cltz_complement): New.
(number_of_iterations_bitcount): Add call to the above.
2023-01-16 Jonathan Wakely <jwakely@redhat.com>
* doc/extend.texi (Common Function Attributes): Fix grammar.
2023-01-16 Jakub Jelinek <jakub@redhat.com>
PR other/108413
* config/riscv/riscv-vsetvl.h: Add space in between Copyright and (C).
* config/riscv/riscv-vsetvl.cc: Likewise.
2023-01-16 Jakub Jelinek <jakub@redhat.com>
PR c++/105593
* config/i386/xmmintrin.h (_mm_undefined_ps): Temporarily
disable -Winit-self using pragma GCC diagnostic ignored.
* config/i386/emmintrin.h (_mm_undefined_pd, _mm_undefined_si128):
Likewise.
* config/i386/avxintrin.h (_mm256_undefined_pd, _mm256_undefined_ps,
_mm256_undefined_si256): Likewise.
* config/i386/avx512fintrin.h (_mm512_undefined_pd,
_mm512_undefined_ps, _mm512_undefined_epi32): Likewise.
* config/i386/avx512fp16intrin.h (_mm_undefined_ph,
_mm256_undefined_ph, _mm512_undefined_ph): Likewise.
2023-01-16 Kewen Lin <linkw@linux.ibm.com>
PR target/108272
* config/rs6000/rs6000.cc (rs6000_opaque_type_invalid_use_p): Add the
support for invalid uses in inline asm, factor out the checking and
erroring to lambda function check_and_error_invalid_use.
2023-01-15 Aldy Hernandez <aldyh@redhat.com>
PR tree-optimization/107608
* range-op-float.cc (range_operator_float::fold_range): Avoid
folding into INF when flag_trapping_math.
* value-range.h (frange::known_isinf): Return false for possible NANs.
2023-01-15 Xianmiao Qu <cooper.qu@linux.alibaba.com>
* config.gcc (csky-*-*): Support --with-float=softfp.
2023-01-14 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa-protos.h (order_regs_for_local_alloc):
Rename to xtensa_adjust_reg_alloc_order.
* config/xtensa/xtensa.cc (xtensa_adjust_reg_alloc_order):
Ditto. And also remove code to reorder register numbers for
leaf functions, rename the tables, and adjust the allocation
order for the call0 ABI to use register A0 more.
(xtensa_leaf_regs): Remove.
* config/xtensa/xtensa.h (REG_ALLOC_ORDER): Cosmetics.
(order_regs_for_local_alloc): Rename as the above.
(LEAF_REGISTERS, LEAF_REG_REMAP, leaf_function): Remove.
2023-01-14 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
* config/aarch64/aarch64-sve.md (aarch64_vec_duplicate_vq<mode>_le):
Change to define_insn_and_split to fold ldr+dup to ld1rq.
* config/aarch64/predicates.md (aarch64_sve_dup_ld1rq_operand): New.
2023-01-14 Alexandre Oliva <oliva@adacore.com>
* hash-table.h (is_deleted): Precheck !is_empty.
(mark_deleted): Postcheck !is_empty.
(copy constructor): Test is_empty before is_deleted.
2023-01-14 Alexandre Oliva <oliva@adacore.com>
PR target/40457
* config/arm/arm.md (movmisaligndi): Prefer aligned SImode
moves.
2023-01-13 Eric Botcazou <ebotcazou@adacore.com>
PR rtl-optimization/108274
* function.cc (thread_prologue_and_epilogue_insns): Also update the
DF information for calls in a few more cases.
2023-01-13 John David Anglin <danglin@gcc.gnu.org>
* config/pa/pa-linux.h (TARGET_SYNC_LIBCALL): Delete define.
* config/pa/pa.cc (pa_init_libfuncs): Use MAX_SYNC_LIBFUNC_SIZE
define.
* config/pa/pa.h (TARGET_SYNC_LIBCALLS): Use flag_sync_libcalls.
(MAX_SYNC_LIBFUNC_SIZE): Define.
(TARGET_CPU_CPP_BUILTINS): Define __SOFTFP__ when soft float is
enabled.
* config/pa/pa.md (atomic_storeqi): Emit __atomic_exchange_1
libcall when sync libcalls are disabled.
(atomic_storehi, atomic_storesi, atomic_storedi): Likewise.
(atomic_loaddi): Emit __atomic_load_8 libcall when sync libcalls
are disabled on 32-bit target.
* config/pa/pa.opt (matomic-libcalls): New option.
* doc/invoke.texi (HPPA Options): Update.
2023-01-13 Alexander Monakov <amonakov@ispras.ru>
PR rtl-optimization/108117
PR rtl-optimization/108132
* sched-deps.cc (deps_analyze_insn): Do not schedule across
calls before reload.
2023-01-13 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* common/config/arm/arm-common.cc (arm_canon_arch_option_1): Ignore cde
options for -mlibarch.
* config/arm/arm-cpus.in (begin cpu cortex-m55): Add cde options.
* doc/invoke.texi (CDE): Document options for Cortex-M55 CPU.
2023-01-13 Qing Zhao <qing.zhao@oracle.com>
* attribs.cc (strict_flex_array_level_of): Move this function to ...
* attribs.h (strict_flex_array_level_of): Remove the declaration.
* gimple-array-bounds.cc (array_bounds_checker::check_array_ref):
replace the referece to strict_flex_array_level_of with
DECL_NOT_FLEXARRAY.
* tree.cc (component_ref_size): Likewise.
2023-01-13 Richard Biener <rguenther@suse.de>
PR target/55522
* config/arm/linux-eabi.h (ENDFILE_SPEC): Don't add
crtfastmath.o for -shared.
* config/arm/unknown-elf.h (STARTFILE_SPEC): Likewise.
2023-01-13 Richard Biener <rguenther@suse.de>
PR target/55522
* config/aarch64/aarch64-elf-raw.h (ENDFILE_SPEC): Don't add
crtfastmath.o for -shared.
* config/aarch64/aarch64-freebsd.h (GNU_USER_TARGET_MATHFILE_SPEC):
Likewise.
* config/aarch64/aarch64-linux.h (GNU_USER_TARGET_MATHFILE_SPEC):
Likewise.
2023-01-13 Richard Sandiford <richard.sandiford@arm.com>
* config/aarch64/aarch64.cc (aarch64_dwarf_frame_reg_mode): New
function.
(TARGET_DWARF_FRAME_REG_MODE): Define.
2023-01-13 Richard Biener <rguenther@suse.de>
PR target/107209
* config/aarch64/aarch64.cc (aarch64_gimple_fold_builtin): Don't
update EH info on the fly.
2023-01-13 Richard Biener <rguenther@suse.de>
PR tree-optimization/108387
* tree-ssa-sccvn.cc (visit_nary_op): Check for SSA_NAME
value before inserting expression into the tables.
2023-01-12 Andrew Pinski <apinski@marvell.com>
Roger Sayle <roger@nextmovesoftware.com>
PR tree-optimization/92342
* match.pd ((m1 CMP m2) * d -> (m1 CMP m2) ? d : 0):
Use tcc_comparison and :c for the multiply.
(b & -(a CMP c) -> (a CMP c)?b:0): New pattern.
2023-01-12 Christophe Lyon <christophe.lyon@arm.com>
Richard Sandiford <richard.sandiford@arm.com>
PR target/105549
* config/aarch64/aarch64.cc (aarch64_function_arg_alignment):
Check DECL_PACKED for bitfield.
(aarch64_layout_arg): Warn when parameter passing ABI changes.
(aarch64_function_arg_boundary): Do not warn here.
(aarch64_gimplify_va_arg_expr): Warn when parameter passing ABI
changes.
2023-01-12 Christophe Lyon <christophe.lyon@arm.com>
Richard Sandiford <richard.sandiford@arm.com>
* config/aarch64/aarch64.cc (aarch64_function_arg_alignment): Fix
comment.
(aarch64_layout_arg): Factorize warning conditions.
(aarch64_function_arg_boundary): Fix typo.
* function.cc (currently_expanding_function_start): New variable.
(expand_function_start): Handle
currently_expanding_function_start.
* function.h (currently_expanding_function_start): Declare.
2023-01-12 Richard Biener <rguenther@suse.de>
PR tree-optimization/99412
* tree-ssa-reassoc.cc (is_phi_for_stmt): Remove.
(swap_ops_for_binary_stmt): Remove reduction handling.
(rewrite_expr_tree_parallel): Adjust.
(reassociate_bb): Likewise.
* tree-parloops.cc (build_new_reduction): Handle MINUS_EXPR.
2023-01-12 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.md (ctzsi2, ffssi2):
Rearrange the emitting codes.
2023-01-12 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.md (*btrue):
Correct value of the attribute "length" that depends on
TARGET_DENSITY and operands, and add '?' character to the register
constraint of the compared operand.
2023-01-12 Alexandre Oliva <oliva@adacore.com>
* hash-table.h (expand): Check elements and deleted counts.
(verify): Likewise.
2023-01-11 Roger Sayle <roger@nextmovesoftware.com>
PR tree-optimization/71343
* tree-ssa-sccvn.cc (visit_nary_op) <case LSHIFT_EXPR>: Make
the value number of the expression X << C the same as the value
number for the multiplication X * (1<<C).
2023-01-11 David Faust <david.faust@oracle.com>
PR target/108293
* config/bpf/bpf.cc (bpf_print_operand): Correct handling for
floating point modes.
2023-01-11 Eric Botcazou <ebotcazou@adacore.com>
PR tree-optimization/108199
* tree-sra.cc (sra_modify_expr): Deal with reverse storage order
for bit-field references.
2023-01-11 Kewen Lin <linkw@linux.ibm.com>
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Make
OPTION_MASK_P10_FUSION implicit setting honour Power10 tuning setting.
* config/rs6000/rs6000-cpus.def (ISA_3_1_MASKS_SERVER): Remove
OPTION_MASK_P10_FUSION.
2023-01-11 Richard Biener <rguenther@suse.de>
PR tree-optimization/107767
* tree-cfgcleanup.cc (phi_alternatives_equal): Export.
* tree-cfgcleanup.h (phi_alternatives_equal): Declare.
* tree-switch-conversion.cc (switch_conversion::collect):
Count unique non-default targets accounting for later
merging opportunities.
2023-01-11 Martin Liska <mliska@suse.cz>
PR middle-end/107976
* params.opt: Limit JT params.
* stmt.cc (emit_case_dispatch_table): Use auto_vec.
2023-01-11 Richard Biener <rguenther@suse.de>
PR tree-optimization/108352
* tree-ssa-threadbackward.cc
(back_threader_profitability::profitable_path_p): Adjust
heuristic that allows non-multi-way branch threads creating
irreducible loops.
* doc/invoke.texi (--param fsm-scale-path-blocks): Remove.
(--param fsm-scale-path-stmts): Adjust.
* params.opt (--param=fsm-scale-path-blocks=): Remove.
(-param=fsm-scale-path-stmts=): Adjust description.
2023-01-11 Richard Biener <rguenther@suse.de>
PR tree-optimization/108353
* tree-ssa-propagate.cc (cfg_blocks_back, ssa_edge_worklist_back):
Remove.
(add_ssa_edge): Simplify.
(add_control_edge): Likewise.
(ssa_prop_init): Likewise.
(ssa_prop_fini): Likewise.
(ssa_propagation_engine::ssa_propagate): Likewise.
2023-01-11 Andreas Krebbel <krebbel@linux.ibm.com>
* config/s390/s390.md (*not<mode>): New pattern.
2023-01-11 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.cc (xtensa_insn_cost):
Let insn cost for size be obtained by applying COSTS_N_INSNS()
to instruction length and then dividing by 3.
2023-01-10 Richard Biener <rguenther@suse.de>
PR tree-optimization/106293
* tree-ssa-dse.cc (dse_classify_store): Use a worklist to
process degenerate PHI defs.
2023-01-10 Roger Sayle <roger@nextmovesoftware.com>
PR rtl-optimization/106421
* cprop.cc (bypass_block): Check that DEST is local to this
function (non-NULL) before calling find_edge.
2023-01-10 Martin Jambor <mjambor@suse.cz>
PR ipa/108110
* ipa-param-manipulation.h (ipa_param_body_adjustments): New members
sort_replacements, lookup_first_base_replacement and
m_sorted_replacements_p.
* ipa-param-manipulation.cc: Define INCLUDE_ALGORITHM.
(ipa_param_body_adjustments::register_replacement): Set
m_sorted_replacements_p to false.
(compare_param_body_replacement): New function.
(ipa_param_body_adjustments::sort_replacements): Likewise.
(ipa_param_body_adjustments::common_initialization): Call
sort_replacements.
(ipa_param_body_adjustments::ipa_param_body_adjustments): Initialize
m_sorted_replacements_p.
(ipa_param_body_adjustments::lookup_replacement_1): Rework to use
std::lower_bound.
(ipa_param_body_adjustments::lookup_first_base_replacement): New
function.
(ipa_param_body_adjustments::modify_call_stmt): Use
lookup_first_base_replacement.
* omp-simd-clone.cc (ipa_simd_modify_function_body): Call
adjustments->sort_replacements.
2023-01-10 Richard Biener <rguenther@suse.de>
PR tree-optimization/108314
* tree-vect-stmts.cc (vectorizable_condition): Do not
perform BIT_NOT_EXPR optimization for EXTRACT_LAST_REDUCTION.
2023-01-10 Xianmiao Qu <cooper.qu@linux.alibaba.com>
* config/csky/csky-linux-elf.h (SYSROOT_SUFFIX_SPEC): New.
2023-01-10 Xianmiao Qu <cooper.qu@linux.alibaba.com>
* config/csky/csky.h (MULTILIB_DEFAULTS): Fix float abi option.
2023-01-10 Xianmiao Qu <cooper.qu@linux.alibaba.com>
* config/csky/csky.cc (csky_cpu_cpp_builtins): Add builtin
defines for soft float abi.
2023-01-10 Xianmiao Qu <cooper.qu@linux.alibaba.com>
* config/csky/csky.md (smart_bseti): Change condition to CSKY_ISA_FEATURE (E1).
(smart_bclri): Likewise.
(fast_bseti): Change condition to CSKY_ISA_FEATURE (E2).
(fast_bclri): Likewise.
(fast_cmpnesi_i): Likewise.
(*fast_cmpltsi_i): Likewise.
(*fast_cmpgeusi_i): Likewise.
2023-01-10 Xianmiao Qu <cooper.qu@linux.alibaba.com>
* config/csky/csky_insn_fpuv3.md (l<frm_pattern><fixsuop><mode>si2): Test
flag_fp_int_builtin_inexact || !flag_trapping_math.
(<frm_pattern><mode>2): Likewise.
2023-01-10 Andreas Krebbel <krebbel@linux.ibm.com>
* config/s390/s390.cc (s390_register_info): Check call_used_regs
instead of hard-coding the register numbers for call saved
registers.
(s390_optimize_register_info): Likewise.
2023-01-09 Eric Botcazou <ebotcazou@adacore.com>
* doc/gm2.texi (Overview): Fix @node markers.
(Using): Likewise. Remove subsections that were moved to Overview
from the menu and move others around.
2023-01-09 Richard Biener <rguenther@suse.de>
PR middle-end/108209
* genmatch.cc (commutative_op): Fix return value for
user-id with non-commutative first replacement.
2023-01-09 Jakub Jelinek <jakub@redhat.com>
PR target/107453
* calls.cc (expand_call): For calls with
TYPE_NO_NAMED_ARGS_STDARG_P (funtype) use zero for n_named_args.
Formatting fix.
2023-01-09 Richard Biener <rguenther@suse.de>
PR middle-end/69482
* cfgexpand.cc (discover_nonconstant_array_refs_r): Volatile
qualified accesses also force objects to memory.
2023-01-09 Martin Liska <mliska@suse.cz>
PR lto/108330
* lto-cgraph.cc (compute_ltrans_boundary): Do not insert
NULL (deleleted value) to a hash_set.
2023-01-08 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.md (*splice_bits):
New insn_and_split pattern.
2023-01-07 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
* config/xtensa/xtensa.cc
(xtensa_split_imm_two_addends, xtensa_emit_add_imm):
New helper functions.
(xtensa_set_return_address, xtensa_output_mi_thunk):
Change to use the helper function.
(xtensa_emit_adjust_stack_ptr): Ditto.
And also change to try reusing the content of scratch register
A9 if the register is not modified in the function body.
2023-01-07 LIU Hao <lh_mouse@126.com>
PR middle-end/108300
* config/xtensa/xtensa-dynconfig.c: Define `WIN32_LEAN_AND_MEAN`
before <windows.h>.
* diagnostic-color.cc: Likewise.
* plugin.cc: Likewise.
* prefix.cc: Likewise.
2023-01-06 Joseph Myers <joseph@codesourcery.com>
* doc/extend.texi (__builtin_tgmath): Do not restate standard rule
for handling real integer types.
2023-01-06 Tamar Christina <tamar.christina@arm.com>
Revert:
2022-12-12 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64-simd.md (*aarch64_simd_movv2hf): New.
(mov<mode>, movmisalign<mode>, aarch64_dup_lane<mode>,
aarch64_store_lane0<mode>, aarch64_simd_vec_set<mode>,
@aarch64_simd_vec_copy_lane<mode>, vec_set<mode>,
reduc_<optab>_scal_<mode>, reduc_<fmaxmin>_scal_<mode>,
aarch64_reduc_<optab>_internal<mode>, aarch64_get_lane<mode>,
vec_init<mode><Vel>, vec_extract<mode><Vel>): Support V2HF.
(aarch64_simd_dupv2hf): New.
* config/aarch64/aarch64.cc (aarch64_classify_vector_mode):
Add E_V2HFmode.
* config/aarch64/iterators.md (VHSDF_P): New.
(V2F, VMOVE, nunits, Vtype, Vmtype, Vetype, stype, VEL,
Vel, q, vp): Add V2HF.
* config/arm/types.md (neon_fp_reduc_add_h): New.
2023-01-06 Martin Liska <mliska@suse.cz>
PR middle-end/107966
* doc/options.texi: Fix Var documentation in internal manual.
2023-01-05 Roger Sayle <roger@nextmovesoftware.com>
Revert:
2023-01-03 Roger Sayle <roger@nextmovesoftware.com>
* config/i386/i386-expand.cc (ix86_expand_int_movcc): Rewrite
RTL expansion to allow condition (mask) to be shared/reused,
by avoiding overwriting pseudos and adding REG_EQUAL notes.
2023-01-05 Iain Sandoe <iain@sandoe.co.uk>
* common.opt: Add -static-libgm2.
* config/darwin.h (LINK_SPEC): Handle static-libgm2.
* doc/gm2.texi: Document static-libgm2.
* gcc.cc (driver_handle_option): Allow static-libgm2.
2023-01-05 Tejas Joshi <TejasSanjay.Joshi@amd.com>
* common/config/i386/i386-common.cc (processor_alias_table):
Use CPU_ZNVER4 for znver4.
* config/i386/i386.md: Add znver4.md.
* config/i386/znver4.md: New.
2023-01-04 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/108253
* tree-vrp.cc (maybe_set_nonzero_bits): Handle var with pointer
types.
2023-01-04 Jakub Jelinek <jakub@redhat.com>
PR middle-end/108237
* generic-match-head.cc: Include tree-pass.h.
(canonicalize_math_p, optimize_vectors_before_lowering_p): Define
to false if cfun and cfun->curr_properties has PROP_gimple_opt_math
resp. PROP_gimple_lvec property set.
2023-01-04 Jakub Jelinek <jakub@redhat.com>
PR sanitizer/108256
* convert.cc (do_narrow): Punt for MULT_EXPR if original
type doesn't wrap around and -fsanitize=signed-integer-overflow
is on.
* fold-const.cc (fold_unary_loc) <CASE_CONVERT>: Likewise.
2023-01-04 Hu, Lin1 <lin1.hu@intel.com>
* common/config/i386/cpuinfo.h (get_intel_cpu): Handle Emeraldrapids.
* common/config/i386/i386-common.cc: Add Emeraldrapids.
2023-01-04 Hu, Lin1 <lin1.hu@intel.com>
* common/config/i386/cpuinfo.h (get_intel_cpu): Remove case 0xb5
for meteorlake.
2023-01-03 Sandra Loosemore <sandra@codesourcery.com>
* cgraph.h (struct cgraph_node): Add gc_candidate bit, modify
default constructor to initialize it.
* cgraphunit.cc (expand_all_functions): Save gc_candidate functions
for last and iterate to handle recursive calls. Delete leftover
candidates at the end.
* omp-simd-clone.cc (simd_clone_create): Set gc_candidate bit
on local clones.
* tree-vect-stmts.cc (vectorizable_simd_clone_call): Clear
gc_candidate bit when a clone is used.
2023-01-03 Florian Weimer <fweimer@redhat.com>
Revert:
2023-01-02 Florian Weimer <fweimer@redhat.com>
* dwarf2cfi.cc (init_return_column_size): Remove.
(init_one_dwarf_reg_size): Adjust.
(generate_dwarf_reg_sizes): New function. Extracted
from expand_builtin_init_dwarf_reg_sizes.
(expand_builtin_init_dwarf_reg_sizes): Call
generate_dwarf_reg_sizes.
* target.def (init_dwarf_reg_sizes_extra): Adjust
hook signature.
* config/msp430/msp430.cc
(msp430_init_dwarf_reg_sizes_extra): Adjust.
* config/rs6000/rs6000.cc
(rs6000_init_dwarf_reg_sizes_extra): Likewise.
* doc/tm.texi: Update.
2023-01-03 Florian Weimer <fweimer@redhat.com>
Revert:
2023-01-02 Florian Weimer <fweimer@redhat.com>
* debug.h (dwarf_reg_sizes_constant): Declare.
* dwarf2cfi.cc (dwarf_reg_sizes_constant): New function.
2023-01-03 Siddhesh Poyarekar <siddhesh@gotplt.org>
PR tree-optimization/105043
* doc/extend.texi (Object Size Checking): Split out into two
subsections and mention _FORTIFY_SOURCE.
2023-01-03 Roger Sayle <roger@nextmovesoftware.com>
* config/i386/i386-expand.cc (ix86_expand_int_movcc): Rewrite
RTL expansion to allow condition (mask) to be shared/reused,
by avoiding overwriting pseudos and adding REG_EQUAL notes.
2023-01-03 Roger Sayle <roger@nextmovesoftware.com>
PR target/108229
* config/i386/i386-features.cc
(general_scalar_chain::compute_convert_gain) <case PLUS>: Consider
the gain/cost of converting a MEM operand.
2023-01-03 Jakub Jelinek <jakub@redhat.com>
PR middle-end/108264
* expr.cc (store_expr): For stores into SUBREG_PROMOTED_* targets
from source which doesn't have scalar integral mode first convert
it to outer_mode.
2023-01-03 Jakub Jelinek <jakub@redhat.com>
PR rtl-optimization/108263
* cfgrtl.cc (fixup_reorder_chain): Avoid trying to redirect
asm goto to EXIT.
2023-01-02 Alexander Monakov <amonakov@ispras.ru>
PR target/87832
* config/i386/lujiazui.md (lujiazui_div): New automaton.
(lua_div): New unit.
(lua_idiv_qi): Correct unit in the reservation.
(lua_idiv_qi_load): Ditto.
(lua_idiv_hi): Ditto.
(lua_idiv_hi_load): Ditto.
(lua_idiv_si): Ditto.
(lua_idiv_si_load): Ditto.
(lua_idiv_di): Ditto.
(lua_idiv_di_load): Ditto.
(lua_fdiv_SF): Ditto.
(lua_fdiv_SF_load): Ditto.
(lua_fdiv_DF): Ditto.
(lua_fdiv_DF_load): Ditto.
(lua_fdiv_XF): Ditto.
(lua_fdiv_XF_load): Ditto.
(lua_ssediv_SF): Ditto.
(lua_ssediv_load_SF): Ditto.
(lua_ssediv_V4SF): Ditto.
(lua_ssediv_load_V4SF): Ditto.
(lua_ssediv_V8SF): Ditto.
(lua_ssediv_load_V8SF): Ditto.
(lua_ssediv_SD): Ditto.
(lua_ssediv_load_SD): Ditto.
(lua_ssediv_V2DF): Ditto.
(lua_ssediv_load_V2DF): Ditto.
(lua_ssediv_V4DF): Ditto.
(lua_ssediv_load_V4DF): Ditto.
2023-01-02 Florian Weimer <fweimer@redhat.com>
* debug.h (dwarf_reg_sizes_constant): Declare.
* dwarf2cfi.cc (dwarf_reg_sizes_constant): New function.
2023-01-02 Florian Weimer <fweimer@redhat.com>
* dwarf2cfi.cc (init_return_column_size): Remove.
(init_one_dwarf_reg_size): Adjust.
(generate_dwarf_reg_sizes): New function. Extracted
from expand_builtin_init_dwarf_reg_sizes.
(expand_builtin_init_dwarf_reg_sizes): Call
generate_dwarf_reg_sizes.
* target.def (init_dwarf_reg_sizes_extra): Adjust
hook signature.
* config/msp430/msp430.cc
(msp430_init_dwarf_reg_sizes_extra): Adjust.
* config/rs6000/rs6000.cc
(rs6000_init_dwarf_reg_sizes_extra): Likewise.
* doc/tm.texi: Update.
2023-01-02 Jakub Jelinek <jakub@redhat.com>
* gcc.cc (process_command): Update copyright notice dates.
* gcov-dump.cc (print_version): Ditto.
* gcov.cc (print_version): Ditto.
* gcov-tool.cc (print_version): Ditto.
* gengtype.cc (create_file): Ditto.
* doc/cpp.texi: Bump @copying's copyright year.
* doc/cppinternals.texi: Ditto.
* doc/gcc.texi: Ditto.
* doc/gccint.texi: Ditto.
* doc/gcov.texi: Ditto.
* doc/install.texi: Ditto.
* doc/invoke.texi: Ditto.
2023-01-01 Roger Sayle <roger@nextmovesoftware.com>
Uroš Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (extendditi2): New define_insn.
(define_split): Use DWIH mode iterator to treat new extendditi2
identically to existing extendsidi2_1.
(define_peephole2): Likewise.
(define_peephole2): Likewise.
(define_Split): Likewise.
Copyright (C) 2023 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.