blob: 9da601c4f84d651fcaa9aed17509d3e7b9b783f2 [file] [log] [blame]
/* Expand the basic unary and binary arithmetic operations, for GNU compiler.
Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 2, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING. If not, write to the Free
Software Foundation, 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA. */
#include "config.h"
#include "system.h"
#include "toplev.h"
/* Include insn-config.h before expr.h so that HAVE_conditional_move
is properly defined. */
#include "insn-config.h"
#include "rtl.h"
#include "tree.h"
#include "tm_p.h"
#include "flags.h"
#include "function.h"
#include "except.h"
#include "expr.h"
#include "optabs.h"
#include "libfuncs.h"
#include "recog.h"
#include "reload.h"
#include "ggc.h"
#include "real.h"
#include "basic-block.h"
/* Each optab contains info on how this target machine
can perform a particular operation
for all sizes and kinds of operands.
The operation to be performed is often specified
by passing one of these optabs as an argument.
See expr.h for documentation of these optabs. */
optab optab_table[OTI_MAX];
rtx libfunc_table[LTI_MAX];
/* Tables of patterns for extending one integer mode to another. */
enum insn_code extendtab[MAX_MACHINE_MODE][MAX_MACHINE_MODE][2];
/* Tables of patterns for converting between fixed and floating point. */
enum insn_code fixtab[NUM_MACHINE_MODES][NUM_MACHINE_MODES][2];
enum insn_code fixtrunctab[NUM_MACHINE_MODES][NUM_MACHINE_MODES][2];
enum insn_code floattab[NUM_MACHINE_MODES][NUM_MACHINE_MODES][2];
/* Contains the optab used for each rtx code. */
optab code_to_optab[NUM_RTX_CODE + 1];
/* Indexed by the rtx-code for a conditional (eg. EQ, LT,...)
gives the gen_function to make a branch to test that condition. */
rtxfun bcc_gen_fctn[NUM_RTX_CODE];
/* Indexed by the rtx-code for a conditional (eg. EQ, LT,...)
gives the insn code to make a store-condition insn
to test that condition. */
enum insn_code setcc_gen_code[NUM_RTX_CODE];
#ifdef HAVE_conditional_move
/* Indexed by the machine mode, gives the insn code to make a conditional
move insn. This is not indexed by the rtx-code like bcc_gen_fctn and
setcc_gen_code to cut down on the number of named patterns. Consider a day
when a lot more rtx codes are conditional (eg: for the ARM). */
enum insn_code movcc_gen_code[NUM_MACHINE_MODES];
#endif
/* The insn generating function can not take an rtx_code argument.
TRAP_RTX is used as an rtx argument. Its code is replaced with
the code to be used in the trap insn and all other fields are ignored. */
static GTY(()) rtx trap_rtx;
static int add_equal_note PARAMS ((rtx, rtx, enum rtx_code, rtx, rtx));
static rtx widen_operand PARAMS ((rtx, enum machine_mode,
enum machine_mode, int, int));
static int expand_cmplxdiv_straight PARAMS ((rtx, rtx, rtx, rtx,
rtx, rtx, enum machine_mode,
int, enum optab_methods,
enum mode_class, optab));
static int expand_cmplxdiv_wide PARAMS ((rtx, rtx, rtx, rtx,
rtx, rtx, enum machine_mode,
int, enum optab_methods,
enum mode_class, optab));
static void prepare_cmp_insn PARAMS ((rtx *, rtx *, enum rtx_code *, rtx,
enum machine_mode *, int *,
enum can_compare_purpose));
static enum insn_code can_fix_p PARAMS ((enum machine_mode, enum machine_mode,
int, int *));
static enum insn_code can_float_p PARAMS ((enum machine_mode,
enum machine_mode,
int));
static rtx ftruncify PARAMS ((rtx));
static optab new_optab PARAMS ((void));
static inline optab init_optab PARAMS ((enum rtx_code));
static inline optab init_optabv PARAMS ((enum rtx_code));
static void init_libfuncs PARAMS ((optab, int, int, const char *, int));
static void init_integral_libfuncs PARAMS ((optab, const char *, int));
static void init_floating_libfuncs PARAMS ((optab, const char *, int));
static void emit_cmp_and_jump_insn_1 PARAMS ((rtx, rtx, enum machine_mode,
enum rtx_code, int, rtx));
static void prepare_float_lib_cmp PARAMS ((rtx *, rtx *, enum rtx_code *,
enum machine_mode *, int *));
static rtx expand_vector_binop PARAMS ((enum machine_mode, optab,
rtx, rtx, rtx, int,
enum optab_methods));
static rtx expand_vector_unop PARAMS ((enum machine_mode, optab, rtx, rtx,
int));
#ifndef HAVE_conditional_trap
#define HAVE_conditional_trap 0
#define gen_conditional_trap(a,b) (abort (), NULL_RTX)
#endif
/* Add a REG_EQUAL note to the last insn in INSNS. TARGET is being set to
the result of operation CODE applied to OP0 (and OP1 if it is a binary
operation).
If the last insn does not set TARGET, don't do anything, but return 1.
If a previous insn sets TARGET and TARGET is one of OP0 or OP1,
don't add the REG_EQUAL note but return 0. Our caller can then try
again, ensuring that TARGET is not one of the operands. */
static int
add_equal_note (insns, target, code, op0, op1)
rtx insns;
rtx target;
enum rtx_code code;
rtx op0, op1;
{
rtx last_insn, insn, set;
rtx note;
if (! insns
|| ! INSN_P (insns)
|| NEXT_INSN (insns) == NULL_RTX)
abort ();
if (GET_RTX_CLASS (code) != '1' && GET_RTX_CLASS (code) != '2'
&& GET_RTX_CLASS (code) != 'c' && GET_RTX_CLASS (code) != '<')
return 1;
if (GET_CODE (target) == ZERO_EXTRACT)
return 1;
for (last_insn = insns;
NEXT_INSN (last_insn) != NULL_RTX;
last_insn = NEXT_INSN (last_insn))
;
set = single_set (last_insn);
if (set == NULL_RTX)
return 1;
if (! rtx_equal_p (SET_DEST (set), target)
/* For a STRICT_LOW_PART, the REG_NOTE applies to what is inside the
SUBREG. */
&& (GET_CODE (SET_DEST (set)) != STRICT_LOW_PART
|| ! rtx_equal_p (SUBREG_REG (XEXP (SET_DEST (set), 0)),
target)))
return 1;
/* If TARGET is in OP0 or OP1, check if anything in SEQ sets TARGET
besides the last insn. */
if (reg_overlap_mentioned_p (target, op0)
|| (op1 && reg_overlap_mentioned_p (target, op1)))
{
insn = PREV_INSN (last_insn);
while (insn != NULL_RTX)
{
if (reg_set_p (target, insn))
return 0;
insn = PREV_INSN (insn);
}
}
if (GET_RTX_CLASS (code) == '1')
note = gen_rtx_fmt_e (code, GET_MODE (target), copy_rtx (op0));
else
note = gen_rtx_fmt_ee (code, GET_MODE (target), copy_rtx (op0), copy_rtx (op1));
set_unique_reg_note (last_insn, REG_EQUAL, note);
return 1;
}
/* Widen OP to MODE and return the rtx for the widened operand. UNSIGNEDP
says whether OP is signed or unsigned. NO_EXTEND is nonzero if we need
not actually do a sign-extend or zero-extend, but can leave the
higher-order bits of the result rtx undefined, for example, in the case
of logical operations, but not right shifts. */
static rtx
widen_operand (op, mode, oldmode, unsignedp, no_extend)
rtx op;
enum machine_mode mode, oldmode;
int unsignedp;
int no_extend;
{
rtx result;
/* If we don't have to extend and this is a constant, return it. */
if (no_extend && GET_MODE (op) == VOIDmode)
return op;
/* If we must extend do so. If OP is a SUBREG for a promoted object, also
extend since it will be more efficient to do so unless the signedness of
a promoted object differs from our extension. */
if (! no_extend
|| (GET_CODE (op) == SUBREG && SUBREG_PROMOTED_VAR_P (op)
&& SUBREG_PROMOTED_UNSIGNED_P (op) == unsignedp))
return convert_modes (mode, oldmode, op, unsignedp);
/* If MODE is no wider than a single word, we return a paradoxical
SUBREG. */
if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD)
return gen_rtx_SUBREG (mode, force_reg (GET_MODE (op), op), 0);
/* Otherwise, get an object of MODE, clobber it, and set the low-order
part to OP. */
result = gen_reg_rtx (mode);
emit_insn (gen_rtx_CLOBBER (VOIDmode, result));
emit_move_insn (gen_lowpart (GET_MODE (op), result), op);
return result;
}
/* Generate code to perform a straightforward complex divide. */
static int
expand_cmplxdiv_straight (real0, real1, imag0, imag1, realr, imagr, submode,
unsignedp, methods, class, binoptab)
rtx real0, real1, imag0, imag1, realr, imagr;
enum machine_mode submode;
int unsignedp;
enum optab_methods methods;
enum mode_class class;
optab binoptab;
{
rtx divisor;
rtx real_t, imag_t;
rtx temp1, temp2;
rtx res;
optab this_add_optab = add_optab;
optab this_sub_optab = sub_optab;
optab this_neg_optab = neg_optab;
optab this_mul_optab = smul_optab;
if (binoptab == sdivv_optab)
{
this_add_optab = addv_optab;
this_sub_optab = subv_optab;
this_neg_optab = negv_optab;
this_mul_optab = smulv_optab;
}
/* Don't fetch these from memory more than once. */
real0 = force_reg (submode, real0);
real1 = force_reg (submode, real1);
if (imag0 != 0)
imag0 = force_reg (submode, imag0);
imag1 = force_reg (submode, imag1);
/* Divisor: c*c + d*d. */
temp1 = expand_binop (submode, this_mul_optab, real1, real1,
NULL_RTX, unsignedp, methods);
temp2 = expand_binop (submode, this_mul_optab, imag1, imag1,
NULL_RTX, unsignedp, methods);
if (temp1 == 0 || temp2 == 0)
return 0;
divisor = expand_binop (submode, this_add_optab, temp1, temp2,
NULL_RTX, unsignedp, methods);
if (divisor == 0)
return 0;
if (imag0 == 0)
{
/* Mathematically, ((a)(c-id))/divisor. */
/* Computationally, (a+i0) / (c+id) = (ac/(cc+dd)) + i(-ad/(cc+dd)). */
/* Calculate the dividend. */
real_t = expand_binop (submode, this_mul_optab, real0, real1,
NULL_RTX, unsignedp, methods);
imag_t = expand_binop (submode, this_mul_optab, real0, imag1,
NULL_RTX, unsignedp, methods);
if (real_t == 0 || imag_t == 0)
return 0;
imag_t = expand_unop (submode, this_neg_optab, imag_t,
NULL_RTX, unsignedp);
}
else
{
/* Mathematically, ((a+ib)(c-id))/divider. */
/* Calculate the dividend. */
temp1 = expand_binop (submode, this_mul_optab, real0, real1,
NULL_RTX, unsignedp, methods);
temp2 = expand_binop (submode, this_mul_optab, imag0, imag1,
NULL_RTX, unsignedp, methods);
if (temp1 == 0 || temp2 == 0)
return 0;
real_t = expand_binop (submode, this_add_optab, temp1, temp2,
NULL_RTX, unsignedp, methods);
temp1 = expand_binop (submode, this_mul_optab, imag0, real1,
NULL_RTX, unsignedp, methods);
temp2 = expand_binop (submode, this_mul_optab, real0, imag1,
NULL_RTX, unsignedp, methods);
if (temp1 == 0 || temp2 == 0)
return 0;
imag_t = expand_binop (submode, this_sub_optab, temp1, temp2,
NULL_RTX, unsignedp, methods);
if (real_t == 0 || imag_t == 0)
return 0;
}
if (class == MODE_COMPLEX_FLOAT)
res = expand_binop (submode, binoptab, real_t, divisor,
realr, unsignedp, methods);
else
res = expand_divmod (0, TRUNC_DIV_EXPR, submode,
real_t, divisor, realr, unsignedp);
if (res == 0)
return 0;
if (res != realr)
emit_move_insn (realr, res);
if (class == MODE_COMPLEX_FLOAT)
res = expand_binop (submode, binoptab, imag_t, divisor,
imagr, unsignedp, methods);
else
res = expand_divmod (0, TRUNC_DIV_EXPR, submode,
imag_t, divisor, imagr, unsignedp);
if (res == 0)
return 0;
if (res != imagr)
emit_move_insn (imagr, res);
return 1;
}
/* Generate code to perform a wide-input-range-acceptable complex divide. */
static int
expand_cmplxdiv_wide (real0, real1, imag0, imag1, realr, imagr, submode,
unsignedp, methods, class, binoptab)
rtx real0, real1, imag0, imag1, realr, imagr;
enum machine_mode submode;
int unsignedp;
enum optab_methods methods;
enum mode_class class;
optab binoptab;
{
rtx ratio, divisor;
rtx real_t, imag_t;
rtx temp1, temp2, lab1, lab2;
enum machine_mode mode;
rtx res;
optab this_add_optab = add_optab;
optab this_sub_optab = sub_optab;
optab this_neg_optab = neg_optab;
optab this_mul_optab = smul_optab;
if (binoptab == sdivv_optab)
{
this_add_optab = addv_optab;
this_sub_optab = subv_optab;
this_neg_optab = negv_optab;
this_mul_optab = smulv_optab;
}
/* Don't fetch these from memory more than once. */
real0 = force_reg (submode, real0);
real1 = force_reg (submode, real1);
if (imag0 != 0)
imag0 = force_reg (submode, imag0);
imag1 = force_reg (submode, imag1);
/* XXX What's an "unsigned" complex number? */
if (unsignedp)
{
temp1 = real1;
temp2 = imag1;
}
else
{
temp1 = expand_abs (submode, real1, NULL_RTX, unsignedp, 1);
temp2 = expand_abs (submode, imag1, NULL_RTX, unsignedp, 1);
}
if (temp1 == 0 || temp2 == 0)
return 0;
mode = GET_MODE (temp1);
lab1 = gen_label_rtx ();
emit_cmp_and_jump_insns (temp1, temp2, LT, NULL_RTX,
mode, unsignedp, lab1);
/* |c| >= |d|; use ratio d/c to scale dividend and divisor. */
if (class == MODE_COMPLEX_FLOAT)
ratio = expand_binop (submode, binoptab, imag1, real1,
NULL_RTX, unsignedp, methods);
else
ratio = expand_divmod (0, TRUNC_DIV_EXPR, submode,
imag1, real1, NULL_RTX, unsignedp);
if (ratio == 0)
return 0;
/* Calculate divisor. */
temp1 = expand_binop (submode, this_mul_optab, imag1, ratio,
NULL_RTX, unsignedp, methods);
if (temp1 == 0)
return 0;
divisor = expand_binop (submode, this_add_optab, temp1, real1,
NULL_RTX, unsignedp, methods);
if (divisor == 0)
return 0;
/* Calculate dividend. */
if (imag0 == 0)
{
real_t = real0;
/* Compute a / (c+id) as a / (c+d(d/c)) + i (-a(d/c)) / (c+d(d/c)). */
imag_t = expand_binop (submode, this_mul_optab, real0, ratio,
NULL_RTX, unsignedp, methods);
if (imag_t == 0)
return 0;
imag_t = expand_unop (submode, this_neg_optab, imag_t,
NULL_RTX, unsignedp);
if (real_t == 0 || imag_t == 0)
return 0;
}
else
{
/* Compute (a+ib)/(c+id) as
(a+b(d/c))/(c+d(d/c) + i(b-a(d/c))/(c+d(d/c)). */
temp1 = expand_binop (submode, this_mul_optab, imag0, ratio,
NULL_RTX, unsignedp, methods);
if (temp1 == 0)
return 0;
real_t = expand_binop (submode, this_add_optab, temp1, real0,
NULL_RTX, unsignedp, methods);
temp1 = expand_binop (submode, this_mul_optab, real0, ratio,
NULL_RTX, unsignedp, methods);
if (temp1 == 0)
return 0;
imag_t = expand_binop (submode, this_sub_optab, imag0, temp1,
NULL_RTX, unsignedp, methods);
if (real_t == 0 || imag_t == 0)
return 0;
}
if (class == MODE_COMPLEX_FLOAT)
res = expand_binop (submode, binoptab, real_t, divisor,
realr, unsignedp, methods);
else
res = expand_divmod (0, TRUNC_DIV_EXPR, submode,
real_t, divisor, realr, unsignedp);
if (res == 0)
return 0;
if (res != realr)
emit_move_insn (realr, res);
if (class == MODE_COMPLEX_FLOAT)
res = expand_binop (submode, binoptab, imag_t, divisor,
imagr, unsignedp, methods);
else
res = expand_divmod (0, TRUNC_DIV_EXPR, submode,
imag_t, divisor, imagr, unsignedp);
if (res == 0)
return 0;
if (res != imagr)
emit_move_insn (imagr, res);
lab2 = gen_label_rtx ();
emit_jump_insn (gen_jump (lab2));
emit_barrier ();
emit_label (lab1);
/* |d| > |c|; use ratio c/d to scale dividend and divisor. */
if (class == MODE_COMPLEX_FLOAT)
ratio = expand_binop (submode, binoptab, real1, imag1,
NULL_RTX, unsignedp, methods);
else
ratio = expand_divmod (0, TRUNC_DIV_EXPR, submode,
real1, imag1, NULL_RTX, unsignedp);
if (ratio == 0)
return 0;
/* Calculate divisor. */
temp1 = expand_binop (submode, this_mul_optab, real1, ratio,
NULL_RTX, unsignedp, methods);
if (temp1 == 0)
return 0;
divisor = expand_binop (submode, this_add_optab, temp1, imag1,
NULL_RTX, unsignedp, methods);
if (divisor == 0)
return 0;
/* Calculate dividend. */
if (imag0 == 0)
{
/* Compute a / (c+id) as a(c/d) / (c(c/d)+d) + i (-a) / (c(c/d)+d). */
real_t = expand_binop (submode, this_mul_optab, real0, ratio,
NULL_RTX, unsignedp, methods);
imag_t = expand_unop (submode, this_neg_optab, real0,
NULL_RTX, unsignedp);
if (real_t == 0 || imag_t == 0)
return 0;
}
else
{
/* Compute (a+ib)/(c+id) as
(a(c/d)+b)/(c(c/d)+d) + i (b(c/d)-a)/(c(c/d)+d). */
temp1 = expand_binop (submode, this_mul_optab, real0, ratio,
NULL_RTX, unsignedp, methods);
if (temp1 == 0)
return 0;
real_t = expand_binop (submode, this_add_optab, temp1, imag0,
NULL_RTX, unsignedp, methods);
temp1 = expand_binop (submode, this_mul_optab, imag0, ratio,
NULL_RTX, unsignedp, methods);
if (temp1 == 0)
return 0;
imag_t = expand_binop (submode, this_sub_optab, temp1, real0,
NULL_RTX, unsignedp, methods);
if (real_t == 0 || imag_t == 0)
return 0;
}
if (class == MODE_COMPLEX_FLOAT)
res = expand_binop (submode, binoptab, real_t, divisor,
realr, unsignedp, methods);
else
res = expand_divmod (0, TRUNC_DIV_EXPR, submode,
real_t, divisor, realr, unsignedp);
if (res == 0)
return 0;
if (res != realr)
emit_move_insn (realr, res);
if (class == MODE_COMPLEX_FLOAT)
res = expand_binop (submode, binoptab, imag_t, divisor,
imagr, unsignedp, methods);
else
res = expand_divmod (0, TRUNC_DIV_EXPR, submode,
imag_t, divisor, imagr, unsignedp);
if (res == 0)
return 0;
if (res != imagr)
emit_move_insn (imagr, res);
emit_label (lab2);
return 1;
}
/* Wrapper around expand_binop which takes an rtx code to specify
the operation to perform, not an optab pointer. All other
arguments are the same. */
rtx
expand_simple_binop (mode, code, op0, op1, target, unsignedp, methods)
enum machine_mode mode;
enum rtx_code code;
rtx op0, op1;
rtx target;
int unsignedp;
enum optab_methods methods;
{
optab binop = code_to_optab[(int) code];
if (binop == 0)
abort ();
return expand_binop (mode, binop, op0, op1, target, unsignedp, methods);
}
/* Generate code to perform an operation specified by BINOPTAB
on operands OP0 and OP1, with result having machine-mode MODE.
UNSIGNEDP is for the case where we have to widen the operands
to perform the operation. It says to use zero-extension.
If TARGET is nonzero, the value
is generated there, if it is convenient to do so.
In all cases an rtx is returned for the locus of the value;
this may or may not be TARGET. */
rtx
expand_binop (mode, binoptab, op0, op1, target, unsignedp, methods)
enum machine_mode mode;
optab binoptab;
rtx op0, op1;
rtx target;
int unsignedp;
enum optab_methods methods;
{
enum optab_methods next_methods
= (methods == OPTAB_LIB || methods == OPTAB_LIB_WIDEN
? OPTAB_WIDEN : methods);
enum mode_class class;
enum machine_mode wider_mode;
rtx temp;
int commutative_op = 0;
int shift_op = (binoptab->code == ASHIFT
|| binoptab->code == ASHIFTRT
|| binoptab->code == LSHIFTRT
|| binoptab->code == ROTATE
|| binoptab->code == ROTATERT);
rtx entry_last = get_last_insn ();
rtx last;
class = GET_MODE_CLASS (mode);
op0 = protect_from_queue (op0, 0);
op1 = protect_from_queue (op1, 0);
if (target)
target = protect_from_queue (target, 1);
if (flag_force_mem)
{
op0 = force_not_mem (op0);
op1 = force_not_mem (op1);
}
/* If subtracting an integer constant, convert this into an addition of
the negated constant. */
if (binoptab == sub_optab && GET_CODE (op1) == CONST_INT)
{
op1 = negate_rtx (mode, op1);
binoptab = add_optab;
}
/* If we are inside an appropriately-short loop and one operand is an
expensive constant, force it into a register. */
if (CONSTANT_P (op0) && preserve_subexpressions_p ()
&& rtx_cost (op0, binoptab->code) > COSTS_N_INSNS (1))
op0 = force_reg (mode, op0);
if (CONSTANT_P (op1) && preserve_subexpressions_p ()
&& ! shift_op && rtx_cost (op1, binoptab->code) > COSTS_N_INSNS (1))
op1 = force_reg (mode, op1);
/* Record where to delete back to if we backtrack. */
last = get_last_insn ();
/* If operation is commutative,
try to make the first operand a register.
Even better, try to make it the same as the target.
Also try to make the last operand a constant. */
if (GET_RTX_CLASS (binoptab->code) == 'c'
|| binoptab == smul_widen_optab
|| binoptab == umul_widen_optab
|| binoptab == smul_highpart_optab
|| binoptab == umul_highpart_optab)
{
commutative_op = 1;
if (((target == 0 || GET_CODE (target) == REG)
? ((GET_CODE (op1) == REG
&& GET_CODE (op0) != REG)
|| target == op1)
: rtx_equal_p (op1, target))
|| GET_CODE (op0) == CONST_INT)
{
temp = op1;
op1 = op0;
op0 = temp;
}
}
/* If we can do it with a three-operand insn, do so. */
if (methods != OPTAB_MUST_WIDEN
&& binoptab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
{
int icode = (int) binoptab->handlers[(int) mode].insn_code;
enum machine_mode mode0 = insn_data[icode].operand[1].mode;
enum machine_mode mode1 = insn_data[icode].operand[2].mode;
rtx pat;
rtx xop0 = op0, xop1 = op1;
if (target)
temp = target;
else
temp = gen_reg_rtx (mode);
/* If it is a commutative operator and the modes would match
if we would swap the operands, we can save the conversions. */
if (commutative_op)
{
if (GET_MODE (op0) != mode0 && GET_MODE (op1) != mode1
&& GET_MODE (op0) == mode1 && GET_MODE (op1) == mode0)
{
rtx tmp;
tmp = op0; op0 = op1; op1 = tmp;
tmp = xop0; xop0 = xop1; xop1 = tmp;
}
}
/* In case the insn wants input operands in modes different from
those of the actual operands, convert the operands. It would
seem that we don't need to convert CONST_INTs, but we do, so
that they're properly zero-extended, sign-extended or truncated
for their mode. */
if (GET_MODE (op0) != mode0 && mode0 != VOIDmode)
xop0 = convert_modes (mode0,
GET_MODE (op0) != VOIDmode
? GET_MODE (op0)
: mode,
xop0, unsignedp);
if (GET_MODE (op1) != mode1 && mode1 != VOIDmode)
xop1 = convert_modes (mode1,
GET_MODE (op1) != VOIDmode
? GET_MODE (op1)
: mode,
xop1, unsignedp);
/* Now, if insn's predicates don't allow our operands, put them into
pseudo regs. */
if (! (*insn_data[icode].operand[1].predicate) (xop0, mode0)
&& mode0 != VOIDmode)
xop0 = copy_to_mode_reg (mode0, xop0);
if (! (*insn_data[icode].operand[2].predicate) (xop1, mode1)
&& mode1 != VOIDmode)
xop1 = copy_to_mode_reg (mode1, xop1);
if (! (*insn_data[icode].operand[0].predicate) (temp, mode))
temp = gen_reg_rtx (mode);
pat = GEN_FCN (icode) (temp, xop0, xop1);
if (pat)
{
/* If PAT is composed of more than one insn, try to add an appropriate
REG_EQUAL note to it. If we can't because TEMP conflicts with an
operand, call ourselves again, this time without a target. */
if (INSN_P (pat) && NEXT_INSN (pat) != NULL_RTX
&& ! add_equal_note (pat, temp, binoptab->code, xop0, xop1))
{
delete_insns_since (last);
return expand_binop (mode, binoptab, op0, op1, NULL_RTX,
unsignedp, methods);
}
emit_insn (pat);
return temp;
}
else
delete_insns_since (last);
}
/* If this is a multiply, see if we can do a widening operation that
takes operands of this mode and makes a wider mode. */
if (binoptab == smul_optab && GET_MODE_WIDER_MODE (mode) != VOIDmode
&& (((unsignedp ? umul_widen_optab : smul_widen_optab)
->handlers[(int) GET_MODE_WIDER_MODE (mode)].insn_code)
!= CODE_FOR_nothing))
{
temp = expand_binop (GET_MODE_WIDER_MODE (mode),
unsignedp ? umul_widen_optab : smul_widen_optab,
op0, op1, NULL_RTX, unsignedp, OPTAB_DIRECT);
if (temp != 0)
{
if (GET_MODE_CLASS (mode) == MODE_INT)
return gen_lowpart (mode, temp);
else
return convert_to_mode (mode, temp, unsignedp);
}
}
/* Look for a wider mode of the same class for which we think we
can open-code the operation. Check for a widening multiply at the
wider mode as well. */
if ((class == MODE_INT || class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT)
&& methods != OPTAB_DIRECT && methods != OPTAB_LIB)
for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode;
wider_mode = GET_MODE_WIDER_MODE (wider_mode))
{
if (binoptab->handlers[(int) wider_mode].insn_code != CODE_FOR_nothing
|| (binoptab == smul_optab
&& GET_MODE_WIDER_MODE (wider_mode) != VOIDmode
&& (((unsignedp ? umul_widen_optab : smul_widen_optab)
->handlers[(int) GET_MODE_WIDER_MODE (wider_mode)].insn_code)
!= CODE_FOR_nothing)))
{
rtx xop0 = op0, xop1 = op1;
int no_extend = 0;
/* For certain integer operations, we need not actually extend
the narrow operands, as long as we will truncate
the results to the same narrowness. */
if ((binoptab == ior_optab || binoptab == and_optab
|| binoptab == xor_optab
|| binoptab == add_optab || binoptab == sub_optab
|| binoptab == smul_optab || binoptab == ashl_optab)
&& class == MODE_INT)
no_extend = 1;
xop0 = widen_operand (xop0, wider_mode, mode, unsignedp, no_extend);
/* The second operand of a shift must always be extended. */
xop1 = widen_operand (xop1, wider_mode, mode, unsignedp,
no_extend && binoptab != ashl_optab);
temp = expand_binop (wider_mode, binoptab, xop0, xop1, NULL_RTX,
unsignedp, OPTAB_DIRECT);
if (temp)
{
if (class != MODE_INT)
{
if (target == 0)
target = gen_reg_rtx (mode);
convert_move (target, temp, 0);
return target;
}
else
return gen_lowpart (mode, temp);
}
else
delete_insns_since (last);
}
}
/* These can be done a word at a time. */
if ((binoptab == and_optab || binoptab == ior_optab || binoptab == xor_optab)
&& class == MODE_INT
&& GET_MODE_SIZE (mode) > UNITS_PER_WORD
&& binoptab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing)
{
int i;
rtx insns;
rtx equiv_value;
/* If TARGET is the same as one of the operands, the REG_EQUAL note
won't be accurate, so use a new target. */
if (target == 0 || target == op0 || target == op1)
target = gen_reg_rtx (mode);
start_sequence ();
/* Do the actual arithmetic. */
for (i = 0; i < GET_MODE_BITSIZE (mode) / BITS_PER_WORD; i++)
{
rtx target_piece = operand_subword (target, i, 1, mode);
rtx x = expand_binop (word_mode, binoptab,
operand_subword_force (op0, i, mode),
operand_subword_force (op1, i, mode),
target_piece, unsignedp, next_methods);
if (x == 0)
break;
if (target_piece != x)
emit_move_insn (target_piece, x);
}
insns = get_insns ();
end_sequence ();
if (i == GET_MODE_BITSIZE (mode) / BITS_PER_WORD)
{
if (binoptab->code != UNKNOWN)
equiv_value
= gen_rtx_fmt_ee (binoptab->code, mode,
copy_rtx (op0), copy_rtx (op1));
else
equiv_value = 0;
emit_no_conflict_block (insns, target, op0, op1, equiv_value);
return target;
}
}
/* Synthesize double word shifts from single word shifts. */
if ((binoptab == lshr_optab || binoptab == ashl_optab
|| binoptab == ashr_optab)
&& class == MODE_INT
&& GET_CODE (op1) == CONST_INT
&& GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD
&& binoptab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing
&& ashl_optab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing
&& lshr_optab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing)
{
rtx insns, inter, equiv_value;
rtx into_target, outof_target;
rtx into_input, outof_input;
int shift_count, left_shift, outof_word;
/* If TARGET is the same as one of the operands, the REG_EQUAL note
won't be accurate, so use a new target. */
if (target == 0 || target == op0 || target == op1)
target = gen_reg_rtx (mode);
start_sequence ();
shift_count = INTVAL (op1);
/* OUTOF_* is the word we are shifting bits away from, and
INTO_* is the word that we are shifting bits towards, thus
they differ depending on the direction of the shift and
WORDS_BIG_ENDIAN. */
left_shift = binoptab == ashl_optab;
outof_word = left_shift ^ ! WORDS_BIG_ENDIAN;
outof_target = operand_subword (target, outof_word, 1, mode);
into_target = operand_subword (target, 1 - outof_word, 1, mode);
outof_input = operand_subword_force (op0, outof_word, mode);
into_input = operand_subword_force (op0, 1 - outof_word, mode);
if (shift_count >= BITS_PER_WORD)
{
inter = expand_binop (word_mode, binoptab,
outof_input,
GEN_INT (shift_count - BITS_PER_WORD),
into_target, unsignedp, next_methods);
if (inter != 0 && inter != into_target)
emit_move_insn (into_target, inter);
/* For a signed right shift, we must fill the word we are shifting
out of with copies of the sign bit. Otherwise it is zeroed. */
if (inter != 0 && binoptab != ashr_optab)
inter = CONST0_RTX (word_mode);
else if (inter != 0)
inter = expand_binop (word_mode, binoptab,
outof_input,
GEN_INT (BITS_PER_WORD - 1),
outof_target, unsignedp, next_methods);
if (inter != 0 && inter != outof_target)
emit_move_insn (outof_target, inter);
}
else
{
rtx carries;
optab reverse_unsigned_shift, unsigned_shift;
/* For a shift of less then BITS_PER_WORD, to compute the carry,
we must do a logical shift in the opposite direction of the
desired shift. */
reverse_unsigned_shift = (left_shift ? lshr_optab : ashl_optab);
/* For a shift of less than BITS_PER_WORD, to compute the word
shifted towards, we need to unsigned shift the orig value of
that word. */
unsigned_shift = (left_shift ? ashl_optab : lshr_optab);
carries = expand_binop (word_mode, reverse_unsigned_shift,
outof_input,
GEN_INT (BITS_PER_WORD - shift_count),
0, unsignedp, next_methods);
if (carries == 0)
inter = 0;
else
inter = expand_binop (word_mode, unsigned_shift, into_input,
op1, 0, unsignedp, next_methods);
if (inter != 0)
inter = expand_binop (word_mode, ior_optab, carries, inter,
into_target, unsignedp, next_methods);
if (inter != 0 && inter != into_target)
emit_move_insn (into_target, inter);
if (inter != 0)
inter = expand_binop (word_mode, binoptab, outof_input,
op1, outof_target, unsignedp, next_methods);
if (inter != 0 && inter != outof_target)
emit_move_insn (outof_target, inter);
}
insns = get_insns ();
end_sequence ();
if (inter != 0)
{
if (binoptab->code != UNKNOWN)
equiv_value = gen_rtx_fmt_ee (binoptab->code, mode, op0, op1);
else
equiv_value = 0;
emit_no_conflict_block (insns, target, op0, op1, equiv_value);
return target;
}
}
/* Synthesize double word rotates from single word shifts. */
if ((binoptab == rotl_optab || binoptab == rotr_optab)
&& class == MODE_INT
&& GET_CODE (op1) == CONST_INT
&& GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD
&& ashl_optab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing
&& lshr_optab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing)
{
rtx insns, equiv_value;
rtx into_target, outof_target;
rtx into_input, outof_input;
rtx inter;
int shift_count, left_shift, outof_word;
/* If TARGET is the same as one of the operands, the REG_EQUAL note
won't be accurate, so use a new target. */
if (target == 0 || target == op0 || target == op1)
target = gen_reg_rtx (mode);
start_sequence ();
shift_count = INTVAL (op1);
/* OUTOF_* is the word we are shifting bits away from, and
INTO_* is the word that we are shifting bits towards, thus
they differ depending on the direction of the shift and
WORDS_BIG_ENDIAN. */
left_shift = (binoptab == rotl_optab);
outof_word = left_shift ^ ! WORDS_BIG_ENDIAN;
outof_target = operand_subword (target, outof_word, 1, mode);
into_target = operand_subword (target, 1 - outof_word, 1, mode);
outof_input = operand_subword_force (op0, outof_word, mode);
into_input = operand_subword_force (op0, 1 - outof_word, mode);
if (shift_count == BITS_PER_WORD)
{
/* This is just a word swap. */
emit_move_insn (outof_target, into_input);
emit_move_insn (into_target, outof_input);
inter = const0_rtx;
}
else
{
rtx into_temp1, into_temp2, outof_temp1, outof_temp2;
rtx first_shift_count, second_shift_count;
optab reverse_unsigned_shift, unsigned_shift;
reverse_unsigned_shift = (left_shift ^ (shift_count < BITS_PER_WORD)
? lshr_optab : ashl_optab);
unsigned_shift = (left_shift ^ (shift_count < BITS_PER_WORD)
? ashl_optab : lshr_optab);
if (shift_count > BITS_PER_WORD)
{
first_shift_count = GEN_INT (shift_count - BITS_PER_WORD);
second_shift_count = GEN_INT (2 * BITS_PER_WORD - shift_count);
}
else
{
first_shift_count = GEN_INT (BITS_PER_WORD - shift_count);
second_shift_count = GEN_INT (shift_count);
}
into_temp1 = expand_binop (word_mode, unsigned_shift,
outof_input, first_shift_count,
NULL_RTX, unsignedp, next_methods);
into_temp2 = expand_binop (word_mode, reverse_unsigned_shift,
into_input, second_shift_count,
NULL_RTX, unsignedp, next_methods);
if (into_temp1 != 0 && into_temp2 != 0)
inter = expand_binop (word_mode, ior_optab, into_temp1, into_temp2,
into_target, unsignedp, next_methods);
else
inter = 0;
if (inter != 0 && inter != into_target)
emit_move_insn (into_target, inter);
outof_temp1 = expand_binop (word_mode, unsigned_shift,
into_input, first_shift_count,
NULL_RTX, unsignedp, next_methods);
outof_temp2 = expand_binop (word_mode, reverse_unsigned_shift,
outof_input, second_shift_count,
NULL_RTX, unsignedp, next_methods);
if (inter != 0 && outof_temp1 != 0 && outof_temp2 != 0)
inter = expand_binop (word_mode, ior_optab,
outof_temp1, outof_temp2,
outof_target, unsignedp, next_methods);
if (inter != 0 && inter != outof_target)
emit_move_insn (outof_target, inter);
}
insns = get_insns ();
end_sequence ();
if (inter != 0)
{
if (binoptab->code != UNKNOWN)
equiv_value = gen_rtx_fmt_ee (binoptab->code, mode, op0, op1);
else
equiv_value = 0;
/* We can't make this a no conflict block if this is a word swap,
because the word swap case fails if the input and output values
are in the same register. */
if (shift_count != BITS_PER_WORD)
emit_no_conflict_block (insns, target, op0, op1, equiv_value);
else
emit_insn (insns);
return target;
}
}
/* These can be done a word at a time by propagating carries. */
if ((binoptab == add_optab || binoptab == sub_optab)
&& class == MODE_INT
&& GET_MODE_SIZE (mode) >= 2 * UNITS_PER_WORD
&& binoptab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing)
{
unsigned int i;
optab otheroptab = binoptab == add_optab ? sub_optab : add_optab;
const unsigned int nwords = GET_MODE_BITSIZE (mode) / BITS_PER_WORD;
rtx carry_in = NULL_RTX, carry_out = NULL_RTX;
rtx xop0, xop1, xtarget;
/* We can handle either a 1 or -1 value for the carry. If STORE_FLAG
value is one of those, use it. Otherwise, use 1 since it is the
one easiest to get. */
#if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1
int normalizep = STORE_FLAG_VALUE;
#else
int normalizep = 1;
#endif
/* Prepare the operands. */
xop0 = force_reg (mode, op0);
xop1 = force_reg (mode, op1);
xtarget = gen_reg_rtx (mode);
if (target == 0 || GET_CODE (target) != REG)
target = xtarget;
/* Indicate for flow that the entire target reg is being set. */
if (GET_CODE (target) == REG)
emit_insn (gen_rtx_CLOBBER (VOIDmode, xtarget));
/* Do the actual arithmetic. */
for (i = 0; i < nwords; i++)
{
int index = (WORDS_BIG_ENDIAN ? nwords - i - 1 : i);
rtx target_piece = operand_subword (xtarget, index, 1, mode);
rtx op0_piece = operand_subword_force (xop0, index, mode);
rtx op1_piece = operand_subword_force (xop1, index, mode);
rtx x;
/* Main add/subtract of the input operands. */
x = expand_binop (word_mode, binoptab,
op0_piece, op1_piece,
target_piece, unsignedp, next_methods);
if (x == 0)
break;
if (i + 1 < nwords)
{
/* Store carry from main add/subtract. */
carry_out = gen_reg_rtx (word_mode);
carry_out = emit_store_flag_force (carry_out,
(binoptab == add_optab
? LT : GT),
x, op0_piece,
word_mode, 1, normalizep);
}
if (i > 0)
{
rtx newx;
/* Add/subtract previous carry to main result. */
newx = expand_binop (word_mode,
normalizep == 1 ? binoptab : otheroptab,
x, carry_in,
NULL_RTX, 1, next_methods);
if (i + 1 < nwords)
{
/* Get out carry from adding/subtracting carry in. */
rtx carry_tmp = gen_reg_rtx (word_mode);
carry_tmp = emit_store_flag_force (carry_tmp,
(binoptab == add_optab
? LT : GT),
newx, x,
word_mode, 1, normalizep);
/* Logical-ior the two poss. carry together. */
carry_out = expand_binop (word_mode, ior_optab,
carry_out, carry_tmp,
carry_out, 0, next_methods);
if (carry_out == 0)
break;
}
emit_move_insn (target_piece, newx);
}
carry_in = carry_out;
}
if (i == GET_MODE_BITSIZE (mode) / (unsigned) BITS_PER_WORD)
{
if (mov_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
{
rtx temp = emit_move_insn (target, xtarget);
set_unique_reg_note (temp,
REG_EQUAL,
gen_rtx_fmt_ee (binoptab->code, mode,
copy_rtx (xop0),
copy_rtx (xop1)));
}
else
target = xtarget;
return target;
}
else
delete_insns_since (last);
}
/* If we want to multiply two two-word values and have normal and widening
multiplies of single-word values, we can do this with three smaller
multiplications. Note that we do not make a REG_NO_CONFLICT block here
because we are not operating on one word at a time.
The multiplication proceeds as follows:
_______________________
[__op0_high_|__op0_low__]
_______________________
* [__op1_high_|__op1_low__]
_______________________________________________
_______________________
(1) [__op0_low__*__op1_low__]
_______________________
(2a) [__op0_low__*__op1_high_]
_______________________
(2b) [__op0_high_*__op1_low__]
_______________________
(3) [__op0_high_*__op1_high_]
This gives a 4-word result. Since we are only interested in the
lower 2 words, partial result (3) and the upper words of (2a) and
(2b) don't need to be calculated. Hence (2a) and (2b) can be
calculated using non-widening multiplication.
(1), however, needs to be calculated with an unsigned widening
multiplication. If this operation is not directly supported we
try using a signed widening multiplication and adjust the result.
This adjustment works as follows:
If both operands are positive then no adjustment is needed.
If the operands have different signs, for example op0_low < 0 and
op1_low >= 0, the instruction treats the most significant bit of
op0_low as a sign bit instead of a bit with significance
2**(BITS_PER_WORD-1), i.e. the instruction multiplies op1_low
with 2**BITS_PER_WORD - op0_low, and two's complements the
result. Conclusion: We need to add op1_low * 2**BITS_PER_WORD to
the result.
Similarly, if both operands are negative, we need to add
(op0_low + op1_low) * 2**BITS_PER_WORD.
We use a trick to adjust quickly. We logically shift op0_low right
(op1_low) BITS_PER_WORD-1 steps to get 0 or 1, and add this to
op0_high (op1_high) before it is used to calculate 2b (2a). If no
logical shift exists, we do an arithmetic right shift and subtract
the 0 or -1. */
if (binoptab == smul_optab
&& class == MODE_INT
&& GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD
&& smul_optab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing
&& add_optab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing
&& ((umul_widen_optab->handlers[(int) mode].insn_code
!= CODE_FOR_nothing)
|| (smul_widen_optab->handlers[(int) mode].insn_code
!= CODE_FOR_nothing)))
{
int low = (WORDS_BIG_ENDIAN ? 1 : 0);
int high = (WORDS_BIG_ENDIAN ? 0 : 1);
rtx op0_high = operand_subword_force (op0, high, mode);
rtx op0_low = operand_subword_force (op0, low, mode);
rtx op1_high = operand_subword_force (op1, high, mode);
rtx op1_low = operand_subword_force (op1, low, mode);
rtx product = 0;
rtx op0_xhigh = NULL_RTX;
rtx op1_xhigh = NULL_RTX;
/* If the target is the same as one of the inputs, don't use it. This
prevents problems with the REG_EQUAL note. */
if (target == op0 || target == op1
|| (target != 0 && GET_CODE (target) != REG))
target = 0;
/* Multiply the two lower words to get a double-word product.
If unsigned widening multiplication is available, use that;
otherwise use the signed form and compensate. */
if (umul_widen_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
{
product = expand_binop (mode, umul_widen_optab, op0_low, op1_low,
target, 1, OPTAB_DIRECT);
/* If we didn't succeed, delete everything we did so far. */
if (product == 0)
delete_insns_since (last);
else
op0_xhigh = op0_high, op1_xhigh = op1_high;
}
if (product == 0
&& smul_widen_optab->handlers[(int) mode].insn_code
!= CODE_FOR_nothing)
{
rtx wordm1 = GEN_INT (BITS_PER_WORD - 1);
product = expand_binop (mode, smul_widen_optab, op0_low, op1_low,
target, 1, OPTAB_DIRECT);
op0_xhigh = expand_binop (word_mode, lshr_optab, op0_low, wordm1,
NULL_RTX, 1, next_methods);
if (op0_xhigh)
op0_xhigh = expand_binop (word_mode, add_optab, op0_high,
op0_xhigh, op0_xhigh, 0, next_methods);
else
{
op0_xhigh = expand_binop (word_mode, ashr_optab, op0_low, wordm1,
NULL_RTX, 0, next_methods);
if (op0_xhigh)
op0_xhigh = expand_binop (word_mode, sub_optab, op0_high,
op0_xhigh, op0_xhigh, 0,
next_methods);
}
op1_xhigh = expand_binop (word_mode, lshr_optab, op1_low, wordm1,
NULL_RTX, 1, next_methods);
if (op1_xhigh)
op1_xhigh = expand_binop (word_mode, add_optab, op1_high,
op1_xhigh, op1_xhigh, 0, next_methods);
else
{
op1_xhigh = expand_binop (word_mode, ashr_optab, op1_low, wordm1,
NULL_RTX, 0, next_methods);
if (op1_xhigh)
op1_xhigh = expand_binop (word_mode, sub_optab, op1_high,
op1_xhigh, op1_xhigh, 0,
next_methods);
}
}
/* If we have been able to directly compute the product of the
low-order words of the operands and perform any required adjustments
of the operands, we proceed by trying two more multiplications
and then computing the appropriate sum.
We have checked above that the required addition is provided.
Full-word addition will normally always succeed, especially if
it is provided at all, so we don't worry about its failure. The
multiplication may well fail, however, so we do handle that. */
if (product && op0_xhigh && op1_xhigh)
{
rtx product_high = operand_subword (product, high, 1, mode);
rtx temp = expand_binop (word_mode, binoptab, op0_low, op1_xhigh,
NULL_RTX, 0, OPTAB_DIRECT);
if (!REG_P (product_high))
product_high = force_reg (word_mode, product_high);
if (temp != 0)
temp = expand_binop (word_mode, add_optab, temp, product_high,
product_high, 0, next_methods);
if (temp != 0 && temp != product_high)
emit_move_insn (product_high, temp);
if (temp != 0)
temp = expand_binop (word_mode, binoptab, op1_low, op0_xhigh,
NULL_RTX, 0, OPTAB_DIRECT);
if (temp != 0)
temp = expand_binop (word_mode, add_optab, temp,
product_high, product_high,
0, next_methods);
if (temp != 0 && temp != product_high)
emit_move_insn (product_high, temp);
emit_move_insn (operand_subword (product, high, 1, mode), product_high);
if (temp != 0)
{
if (mov_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
{
temp = emit_move_insn (product, product);
set_unique_reg_note (temp,
REG_EQUAL,
gen_rtx_fmt_ee (MULT, mode,
copy_rtx (op0),
copy_rtx (op1)));
}
return product;
}
}
/* If we get here, we couldn't do it for some reason even though we
originally thought we could. Delete anything we've emitted in
trying to do it. */
delete_insns_since (last);
}
/* Open-code the vector operations if we have no hardware support
for them. */
if (class == MODE_VECTOR_INT || class == MODE_VECTOR_FLOAT)
return expand_vector_binop (mode, binoptab, op0, op1, target,
unsignedp, methods);
/* We need to open-code the complex type operations: '+, -, * and /' */
/* At this point we allow operations between two similar complex
numbers, and also if one of the operands is not a complex number
but rather of MODE_FLOAT or MODE_INT. However, the caller
must make sure that the MODE of the non-complex operand matches
the SUBMODE of the complex operand. */
if (class == MODE_COMPLEX_FLOAT || class == MODE_COMPLEX_INT)
{
rtx real0 = 0, imag0 = 0;
rtx real1 = 0, imag1 = 0;
rtx realr, imagr, res;
rtx seq;
rtx equiv_value;
int ok = 0;
/* Find the correct mode for the real and imaginary parts */
enum machine_mode submode = GET_MODE_INNER(mode);
if (submode == BLKmode)
abort ();
if (! target)
target = gen_reg_rtx (mode);
start_sequence ();
realr = gen_realpart (submode, target);
imagr = gen_imagpart (submode, target);
if (GET_MODE (op0) == mode)
{
real0 = gen_realpart (submode, op0);
imag0 = gen_imagpart (submode, op0);
}
else
real0 = op0;
if (GET_MODE (op1) == mode)
{
real1 = gen_realpart (submode, op1);
imag1 = gen_imagpart (submode, op1);
}
else
real1 = op1;
if (real0 == 0 || real1 == 0 || ! (imag0 != 0 || imag1 != 0))
abort ();
switch (binoptab->code)
{
case PLUS:
/* (a+ib) + (c+id) = (a+c) + i(b+d) */
case MINUS:
/* (a+ib) - (c+id) = (a-c) + i(b-d) */
res = expand_binop (submode, binoptab, real0, real1,
realr, unsignedp, methods);
if (res == 0)
break;
else if (res != realr)
emit_move_insn (realr, res);
if (imag0 != 0 && imag1 != 0)
res = expand_binop (submode, binoptab, imag0, imag1,
imagr, unsignedp, methods);
else if (imag0 != 0)
res = imag0;
else if (binoptab->code == MINUS)
res = expand_unop (submode,
binoptab == subv_optab ? negv_optab : neg_optab,
imag1, imagr, unsignedp);
else
res = imag1;
if (res == 0)
break;
else if (res != imagr)
emit_move_insn (imagr, res);
ok = 1;
break;
case MULT:
/* (a+ib) * (c+id) = (ac-bd) + i(ad+cb) */
if (imag0 != 0 && imag1 != 0)
{
rtx temp1, temp2;
/* Don't fetch these from memory more than once. */
real0 = force_reg (submode, real0);
real1 = force_reg (submode, real1);
imag0 = force_reg (submode, imag0);
imag1 = force_reg (submode, imag1);
temp1 = expand_binop (submode, binoptab, real0, real1, NULL_RTX,
unsignedp, methods);
temp2 = expand_binop (submode, binoptab, imag0, imag1, NULL_RTX,
unsignedp, methods);
if (temp1 == 0 || temp2 == 0)
break;
res = (expand_binop
(submode,
binoptab == smulv_optab ? subv_optab : sub_optab,
temp1, temp2, realr, unsignedp, methods));
if (res == 0)
break;
else if (res != realr)
emit_move_insn (realr, res);
temp1 = expand_binop (submode, binoptab, real0, imag1,
NULL_RTX, unsignedp, methods);
temp2 = expand_binop (submode, binoptab, real1, imag0,
NULL_RTX, unsignedp, methods);
if (temp1 == 0 || temp2 == 0)
break;
res = (expand_binop
(submode,
binoptab == smulv_optab ? addv_optab : add_optab,
temp1, temp2, imagr, unsignedp, methods));
if (res == 0)
break;
else if (res != imagr)
emit_move_insn (imagr, res);
ok = 1;
}
else
{
/* Don't fetch these from memory more than once. */
real0 = force_reg (submode, real0);
real1 = force_reg (submode, real1);
res = expand_binop (submode, binoptab, real0, real1,
realr, unsignedp, methods);
if (res == 0)
break;
else if (res != realr)
emit_move_insn (realr, res);
if (imag0 != 0)
res = expand_binop (submode, binoptab,
real1, imag0, imagr, unsignedp, methods);
else
res = expand_binop (submode, binoptab,
real0, imag1, imagr, unsignedp, methods);
if (res == 0)
break;
else if (res != imagr)
emit_move_insn (imagr, res);
ok = 1;
}
break;
case DIV:
/* (a+ib) / (c+id) = ((ac+bd)/(cc+dd)) + i((bc-ad)/(cc+dd)) */
if (imag1 == 0)
{
/* (a+ib) / (c+i0) = (a/c) + i(b/c) */
/* Don't fetch these from memory more than once. */
real1 = force_reg (submode, real1);
/* Simply divide the real and imaginary parts by `c' */
if (class == MODE_COMPLEX_FLOAT)
res = expand_binop (submode, binoptab, real0, real1,
realr, unsignedp, methods);
else
res = expand_divmod (0, TRUNC_DIV_EXPR, submode,
real0, real1, realr, unsignedp);
if (res == 0)
break;
else if (res != realr)
emit_move_insn (realr, res);
if (class == MODE_COMPLEX_FLOAT)
res = expand_binop (submode, binoptab, imag0, real1,
imagr, unsignedp, methods);
else
res = expand_divmod (0, TRUNC_DIV_EXPR, submode,
imag0, real1, imagr, unsignedp);
if (res == 0)
break;
else if (res != imagr)
emit_move_insn (imagr, res);
ok = 1;
}
else
{
switch (flag_complex_divide_method)
{
case 0:
ok = expand_cmplxdiv_straight (real0, real1, imag0, imag1,
realr, imagr, submode,
unsignedp, methods,
class, binoptab);
break;
case 1:
ok = expand_cmplxdiv_wide (real0, real1, imag0, imag1,
realr, imagr, submode,
unsignedp, methods,
class, binoptab);
break;
default:
abort ();
}
}
break;
default:
abort ();
}
seq = get_insns ();
end_sequence ();
if (ok)
{
if (binoptab->code != UNKNOWN)
equiv_value
= gen_rtx_fmt_ee (binoptab->code, mode,
copy_rtx (op0), copy_rtx (op1));
else
equiv_value = 0;
emit_no_conflict_block (seq, target, op0, op1, equiv_value);
return target;
}
}
/* It can't be open-coded in this mode.
Use a library call if one is available and caller says that's ok. */
if (binoptab->handlers[(int) mode].libfunc
&& (methods == OPTAB_LIB || methods == OPTAB_LIB_WIDEN))
{
rtx insns;
rtx op1x = op1;
enum machine_mode op1_mode = mode;
rtx value;
start_sequence ();
if (shift_op)
{
op1_mode = word_mode;
/* Specify unsigned here,
since negative shift counts are meaningless. */
op1x = convert_to_mode (word_mode, op1, 1);
}
if (GET_MODE (op0) != VOIDmode
&& GET_MODE (op0) != mode)
op0 = convert_to_mode (mode, op0, unsignedp);
/* Pass 1 for NO_QUEUE so we don't lose any increments
if the libcall is cse'd or moved. */
value = emit_library_call_value (binoptab->handlers[(int) mode].libfunc,
NULL_RTX, LCT_CONST, mode, 2,
op0, mode, op1x, op1_mode);
insns = get_insns ();
end_sequence ();
target = gen_reg_rtx (mode);
emit_libcall_block (insns, target, value,
gen_rtx_fmt_ee (binoptab->code, mode, op0, op1));
return target;
}
delete_insns_since (last);
/* It can't be done in this mode. Can we do it in a wider mode? */
if (! (methods == OPTAB_WIDEN || methods == OPTAB_LIB_WIDEN
|| methods == OPTAB_MUST_WIDEN))
{
/* Caller says, don't even try. */
delete_insns_since (entry_last);
return 0;
}
/* Compute the value of METHODS to pass to recursive calls.
Don't allow widening to be tried recursively. */
methods = (methods == OPTAB_LIB_WIDEN ? OPTAB_LIB : OPTAB_DIRECT);
/* Look for a wider mode of the same class for which it appears we can do
the operation. */
if (class == MODE_INT || class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT)
{
for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode;
wider_mode = GET_MODE_WIDER_MODE (wider_mode))
{
if ((binoptab->handlers[(int) wider_mode].insn_code
!= CODE_FOR_nothing)
|| (methods == OPTAB_LIB
&& binoptab->handlers[(int) wider_mode].libfunc))
{
rtx xop0 = op0, xop1 = op1;
int no_extend = 0;
/* For certain integer operations, we need not actually extend
the narrow operands, as long as we will truncate
the results to the same narrowness. */
if ((binoptab == ior_optab || binoptab == and_optab
|| binoptab == xor_optab
|| binoptab == add_optab || binoptab == sub_optab
|| binoptab == smul_optab || binoptab == ashl_optab)
&& class == MODE_INT)
no_extend = 1;
xop0 = widen_operand (xop0, wider_mode, mode,
unsignedp, no_extend);
/* The second operand of a shift must always be extended. */
xop1 = widen_operand (xop1, wider_mode, mode, unsignedp,
no_extend && binoptab != ashl_optab);
temp = expand_binop (wider_mode, binoptab, xop0, xop1, NULL_RTX,
unsignedp, methods);
if (temp)
{
if (class != MODE_INT)
{
if (target == 0)
target = gen_reg_rtx (mode);
convert_move (target, temp, 0);
return target;
}
else
return gen_lowpart (mode, temp);
}
else
delete_insns_since (last);
}
}
}
delete_insns_since (entry_last);
return 0;
}
/* Like expand_binop, but for open-coding vectors binops. */
static rtx
expand_vector_binop (mode, binoptab, op0, op1, target, unsignedp, methods)
enum machine_mode mode;
optab binoptab;
rtx op0, op1;
rtx target;
int unsignedp;
enum optab_methods methods;
{
enum machine_mode submode, tmode;
int size, elts, subsize, subbitsize, i;
rtx t, a, b, res, seq;
enum mode_class class;
class = GET_MODE_CLASS (mode);
size = GET_MODE_SIZE (mode);
submode = GET_MODE_INNER (mode);
/* Search for the widest vector mode with the same inner mode that is
still narrower than MODE and that allows to open-code this operator.
Note, if we find such a mode and the handler later decides it can't
do the expansion, we'll be called recursively with the narrower mode. */
for (tmode = GET_CLASS_NARROWEST_MODE (class);
GET_MODE_SIZE (tmode) < GET_MODE_SIZE (mode);
tmode = GET_MODE_WIDER_MODE (tmode))
{
if (GET_MODE_INNER (tmode) == GET_MODE_INNER (mode)
&& binoptab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
submode = tmode;
}
switch (binoptab->code)
{
case AND:
case IOR:
case XOR:
tmode = int_mode_for_mode (mode);
if (tmode != BLKmode)
submode = tmode;
case PLUS:
case MINUS:
case MULT:
case DIV:
subsize = GET_MODE_SIZE (submode);
subbitsize = GET_MODE_BITSIZE (submode);
elts = size / subsize;
/* If METHODS is OPTAB_DIRECT, we don't insist on the exact mode,
but that we operate on more than one element at a time. */
if (subsize == GET_MODE_UNIT_SIZE (mode) && methods == OPTAB_DIRECT)
return 0;
start_sequence ();
/* Errors can leave us with a const0_rtx as operand. */
if (GET_MODE (op0) != mode)
op0 = copy_to_mode_reg (mode, op0);
if (GET_MODE (op1) != mode)
op1 = copy_to_mode_reg (mode, op1);
if (!target)
target = gen_reg_rtx (mode);
for (i = 0; i < elts; ++i)
{
/* If this is part of a register, and not the first item in the
word, we can't store using a SUBREG - that would clobber
previous results.
And storing with a SUBREG is only possible for the least
significant part, hence we can't do it for big endian
(unless we want to permute the evaluation order. */
if (GET_CODE (target) == REG
&& (BYTES_BIG_ENDIAN
? subsize < UNITS_PER_WORD
: ((i * subsize) % UNITS_PER_WORD) != 0))
t = NULL_RTX;
else
t = simplify_gen_subreg (submode, target, mode, i * subsize);
if (CONSTANT_P (op0))
a = simplify_gen_subreg (submode, op0, mode, i * subsize);
else
a = extract_bit_field (op0, subbitsize, i * subbitsize, unsignedp,
NULL_RTX, submode, submode, size);
if (CONSTANT_P (op1))
b = simplify_gen_subreg (submode, op1, mode, i * subsize);
else
b = extract_bit_field (op1, subbitsize, i * subbitsize, unsignedp,
NULL_RTX, submode, submode, size);
if (binoptab->code == DIV)
{
if (class == MODE_VECTOR_FLOAT)
res = expand_binop (submode, binoptab, a, b, t,
unsignedp, methods);
else
res = expand_divmod (0, TRUNC_DIV_EXPR, submode,
a, b, t, unsignedp);
}
else
res = expand_binop (submode, binoptab, a, b, t,
unsignedp, methods);
if (res == 0)
break;
if (t)
emit_move_insn (t, res);
else
store_bit_field (target, subbitsize, i * subbitsize, submode, res,
size);
}
break;
default:
abort ();
}
seq = get_insns ();
end_sequence ();
emit_insn (seq);
return target;
}
/* Like expand_unop but for open-coding vector unops. */
static rtx
expand_vector_unop (mode, unoptab, op0, target, unsignedp)
enum machine_mode mode;
optab unoptab;
rtx op0;
rtx target;
int unsignedp;
{
enum machine_mode submode, tmode;
int size, elts, subsize, subbitsize, i;
rtx t, a, res, seq;
size = GET_MODE_SIZE (mode);
submode = GET_MODE_INNER (mode);
/* Search for the widest vector mode with the same inner mode that is
still narrower than MODE and that allows to open-code this operator.
Note, if we find such a mode and the handler later decides it can't
do the expansion, we'll be called recursively with the narrower mode. */
for (tmode = GET_CLASS_NARROWEST_MODE (GET_MODE_CLASS (mode));
GET_MODE_SIZE (tmode) < GET_MODE_SIZE (mode);
tmode = GET_MODE_WIDER_MODE (tmode))
{
if (GET_MODE_INNER (tmode) == GET_MODE_INNER (mode)
&& unoptab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
submode = tmode;
}
/* If there is no negate operation, try doing a subtract from zero. */
if (unoptab == neg_optab && GET_MODE_CLASS (submode) == MODE_INT
/* Avoid infinite recursion when an
error has left us with the wrong mode. */
&& GET_MODE (op0) == mode)
{
rtx temp;
temp = expand_binop (mode, sub_optab, CONST0_RTX (mode), op0,
target, unsignedp, OPTAB_DIRECT);
if (temp)
return temp;
}
if (unoptab == one_cmpl_optab)
{
tmode = int_mode_for_mode (mode);
if (tmode != BLKmode)
submode = tmode;
}
subsize = GET_MODE_SIZE (submode);
subbitsize = GET_MODE_BITSIZE (submode);
elts = size / subsize;
/* Errors can leave us with a const0_rtx as operand. */
if (GET_MODE (op0) != mode)
op0 = copy_to_mode_reg (mode, op0);
if (!target)
target = gen_reg_rtx (mode);
start_sequence ();
for (i = 0; i < elts; ++i)
{
/* If this is part of a register, and not the first item in the
word, we can't store using a SUBREG - that would clobber
previous results.
And storing with a SUBREG is only possible for the least
significant part, hence we can't do it for big endian
(unless we want to permute the evaluation order. */
if (GET_CODE (target) == REG
&& (BYTES_BIG_ENDIAN
? subsize < UNITS_PER_WORD
: ((i * subsize) % UNITS_PER_WORD) != 0))
t = NULL_RTX;
else
t = simplify_gen_subreg (submode, target, mode, i * subsize);
if (CONSTANT_P (op0))
a = simplify_gen_subreg (submode, op0, mode, i * subsize);
else
a = extract_bit_field (op0, subbitsize, i * subbitsize, unsignedp,
t, submode, submode, size);
res = expand_unop (submode, unoptab, a, t, unsignedp);
if (t)
emit_move_insn (t, res);
else
store_bit_field (target, subbitsize, i * subbitsize, submode, res,
size);
}
seq = get_insns ();
end_sequence ();
emit_insn (seq);
return target;
}
/* Expand a binary operator which has both signed and unsigned forms.
UOPTAB is the optab for unsigned operations, and SOPTAB is for
signed operations.
If we widen unsigned operands, we may use a signed wider operation instead
of an unsigned wider operation, since the result would be the same. */
rtx
sign_expand_binop (mode, uoptab, soptab, op0, op1, target, unsignedp, methods)
enum machine_mode mode;
optab uoptab, soptab;
rtx op0, op1, target;
int unsignedp;
enum optab_methods methods;
{
rtx temp;
optab direct_optab = unsignedp ? uoptab : soptab;
struct optab wide_soptab;
/* Do it without widening, if possible. */
temp = expand_binop (mode, direct_optab, op0, op1, target,
unsignedp, OPTAB_DIRECT);
if (temp || methods == OPTAB_DIRECT)
return temp;
/* Try widening to a signed int. Make a fake signed optab that
hides any signed insn for direct use. */
wide_soptab = *soptab;
wide_soptab.handlers[(int) mode].insn_code = CODE_FOR_nothing;
wide_soptab.handlers[(int) mode].libfunc = 0;
temp = expand_binop (mode, &wide_soptab, op0, op1, target,
unsignedp, OPTAB_WIDEN);
/* For unsigned operands, try widening to an unsigned int. */
if (temp == 0 && unsignedp)
temp = expand_binop (mode, uoptab, op0, op1, target,
unsignedp, OPTAB_WIDEN);
if (temp || methods == OPTAB_WIDEN)
return temp;
/* Use the right width lib call if that exists. */
temp = expand_binop (mode, direct_optab, op0, op1, target, unsignedp, OPTAB_LIB);
if (temp || methods == OPTAB_LIB)
return temp;
/* Must widen and use a lib call, use either signed or unsigned. */
temp = expand_binop (mode, &wide_soptab, op0, op1, target,
unsignedp, methods);
if (temp != 0)
return temp;
if (unsignedp)
return expand_binop (mode, uoptab, op0, op1, target,
unsignedp, methods);
return 0;
}
/* Generate code to perform an operation specified by BINOPTAB
on operands OP0 and OP1, with two results to TARG1 and TARG2.
We assume that the order of the operands for the instruction
is TARG0, OP0, OP1, TARG1, which would fit a pattern like
[(set TARG0 (operate OP0 OP1)) (set TARG1 (operate ...))].
Either TARG0 or TARG1 may be zero, but what that means is that
the result is not actually wanted. We will generate it into
a dummy pseudo-reg and discard it. They may not both be zero.
Returns 1 if this operation can be performed; 0 if not. */
int
expand_twoval_binop (binoptab, op0, op1, targ0, targ1, unsignedp)
optab binoptab;
rtx op0, op1;
rtx targ0, targ1;
int unsignedp;
{
enum machine_mode mode = GET_MODE (targ0 ? targ0 : targ1);
enum mode_class class;
enum machine_mode wider_mode;
rtx entry_last = get_last_insn ();
rtx last;
class = GET_MODE_CLASS (mode);
op0 = protect_from_queue (op0, 0);
op1 = protect_from_queue (op1, 0);
if (flag_force_mem)
{
op0 = force_not_mem (op0);
op1 = force_not_mem (op1);
}
/* If we are inside an appropriately-short loop and one operand is an
expensive constant, force it into a register. */
if (CONSTANT_P (op0) && preserve_subexpressions_p ()
&& rtx_cost (op0, binoptab->code) > COSTS_N_INSNS (1))
op0 = force_reg (mode, op0);
if (CONSTANT_P (op1) && preserve_subexpressions_p ()
&& rtx_cost (op1, binoptab->code) > COSTS_N_INSNS (1))
op1 = force_reg (mode, op1);
if (targ0)
targ0 = protect_from_queue (targ0, 1);
else
targ0 = gen_reg_rtx (mode);
if (targ1)
targ1 = protect_from_queue (targ1, 1);
else
targ1 = gen_reg_rtx (mode);
/* Record where to go back to if we fail. */
last = get_last_insn ();
if (binoptab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
{
int icode = (int) binoptab->handlers[(int) mode].insn_code;
enum machine_mode mode0 = insn_data[icode].operand[1].mode;
enum machine_mode mode1 = insn_data[icode].operand[2].mode;
rtx pat;
rtx xop0 = op0, xop1 = op1;
/* In case the insn wants input operands in modes different from
those of the actual operands, convert the operands. It would
seem that we don't need to convert CONST_INTs, but we do, so
that they're properly zero-extended, sign-extended or truncated
for their mode. */
if (GET_MODE (op0) != mode0 && mode0 != VOIDmode)
xop0 = convert_modes (mode0,
GET_MODE (op0) != VOIDmode
? GET_MODE (op0)
: mode,
xop0, unsignedp);
if (GET_MODE (op1) != mode1 && mode1 != VOIDmode)
xop1 = convert_modes (mode1,
GET_MODE (op1) != VOIDmode
? GET_MODE (op1)
: mode,
xop1, unsignedp);
/* Now, if insn doesn't accept these operands, put them into pseudos. */
if (! (*insn_data[icode].operand[1].predicate) (xop0, mode0))
xop0 = copy_to_mode_reg (mode0, xop0);
if (! (*insn_data[icode].operand[2].predicate) (xop1, mode1))
xop1 = copy_to_mode_reg (mode1, xop1);
/* We could handle this, but we should always be called with a pseudo
for our targets and all insns should take them as outputs. */
if (! (*insn_data[icode].operand[0].predicate) (targ0, mode)
|| ! (*insn_data[icode].operand[3].predicate) (targ1, mode))
abort ();
pat = GEN_FCN (icode) (targ0, xop0, xop1, targ1);
if (pat)
{
emit_insn (pat);
return 1;
}
else
delete_insns_since (last);
}
/* It can't be done in this mode. Can we do it in a wider mode? */
if (class == MODE_INT || class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT)
{
for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode;
wider_mode = GET_MODE_WIDER_MODE (wider_mode))
{
if (binoptab->handlers[(int) wider_mode].insn_code
!= CODE_FOR_nothing)
{
rtx t0 = gen_reg_rtx (wider_mode);
rtx t1 = gen_reg_rtx (wider_mode);
rtx cop0 = convert_modes (wider_mode, mode, op0, unsignedp);
rtx cop1 = convert_modes (wider_mode, mode, op1, unsignedp);
if (expand_twoval_binop (binoptab, cop0, cop1,
t0, t1, unsignedp))
{
convert_move (targ0, t0, unsignedp);
convert_move (targ1, t1, unsignedp);
return 1;
}
else
delete_insns_since (last);
}
}
}
delete_insns_since (entry_last);
return 0;
}
/* Wrapper around expand_unop which takes an rtx code to specify
the operation to perform, not an optab pointer. All other
arguments are the same. */
rtx
expand_simple_unop (mode, code, op0, target, unsignedp)
enum machine_mode mode;
enum rtx_code code;
rtx op0;
rtx target;
int unsignedp;
{
optab unop = code_to_optab[(int) code];
if (unop == 0)
abort ();
return expand_unop (mode, unop, op0, target, unsignedp);
}
/* Generate code to perform an operation specified by UNOPTAB
on operand OP0, with result having machine-mode MODE.
UNSIGNEDP is for the case where we have to widen the operands
to perform the operation. It says to use zero-extension.
If TARGET is nonzero, the value
is generated there, if it is convenient to do so.
In all cases an rtx is returned for the locus of the value;
this may or may not be TARGET. */
rtx
expand_unop (mode, unoptab, op0, target, unsignedp)
enum machine_mode mode;
optab unoptab;
rtx op0;
rtx target;
int unsignedp;
{
enum mode_class class;
enum machine_mode wider_mode;
rtx temp;
rtx last = get_last_insn ();
rtx pat;
class = GET_MODE_CLASS (mode);
op0 = protect_from_queue (op0, 0);
if (flag_force_mem)
{
op0 = force_not_mem (op0);
}
if (target)
target = protect_from_queue (target, 1);
if (unoptab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
{
int icode = (int) unoptab->handlers[(int) mode].insn_code;
enum machine_mode mode0 = insn_data[icode].operand[1].mode;
rtx xop0 = op0;
if (target)
temp = target;
else
temp = gen_reg_rtx (mode);
if (GET_MODE (xop0) != VOIDmode
&& GET_MODE (xop0) != mode0)
xop0 = convert_to_mode (mode0, xop0, unsignedp);
/* Now, if insn doesn't accept our operand, put it into a pseudo. */
if (! (*insn_data[icode].operand[1].predicate) (xop0, mode0))
xop0 = copy_to_mode_reg (mode0, xop0);
if (! (*insn_data[icode].operand[0].predicate) (temp, mode))
temp = gen_reg_rtx (mode);
pat = GEN_FCN (icode) (temp, xop0);
if (pat)
{
if (INSN_P (pat) && NEXT_INSN (pat) != NULL_RTX
&& ! add_equal_note (pat, temp, unoptab->code, xop0, NULL_RTX))
{
delete_insns_since (last);
return expand_unop (mode, unoptab, op0, NULL_RTX, unsignedp);
}
emit_insn (pat);
return temp;
}
else
delete_insns_since (last);
}
/* It can't be done in this mode. Can we open-code it in a wider mode? */
if (class == MODE_INT || class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT)
for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode;
wider_mode = GET_MODE_WIDER_MODE (wider_mode))
{
if (unoptab->handlers[(int) wider_mode].insn_code != CODE_FOR_nothing)
{
rtx xop0 = op0;
/* For certain operations, we need not actually extend
the narrow operand, as long as we will truncate the
results to the same narrowness. */
xop0 = widen_operand (xop0, wider_mode, mode, unsignedp,
(unoptab == neg_optab
|| unoptab == one_cmpl_optab)
&& class == MODE_INT);
temp = expand_unop (wider_mode, unoptab, xop0, NULL_RTX,
unsignedp);
if (temp)
{
if (class != MODE_INT)
{
if (target == 0)
target = gen_reg_rtx (mode);
convert_move (target, temp, 0);
return target;
}
else
return gen_lowpart (mode, temp);
}
else
delete_insns_since (last);
}
}
/* These can be done a word at a time. */
if (unoptab == one_cmpl_optab
&& class == MODE_INT
&& GET_MODE_SIZE (mode) > UNITS_PER_WORD
&& unoptab->handlers[(int) word_mode].insn_code != CODE_FOR_nothing)
{
int i;
rtx insns;
if (target == 0 || target == op0)
target = gen_reg_rtx (mode);
start_sequence ();
/* Do the actual arithmetic. */
for (i = 0; i < GET_MODE_BITSIZE (mode) / BITS_PER_WORD; i++)
{
rtx target_piece = operand_subword (target, i, 1, mode);
rtx x = expand_unop (word_mode, unoptab,
operand_subword_force (op0, i, mode),
target_piece, unsignedp);
if (target_piece != x)
emit_move_insn (target_piece, x);
}
insns = get_insns ();
end_sequence ();
emit_no_conflict_block (insns, target, op0, NULL_RTX,
gen_rtx_fmt_e (unoptab->code, mode,
copy_rtx (op0)));
return target;
}
/* Open-code the complex negation operation. */
else if (unoptab->code == NEG
&& (class == MODE_COMPLEX_FLOAT || class == MODE_COMPLEX_INT))
{
rtx target_piece;
rtx x;
rtx seq;
/* Find the correct mode for the real and imaginary parts */
enum machine_mode submode = GET_MODE_INNER (mode);
if (submode == BLKmode)
abort ();
if (target == 0)
target = gen_reg_rtx (mode);
start_sequence ();
target_piece = gen_imagpart (submode, target);
x = expand_unop (submode, unoptab,
gen_imagpart (submode, op0),
target_piece, unsignedp);
if (target_piece != x)
emit_move_insn (target_piece, x);
target_piece = gen_realpart (submode, target);
x = expand_unop (submode, unoptab,
gen_realpart (submode, op0),
target_piece, unsignedp);
if (target_piece != x)
emit_move_insn (target_piece, x);
seq = get_insns ();
end_sequence ();
emit_no_conflict_block (seq, target, op0, 0,
gen_rtx_fmt_e (unoptab->code, mode,
copy_rtx (op0)));
return target;
}
/* Now try a library call in this mode. */
if (unoptab->handlers[(int) mode].libfunc)
{
rtx insns;
rtx value;
start_sequence ();
/* Pass 1 for NO_QUEUE so we don't lose any increments
if the libcall is cse'd or moved. */
value = emit_library_call_value (unoptab->handlers[(int) mode].libfunc,
NULL_RTX, LCT_CONST, mode, 1, op0, mode);
insns = get_insns ();
end_sequence ();
target = gen_reg_rtx (mode);
emit_libcall_block (insns, target, value,
gen_rtx_fmt_e (unoptab->code, mode, op0));
return target;
}
if (class == MODE_VECTOR_FLOAT || class == MODE_VECTOR_INT)
return expand_vector_unop (mode, unoptab, op0, target, unsignedp);
/* It can't be done in this mode. Can we do it in a wider mode? */
if (class == MODE_INT || class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT)
{
for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode;
wider_mode = GET_MODE_WIDER_MODE (wider_mode))
{
if ((unoptab->handlers[(int) wider_mode].insn_code
!= CODE_FOR_nothing)
|| unoptab->handlers[(int) wider_mode].libfunc)
{
rtx xop0 = op0;
/* For certain operations, we need not actually extend
the narrow operand, as long as we will truncate the
results to the same narrowness. */
xop0 = widen_operand (xop0, wider_mode, mode, unsignedp,
(unoptab == neg_optab
|| unoptab == one_cmpl_optab)
&& class == MODE_INT);
temp = expand_unop (wider_mode, unoptab, xop0, NULL_RTX,
unsignedp);
if (temp)
{
if (class != MODE_INT)
{
if (target == 0)
target = gen_reg_rtx (mode);
convert_move (target, temp, 0);
return target;
}
else
return gen_lowpart (mode, temp);
}
else
delete_insns_since (last);
}
}
}
/* If there is no negate operation, try doing a subtract from zero.
The US Software GOFAST library needs this. */
if (unoptab->code == NEG)
{
rtx temp;
temp = expand_binop (mode,
unoptab == negv_optab ? subv_optab : sub_optab,
CONST0_RTX (mode), op0,
target, unsignedp, OPTAB_LIB_WIDEN);
if (temp)
return temp;
}
return 0;
}
/* Emit code to compute the absolute value of OP0, with result to
TARGET if convenient. (TARGET may be 0.) The return value says
where the result actually is to be found.
MODE is the mode of the operand; the mode of the result is
different but can be deduced from MODE.
*/
rtx
expand_abs (mode, op0, target, result_unsignedp, safe)
enum machine_mode mode;
rtx op0;
rtx target;
int result_unsignedp;
int safe;
{
rtx temp, op1;
if (! flag_trapv)
result_unsignedp = 1;
/* First try to do it with a special abs instruction. */
temp = expand_unop (mode, result_unsignedp ? abs_optab : absv_optab,
op0, target, 0);
if (temp != 0)
return temp;
/* If we have a MAX insn, we can do this as MAX (x, -x). */
if (smax_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
{
rtx last = get_last_insn ();
temp = expand_unop (mode, neg_optab, op0, NULL_RTX, 0);
if (temp != 0)
temp = expand_binop (mode, smax_optab, op0, temp, target, 0,
OPTAB_WIDEN);
if (temp != 0)
return temp;
delete_insns_since (last);
}
/* If this machine has expensive jumps, we can do integer absolute
value of X as (((signed) x >> (W-1)) ^ x) - ((signed) x >> (W-1)),
where W is the width of MODE. */
if (GET_MODE_CLASS (mode) == MODE_INT && BRANCH_COST >= 2)
{
rtx extended = expand_shift (RSHIFT_EXPR, mode, op0,
size_int (GET_MODE_BITSIZE (mode) - 1),
NULL_RTX, 0);
temp = expand_binop (mode, xor_optab, extended, op0, target, 0,
OPTAB_LIB_WIDEN);
if (temp != 0)
temp = expand_binop (mode, result_unsignedp ? sub_optab : subv_optab,
temp, extended, target, 0, OPTAB_LIB_WIDEN);
if (temp != 0)
return temp;
}
/* If that does not win, use conditional jump and negate. */
/* It is safe to use the target if it is the same
as the source if this is also a pseudo register */
if (op0 == target && GET_CODE (op0) == REG
&& REGNO (op0) >= FIRST_PSEUDO_REGISTER)
safe = 1;
op1 = gen_label_rtx ();
if (target == 0 || ! safe
|| GET_MODE (target) != mode
|| (GET_CODE (target) == MEM && MEM_VOLATILE_P (target))
|| (GET_CODE (target) == REG
&& REGNO (target) < FIRST_PSEUDO_REGISTER))
target = gen_reg_rtx (mode);
emit_move_insn (target, op0);
NO_DEFER_POP;
/* If this mode is an integer too wide to compare properly,
compare word by word. Rely on CSE to optimize constant cases. */
if (GET_MODE_CLASS (mode) == MODE_INT
&& ! can_compare_p (GE, mode, ccp_jump))
do_jump_by_parts_greater_rtx (mode, 0, target, const0_rtx,
NULL_RTX, op1);
else
do_compare_rtx_and_jump (target, CONST0_RTX (mode), GE, 0, mode,
NULL_RTX, NULL_RTX, op1);
op0 = expand_unop (mode, result_unsignedp ? neg_optab : negv_optab,
target, target, 0);
if (op0 != target)
emit_move_insn (target, op0);
emit_label (op1);
OK_DEFER_POP;
return target;
}
/* Emit code to compute the absolute value of OP0, with result to
TARGET if convenient. (TARGET may be 0.) The return value says
where the result actually is to be found.
MODE is the mode of the operand; the mode of the result is
different but can be deduced from MODE.
UNSIGNEDP is relevant for complex integer modes. */
rtx
expand_complex_abs (mode, op0, target, unsignedp)
enum machine_mode mode;
rtx op0;
rtx target;
int unsignedp;
{
enum mode_class class = GET_MODE_CLASS (mode);
enum machine_mode wider_mode;
rtx temp;
rtx entry_last = get_last_insn ();
rtx last;
rtx pat;
optab this_abs_optab;
/* Find the correct mode for the real and imaginary parts. */
enum machine_mode submode = GET_MODE_INNER (mode);
if (submode == BLKmode)
abort ();
op0 = protect_from_queue (op0, 0);
if (flag_force_mem)
{
op0 = force_not_mem (op0);
}
last = get_last_insn ();
if (target)
target = protect_from_queue (target, 1);
this_abs_optab = ! unsignedp && flag_trapv
&& (GET_MODE_CLASS(mode) == MODE_INT)
? absv_optab : abs_optab;
if (this_abs_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
{
int icode = (int) this_abs_optab->handlers[(int) mode].insn_code;
enum machine_mode mode0 = insn_data[icode].operand[1].mode;
rtx xop0 = op0;
if (target)
temp = target;
else
temp = gen_reg_rtx (submode);
if (GET_MODE (xop0) != VOIDmode
&& GET_MODE (xop0) != mode0)
xop0 = convert_to_mode (mode0, xop0, unsignedp);
/* Now, if insn doesn't accept our operand, put it into a pseudo. */
if (! (*insn_data[icode].operand[1].predicate) (xop0, mode0))
xop0 = copy_to_mode_reg (mode0, xop0);
if (! (*insn_data[icode].operand[0].predicate) (temp, submode))
temp = gen_reg_rtx (submode);
pat = GEN_FCN (icode) (temp, xop0);
if (pat)
{
if (INSN_P (pat) && NEXT_INSN (pat) != NULL_RTX
&& ! add_equal_note (pat, temp, this_abs_optab->code, xop0,
NULL_RTX))
{
delete_insns_since (last);
return expand_unop (mode, this_abs_optab, op0, NULL_RTX,
unsignedp);
}
emit_insn (pat);
return temp;
}
else
delete_insns_since (last);
}
/* It can't be done in this mode. Can we open-code it in a wider mode? */
for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode;
wider_mode = GET_MODE_WIDER_MODE (wider_mode))
{
if (this_abs_optab->handlers[(int) wider_mode].insn_code
!= CODE_FOR_nothing)
{
rtx xop0 = op0;
xop0 = convert_modes (wider_mode, mode, xop0, unsignedp);
temp = expand_complex_abs (wider_mode, xop0, NULL_RTX, unsignedp);
if (temp)
{
if (class != MODE_COMPLEX_INT)
{
if (target == 0)
target = gen_reg_rtx (submode);
convert_move (target, temp, 0);
return target;
}
else
return gen_lowpart (submode, temp);
}
else
delete_insns_since (last);
}
}
/* Open-code the complex absolute-value operation
if we can open-code sqrt. Otherwise it's not worth while. */
if (sqrt_optab->handlers[(int) submode].insn_code != CODE_FOR_nothing
&& ! flag_trapv)
{
rtx real, imag, total;
real = gen_realpart (submode, op0);
imag = gen_imagpart (submode, op0);
/* Square both parts. */
real = expand_mult (submode, real, real, NULL_RTX, 0);
imag = expand_mult (submode, imag, imag, NULL_RTX, 0);
/* Sum the parts. */
total = expand_binop (submode, add_optab, real, imag, NULL_RTX,
0, OPTAB_LIB_WIDEN);
/* Get sqrt in TARGET. Set TARGET to where the result is. */
target = expand_unop (submode, sqrt_optab, total, target, 0);
if (target == 0)
delete_insns_since (last);
else
return target;
}
/* Now try a library call in this mode. */
if (this_abs_optab->handlers[(int) mode].libfunc)
{
rtx insns;
rtx value;
start_sequence ();
/* Pass 1 for NO_QUEUE so we don't lose any increments
if the libcall is cse'd or moved. */
value = emit_library_call_value (abs_optab->handlers[(int) mode].libfunc,
NULL_RTX, LCT_CONST, submode, 1, op0, mode);
insns = get_insns ();
end_sequence ();
target = gen_reg_rtx (submode);
emit_libcall_block (insns, target, value,
gen_rtx_fmt_e (this_abs_optab->code, mode, op0));
return target;
}
/* It can't be done in this mode. Can we do it in a wider mode? */
for (wider_mode = GET_MODE_WIDER_MODE (mode); wider_mode != VOIDmode;
wider_mode = GET_MODE_WIDER_MODE (wider_mode))
{
if ((this_abs_optab->handlers[(int) wider_mode].insn_code
!= CODE_FOR_nothing)
|| this_abs_optab->handlers[(int) wider_mode].libfunc)
{
rtx xop0 = op0;
xop0 = convert_modes (wider_mode, mode, xop0, unsignedp);
temp = expand_complex_abs (wider_mode, xop0, NULL_RTX, unsignedp);
if (temp)
{
if (class != MODE_COMPLEX_INT)
{
if (target == 0)
target = gen_reg_rtx (submode);
convert_move (target, temp, 0);
return target;
}
else
return gen_lowpart (submode, temp);
}
else
delete_insns_since (last);
}
}
delete_insns_since (entry_last);
return 0;
}
/* Generate an instruction whose insn-code is INSN_CODE,
with two operands: an output TARGET and an input OP0.
TARGET *must* be nonzero, and the output is always stored there.
CODE is an rtx code such that (CODE OP0) is an rtx that describes
the value that is stored into TARGET. */
void
emit_unop_insn (icode, target, op0, code)
int icode;
rtx target;
rtx op0;
enum rtx_code code;
{
rtx temp;
enum machine_mode mode0 = insn_data[icode].operand[1].mode;
rtx pat;
temp = target = protect_from_queue (target, 1);
op0 = protect_from_queue (op0, 0);
/* Sign and zero extension from memory is often done specially on
RISC machines, so forcing into a register here can pessimize
code. */
if (flag_force_mem && code != SIGN_EXTEND && code != ZERO_EXTEND)
op0 = force_not_mem (op0);
/* Now, if insn does not accept our operands, put them into pseudos. */
if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
op0 = copy_to_mode_reg (mode0, op0);
if (! (*insn_data[icode].operand[0].predicate) (temp, GET_MODE (temp))
|| (flag_force_mem && GET_CODE (temp) == MEM))
temp = gen_reg_rtx (GET_MODE (temp));
pat = GEN_FCN (icode) (temp, op0);
if (INSN_P (pat) && NEXT_INSN (pat) != NULL_RTX && code != UNKNOWN)
add_equal_note (pat, temp, code, op0, NULL_RTX);
emit_insn (pat);
if (temp != target)
emit_move_insn (target, temp);
}
/* Emit code to perform a series of operations on a multi-word quantity, one
word at a time.
Such a block is preceded by a CLOBBER of the output, consists of multiple
insns, each setting one word of the output, and followed by a SET copying
the output to itself.
Each of the insns setting words of the output receives a REG_NO_CONFLICT
note indicating that it doesn't conflict with the (also multi-word)
inputs. The entire block is surrounded by REG_LIBCALL and REG_RETVAL
notes.
INSNS is a block of code generated to perform the operation, not including
the CLOBBER and final copy. All insns that compute intermediate values
are first emitted, followed by the block as described above.
TARGET, OP0, and OP1 are the output and inputs of the operations,
respectively. OP1 may be zero for a unary operation.
EQUIV, if nonzero, is an expression to be placed into a REG_EQUAL note
on the last insn.
If TARGET is not a register, INSNS is simply emitted with no special
processing. Likewise if anything in INSNS is not an INSN or if
there is a libcall block inside INSNS.
The final insn emitted is returned. */
rtx
emit_no_conflict_block (insns, target, op0, op1, equiv)
rtx insns;
rtx target;
rtx op0, op1;
rtx equiv;
{
rtx prev, next, first, last, insn;
if (GET_CODE (target) != REG || reload_in_progress)
return emit_insn (insns);
else
for (insn = insns; insn; insn = NEXT_INSN (insn))
if (GET_CODE (insn) != INSN
|| find_reg_note (insn, REG_LIBCALL, NULL_RTX))
return emit_insn (insns);
/* First emit all insns that do not store into words of the output and remove
these from the list. */
for (insn = insns; insn; insn = next)
{
rtx set = 0, note;
int i;
next = NEXT_INSN (insn);
/* Some ports (cris) create an libcall regions at their own. We must
avoid any potential nesting of LIBCALLs. */
if ((note = find_reg_note (insn, REG_LIBCALL, NULL)) != NULL)
remove_note (insn, note);
if ((note = find_reg_note (insn, REG_RETVAL, NULL)) != NULL)
remove_note (insn, note);
if (GET_CODE (PATTERN (insn)) == SET || GET_CODE (PATTERN (insn)) == USE
|| GET_CODE (PATTERN (insn)) == CLOBBER)
set = PATTERN (insn);
else if (GET_CODE (PATTERN (insn)) == PARALLEL)
{
for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
if (GET_CODE (XVECEXP (PATTERN (insn), 0, i)) == SET)
{
set = XVECEXP (PATTERN (insn), 0, i);
break;
}
}
if (set == 0)
abort ();
if (! reg_overlap_mentioned_p (target, SET_DEST (set)))
{
if (PREV_INSN (insn))
NEXT_INSN (PREV_INSN (insn)) = next;
else
insns = next;
if (next)
PREV_INSN (next) = PREV_INSN (insn);
add_insn (insn);
}
}
prev = get_last_insn ();
/* Now write the CLOBBER of the output, followed by the setting of each
of the words, followed by the final copy. */
if (target != op0 && target != op1)
emit_insn (gen_rtx_CLOBBER (VOIDmode, target));
for (insn = insns; insn; insn = next)
{
next = NEXT_INSN (insn);
add_insn (insn);
if (op1 && GET_CODE (op1) == REG)
REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_NO_CONFLICT, op1,
REG_NOTES (insn));
if (op0 && GET_CODE (op0) == REG)
REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_NO_CONFLICT, op0,
REG_NOTES (insn));
}
if (mov_optab->handlers[(int) GET_MODE (target)].insn_code
!= CODE_FOR_nothing)
{
last = emit_move_insn (target, target);
if (equiv)
set_unique_reg_note (last, REG_EQUAL, equiv);
}
else
{
last = get_last_insn ();
/* Remove any existing REG_EQUAL note from "last", or else it will
be mistaken for a note referring to the full contents of the
alleged libcall value when found together with the REG_RETVAL
note added below. An existing note can come from an insn
expansion at "last". */
remove_note (last, find_reg_note (last, REG_EQUAL, NULL_RTX));