| ; Machine description for AArch64 architecture. |
| ; Copyright (C) 2009-2018 Free Software Foundation, Inc. |
| ; Contributed by ARM Ltd. |
| ; |
| ; This file is part of GCC. |
| ; |
| ; GCC is free software; you can redistribute it and/or modify it |
| ; under the terms of the GNU General Public License as published by |
| ; the Free Software Foundation; either version 3, or (at your option) |
| ; any later version. |
| ; |
| ; GCC is distributed in the hope that it will be useful, but |
| ; WITHOUT ANY WARRANTY; without even the implied warranty of |
| ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| ; General Public License for more details. |
| ; |
| ; You should have received a copy of the GNU General Public License |
| ; along with GCC; see the file COPYING3. If not see |
| ; <http://www.gnu.org/licenses/>. |
| |
| HeaderInclude |
| config/aarch64/aarch64-opts.h |
| |
| TargetVariable |
| enum aarch64_processor explicit_tune_core = aarch64_none |
| |
| TargetVariable |
| enum aarch64_arch explicit_arch = aarch64_no_arch |
| |
| TargetSave |
| const char *x_aarch64_override_tune_string |
| |
| TargetVariable |
| unsigned long aarch64_isa_flags = 0 |
| |
| ; The TLS dialect names to use with -mtls-dialect. |
| |
| Enum |
| Name(tls_type) Type(enum aarch64_tls_type) |
| The possible TLS dialects: |
| |
| EnumValue |
| Enum(tls_type) String(trad) Value(TLS_TRADITIONAL) |
| |
| EnumValue |
| Enum(tls_type) String(desc) Value(TLS_DESCRIPTORS) |
| |
| ; The code model option names for -mcmodel. |
| |
| Enum |
| Name(cmodel) Type(enum aarch64_code_model) |
| The code model option names for -mcmodel: |
| |
| EnumValue |
| Enum(cmodel) String(tiny) Value(AARCH64_CMODEL_TINY) |
| |
| EnumValue |
| Enum(cmodel) String(small) Value(AARCH64_CMODEL_SMALL) |
| |
| EnumValue |
| Enum(cmodel) String(large) Value(AARCH64_CMODEL_LARGE) |
| |
| mbig-endian |
| Target Report RejectNegative Mask(BIG_END) |
| Assume target CPU is configured as big endian. |
| |
| mgeneral-regs-only |
| Target Report RejectNegative Mask(GENERAL_REGS_ONLY) Save |
| Generate code which uses only the general registers. |
| |
| mfix-cortex-a53-835769 |
| Target Report Var(aarch64_fix_a53_err835769) Init(2) Save |
| Workaround for ARM Cortex-A53 Erratum number 835769. |
| |
| mfix-cortex-a53-843419 |
| Target Report Var(aarch64_fix_a53_err843419) Init(2) Save |
| Workaround for ARM Cortex-A53 Erratum number 843419. |
| |
| mlittle-endian |
| Target Report RejectNegative InverseMask(BIG_END) |
| Assume target CPU is configured as little endian. |
| |
| mcmodel= |
| Target RejectNegative Joined Enum(cmodel) Var(aarch64_cmodel_var) Init(AARCH64_CMODEL_SMALL) Save |
| Specify the code model. |
| |
| mstrict-align |
| Target Report RejectNegative Mask(STRICT_ALIGN) Save |
| Don't assume that unaligned accesses are handled by the system. |
| |
| momit-leaf-frame-pointer |
| Target Report Var(flag_omit_leaf_frame_pointer) Init(2) Save |
| Omit the frame pointer in leaf functions. |
| |
| mtls-dialect= |
| Target RejectNegative Joined Enum(tls_type) Var(aarch64_tls_dialect) Init(TLS_DESCRIPTORS) Save |
| Specify TLS dialect. |
| |
| mtls-size= |
| Target RejectNegative Joined Var(aarch64_tls_size) Enum(aarch64_tls_size) |
| Specifies bit size of immediate TLS offsets. Valid values are 12, 24, 32, 48. |
| |
| Enum |
| Name(aarch64_tls_size) Type(int) |
| |
| EnumValue |
| Enum(aarch64_tls_size) String(12) Value(12) |
| |
| EnumValue |
| Enum(aarch64_tls_size) String(24) Value(24) |
| |
| EnumValue |
| Enum(aarch64_tls_size) String(32) Value(32) |
| |
| EnumValue |
| Enum(aarch64_tls_size) String(48) Value(48) |
| |
| march= |
| Target RejectNegative ToLower Joined Var(aarch64_arch_string) |
| -march=ARCH Use features of architecture ARCH. |
| |
| mcpu= |
| Target RejectNegative ToLower Joined Var(aarch64_cpu_string) |
| -mcpu=CPU Use features of and optimize for CPU. |
| |
| mtune= |
| Target RejectNegative ToLower Joined Var(aarch64_tune_string) |
| -mtune=CPU Optimize for CPU. |
| |
| mabi= |
| Target RejectNegative Joined Enum(aarch64_abi) Var(aarch64_abi) Init(AARCH64_ABI_DEFAULT) |
| -mabi=ABI Generate code that conforms to the specified ABI. |
| |
| moverride= |
| Target RejectNegative ToLower Joined Var(aarch64_override_tune_string) |
| -moverride=STRING Power users only! Override CPU optimization parameters. |
| |
| Enum |
| Name(aarch64_abi) Type(int) |
| Known AArch64 ABIs (for use with the -mabi= option): |
| |
| EnumValue |
| Enum(aarch64_abi) String(ilp32) Value(AARCH64_ABI_ILP32) |
| |
| EnumValue |
| Enum(aarch64_abi) String(lp64) Value(AARCH64_ABI_LP64) |
| |
| mpc-relative-literal-loads |
| Target Report Save Var(pcrelative_literal_loads) Init(2) Save |
| PC relative literal loads. |
| |
| msign-return-address= |
| Target RejectNegative Report Joined Enum(aarch64_ra_sign_scope_t) Var(aarch64_ra_sign_scope) Init(AARCH64_FUNCTION_NONE) Save |
| Select return address signing scope. |
| |
| Enum |
| Name(aarch64_ra_sign_scope_t) Type(enum aarch64_function_type) |
| Supported AArch64 return address signing scope (for use with -msign-return-address= option): |
| |
| EnumValue |
| Enum(aarch64_ra_sign_scope_t) String(none) Value(AARCH64_FUNCTION_NONE) |
| |
| EnumValue |
| Enum(aarch64_ra_sign_scope_t) String(non-leaf) Value(AARCH64_FUNCTION_NON_LEAF) |
| |
| EnumValue |
| Enum(aarch64_ra_sign_scope_t) String(all) Value(AARCH64_FUNCTION_ALL) |
| |
| mlow-precision-recip-sqrt |
| Common Var(flag_mrecip_low_precision_sqrt) Optimization |
| Enable the reciprocal square root approximation. Enabling this reduces |
| precision of reciprocal square root results to about 16 bits for |
| single precision and to 32 bits for double precision. |
| |
| mlow-precision-sqrt |
| Common Var(flag_mlow_precision_sqrt) Optimization |
| Enable the square root approximation. Enabling this reduces |
| precision of square root results to about 16 bits for |
| single precision and to 32 bits for double precision. |
| If enabled, it implies -mlow-precision-recip-sqrt. |
| |
| mlow-precision-div |
| Common Var(flag_mlow_precision_div) Optimization |
| Enable the division approximation. Enabling this reduces |
| precision of division results to about 16 bits for |
| single precision and to 32 bits for double precision. |
| |
| Enum |
| Name(sve_vector_bits) Type(enum aarch64_sve_vector_bits_enum) |
| The possible SVE vector lengths: |
| |
| EnumValue |
| Enum(sve_vector_bits) String(scalable) Value(SVE_SCALABLE) |
| |
| EnumValue |
| Enum(sve_vector_bits) String(128) Value(SVE_128) |
| |
| EnumValue |
| Enum(sve_vector_bits) String(256) Value(SVE_256) |
| |
| EnumValue |
| Enum(sve_vector_bits) String(512) Value(SVE_512) |
| |
| EnumValue |
| Enum(sve_vector_bits) String(1024) Value(SVE_1024) |
| |
| EnumValue |
| Enum(sve_vector_bits) String(2048) Value(SVE_2048) |
| |
| msve-vector-bits= |
| Target RejectNegative Joined Enum(sve_vector_bits) Var(aarch64_sve_vector_bits) Init(SVE_SCALABLE) |
| -msve-vector-bits=N Set the number of bits in an SVE vector register to N. |
| |
| mverbose-cost-dump |
| Common Undocumented Var(flag_aarch64_verbose_cost) |
| Enables verbose cost model dumping in the debug dump files. |
